2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
39 static const char radeon_family_name[][16] = {
88 * Clear GPU surface registers.
90 void radeon_surface_init(struct radeon_device *rdev)
92 /* FIXME: check this out */
93 if (rdev->family < CHIP_R600) {
96 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
97 if (rdev->surface_regs[i].bo)
98 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
100 radeon_clear_surface_reg(rdev, i);
102 /* enable surfaces */
103 WREG32(RADEON_SURFACE_CNTL, 0);
108 * GPU scratch registers helpers function.
110 void radeon_scratch_init(struct radeon_device *rdev)
114 /* FIXME: check this out */
115 if (rdev->family < CHIP_R300) {
116 rdev->scratch.num_reg = 5;
118 rdev->scratch.num_reg = 7;
120 for (i = 0; i < rdev->scratch.num_reg; i++) {
121 rdev->scratch.free[i] = true;
122 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
126 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
130 for (i = 0; i < rdev->scratch.num_reg; i++) {
131 if (rdev->scratch.free[i]) {
132 rdev->scratch.free[i] = false;
133 *reg = rdev->scratch.reg[i];
140 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
144 for (i = 0; i < rdev->scratch.num_reg; i++) {
145 if (rdev->scratch.reg[i] == reg) {
146 rdev->scratch.free[i] = true;
153 * radeon_vram_location - try to find VRAM location
154 * @rdev: radeon device structure holding all necessary informations
155 * @mc: memory controller structure holding memory informations
156 * @base: base address at which to put VRAM
158 * Function will place try to place VRAM at base address provided
159 * as parameter (which is so far either PCI aperture address or
160 * for IGP TOM base address).
162 * If there is not enough space to fit the unvisible VRAM in the 32bits
163 * address space then we limit the VRAM size to the aperture.
165 * If we are using AGP and if the AGP aperture doesn't allow us to have
166 * room for all the VRAM than we restrict the VRAM to the PCI aperture
167 * size and print a warning.
169 * This function will never fails, worst case are limiting VRAM.
171 * Note: GTT start, end, size should be initialized before calling this
172 * function on AGP platform.
174 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
175 * this shouldn't be a problem as we are using the PCI aperture as a reference.
176 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
179 * Note: we use mc_vram_size as on some board we need to program the mc to
180 * cover the whole aperture even if VRAM size is inferior to aperture size
181 * Novell bug 204882 + along with lots of ubuntu ones
183 * Note: when limiting vram it's safe to overwritte real_vram_size because
184 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
185 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
188 * Note: IGP TOM addr should be the same as the aperture addr, we don't
189 * explicitly check for that thought.
191 * FIXME: when reducing VRAM size align new size on power of 2.
193 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
195 mc->vram_start = base;
196 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
197 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
198 mc->real_vram_size = mc->aper_size;
199 mc->mc_vram_size = mc->aper_size;
201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
204 mc->real_vram_size = mc->aper_size;
205 mc->mc_vram_size = mc->aper_size;
207 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
208 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
209 mc->mc_vram_size >> 20, mc->vram_start,
210 mc->vram_end, mc->real_vram_size >> 20);
214 * radeon_gtt_location - try to find GTT location
215 * @rdev: radeon device structure holding all necessary informations
216 * @mc: memory controller structure holding memory informations
218 * Function will place try to place GTT before or after VRAM.
220 * If GTT size is bigger than space left then we ajust GTT size.
221 * Thus function will never fails.
223 * FIXME: when reducing GTT size align new size on power of 2.
225 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
227 u64 size_af, size_bf;
229 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
230 size_bf = mc->vram_start & ~mc->gtt_base_align;
231 if (size_bf > size_af) {
232 if (mc->gtt_size > size_bf) {
233 dev_warn(rdev->dev, "limiting GTT\n");
234 mc->gtt_size = size_bf;
236 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
238 if (mc->gtt_size > size_af) {
239 dev_warn(rdev->dev, "limiting GTT\n");
240 mc->gtt_size = size_af;
242 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
244 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
245 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
246 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
250 * GPU helpers function.
252 bool radeon_card_posted(struct radeon_device *rdev)
256 /* first check CRTCs */
257 if (ASIC_IS_DCE4(rdev)) {
258 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
259 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
260 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
261 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
262 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
263 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
264 if (reg & EVERGREEN_CRTC_MASTER_EN)
266 } else if (ASIC_IS_AVIVO(rdev)) {
267 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
268 RREG32(AVIVO_D2CRTC_CONTROL);
269 if (reg & AVIVO_CRTC_EN) {
273 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
274 RREG32(RADEON_CRTC2_GEN_CNTL);
275 if (reg & RADEON_CRTC_EN) {
280 /* then check MEM_SIZE, in case the crtcs are off */
281 if (rdev->family >= CHIP_R600)
282 reg = RREG32(R600_CONFIG_MEMSIZE);
284 reg = RREG32(RADEON_CONFIG_MEMSIZE);
293 void radeon_update_bandwidth_info(struct radeon_device *rdev)
296 u32 sclk = rdev->pm.current_sclk;
297 u32 mclk = rdev->pm.current_mclk;
299 /* sclk/mclk in Mhz */
300 a.full = dfixed_const(100);
301 rdev->pm.sclk.full = dfixed_const(sclk);
302 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
303 rdev->pm.mclk.full = dfixed_const(mclk);
304 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
306 if (rdev->flags & RADEON_IS_IGP) {
307 a.full = dfixed_const(16);
308 /* core_bandwidth = sclk(Mhz) * 16 */
309 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
313 bool radeon_boot_test_post_card(struct radeon_device *rdev)
315 if (radeon_card_posted(rdev))
319 DRM_INFO("GPU not posted. posting now...\n");
320 if (rdev->is_atom_bios)
321 atom_asic_init(rdev->mode_info.atom_context);
323 radeon_combios_asic_init(rdev->ddev);
326 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
331 int radeon_dummy_page_init(struct radeon_device *rdev)
333 if (rdev->dummy_page.page)
335 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
336 if (rdev->dummy_page.page == NULL)
338 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
339 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
340 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
341 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
342 __free_page(rdev->dummy_page.page);
343 rdev->dummy_page.page = NULL;
349 void radeon_dummy_page_fini(struct radeon_device *rdev)
351 if (rdev->dummy_page.page == NULL)
353 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
354 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
355 __free_page(rdev->dummy_page.page);
356 rdev->dummy_page.page = NULL;
360 /* ATOM accessor methods */
361 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
363 struct radeon_device *rdev = info->dev->dev_private;
366 r = rdev->pll_rreg(rdev, reg);
370 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
372 struct radeon_device *rdev = info->dev->dev_private;
374 rdev->pll_wreg(rdev, reg, val);
377 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
379 struct radeon_device *rdev = info->dev->dev_private;
382 r = rdev->mc_rreg(rdev, reg);
386 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
388 struct radeon_device *rdev = info->dev->dev_private;
390 rdev->mc_wreg(rdev, reg, val);
393 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
395 struct radeon_device *rdev = info->dev->dev_private;
400 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
402 struct radeon_device *rdev = info->dev->dev_private;
409 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
411 struct radeon_device *rdev = info->dev->dev_private;
413 WREG32_IO(reg*4, val);
416 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
418 struct radeon_device *rdev = info->dev->dev_private;
421 r = RREG32_IO(reg*4);
425 int radeon_atombios_init(struct radeon_device *rdev)
427 struct card_info *atom_card_info =
428 kzalloc(sizeof(struct card_info), GFP_KERNEL);
433 rdev->mode_info.atom_card_info = atom_card_info;
434 atom_card_info->dev = rdev->ddev;
435 atom_card_info->reg_read = cail_reg_read;
436 atom_card_info->reg_write = cail_reg_write;
437 /* needed for iio ops */
439 atom_card_info->ioreg_read = cail_ioreg_read;
440 atom_card_info->ioreg_write = cail_ioreg_write;
442 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
443 atom_card_info->ioreg_read = cail_reg_read;
444 atom_card_info->ioreg_write = cail_reg_write;
446 atom_card_info->mc_read = cail_mc_read;
447 atom_card_info->mc_write = cail_mc_write;
448 atom_card_info->pll_read = cail_pll_read;
449 atom_card_info->pll_write = cail_pll_write;
451 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
452 mutex_init(&rdev->mode_info.atom_context->mutex);
453 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
454 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
458 void radeon_atombios_fini(struct radeon_device *rdev)
460 if (rdev->mode_info.atom_context) {
461 kfree(rdev->mode_info.atom_context->scratch);
462 kfree(rdev->mode_info.atom_context);
464 kfree(rdev->mode_info.atom_card_info);
467 int radeon_combios_init(struct radeon_device *rdev)
469 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
473 void radeon_combios_fini(struct radeon_device *rdev)
477 /* if we get transitioned to only one device, tak VGA back */
478 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
480 struct radeon_device *rdev = cookie;
481 radeon_vga_set_state(rdev, state);
483 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
484 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
486 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
489 void radeon_check_arguments(struct radeon_device *rdev)
491 /* vramlimit must be a power of two */
492 switch (radeon_vram_limit) {
507 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
509 radeon_vram_limit = 0;
512 radeon_vram_limit = radeon_vram_limit << 20;
513 /* gtt size must be power of two and greater or equal to 32M */
514 switch (radeon_gart_size) {
518 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
520 radeon_gart_size = 512;
532 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
534 radeon_gart_size = 512;
537 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
538 /* AGP mode can only be -1, 1, 2, 4, 8 */
539 switch (radeon_agpmode) {
548 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
549 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
555 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
557 struct drm_device *dev = pci_get_drvdata(pdev);
558 struct radeon_device *rdev = dev->dev_private;
559 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
560 if (state == VGA_SWITCHEROO_ON) {
561 printk(KERN_INFO "radeon: switched on\n");
562 /* don't suspend or resume card normally */
563 rdev->powered_down = false;
564 radeon_resume_kms(dev);
565 drm_kms_helper_poll_enable(dev);
567 printk(KERN_INFO "radeon: switched off\n");
568 drm_kms_helper_poll_disable(dev);
569 radeon_suspend_kms(dev, pmm);
570 /* don't suspend or resume card normally */
571 rdev->powered_down = true;
575 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
577 struct drm_device *dev = pci_get_drvdata(pdev);
580 spin_lock(&dev->count_lock);
581 can_switch = (dev->open_count == 0);
582 spin_unlock(&dev->count_lock);
587 int radeon_device_init(struct radeon_device *rdev,
588 struct drm_device *ddev,
589 struct pci_dev *pdev,
595 rdev->shutdown = false;
596 rdev->dev = &pdev->dev;
600 rdev->family = flags & RADEON_FAMILY_MASK;
601 rdev->is_atom_bios = false;
602 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
603 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
604 rdev->gpu_lockup = false;
605 rdev->accel_working = false;
607 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
608 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
610 /* mutex initialization are all done here so we
611 * can recall function without having locking issues */
612 mutex_init(&rdev->cs_mutex);
613 mutex_init(&rdev->ib_pool.mutex);
614 mutex_init(&rdev->cp.mutex);
615 mutex_init(&rdev->dc_hw_i2c_mutex);
616 if (rdev->family >= CHIP_R600)
617 spin_lock_init(&rdev->ih.lock);
618 mutex_init(&rdev->gem.mutex);
619 mutex_init(&rdev->pm.mutex);
620 mutex_init(&rdev->vram_mutex);
621 rwlock_init(&rdev->fence_drv.lock);
622 INIT_LIST_HEAD(&rdev->gem.objects);
623 init_waitqueue_head(&rdev->irq.vblank_queue);
624 init_waitqueue_head(&rdev->irq.idle_queue);
626 /* setup workqueue */
627 rdev->wq = create_workqueue("radeon");
628 if (rdev->wq == NULL)
631 /* Set asic functions */
632 r = radeon_asic_init(rdev);
635 radeon_check_arguments(rdev);
637 /* all of the newer IGP chips have an internal gart
638 * However some rs4xx report as AGP, so remove that here.
640 if ((rdev->family >= CHIP_RS400) &&
641 (rdev->flags & RADEON_IS_IGP)) {
642 rdev->flags &= ~RADEON_IS_AGP;
645 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
646 radeon_agp_disable(rdev);
649 /* set DMA mask + need_dma32 flags.
650 * PCIE - can handle 40-bits.
651 * IGP - can handle 40-bits (in theory)
652 * AGP - generally dma32 is safest
655 rdev->need_dma32 = false;
656 if (rdev->flags & RADEON_IS_AGP)
657 rdev->need_dma32 = true;
658 if (rdev->flags & RADEON_IS_PCI)
659 rdev->need_dma32 = true;
661 dma_bits = rdev->need_dma32 ? 32 : 40;
662 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
664 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
667 /* Registers mapping */
668 /* TODO: block userspace mapping of io register */
669 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
670 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
671 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
672 if (rdev->rmmio == NULL) {
675 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
676 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
678 /* io port mapping */
679 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
680 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
681 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
682 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
686 if (rdev->rio_mem == NULL)
687 DRM_ERROR("Unable to find PCI I/O BAR\n");
689 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
690 /* this will fail for cards that aren't VGA class devices, just
692 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
693 vga_switcheroo_register_client(rdev->pdev,
694 radeon_switcheroo_set_state,
695 radeon_switcheroo_can_switch);
697 r = radeon_init(rdev);
701 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
702 /* Acceleration not working on AGP card try again
703 * with fallback to PCI or PCIE GART
705 radeon_asic_reset(rdev);
707 radeon_agp_disable(rdev);
708 r = radeon_init(rdev);
712 if (radeon_testing) {
713 radeon_test_moves(rdev);
715 if (radeon_benchmarking) {
716 radeon_benchmark(rdev);
721 void radeon_device_fini(struct radeon_device *rdev)
723 DRM_INFO("radeon: finishing device.\n");
724 rdev->shutdown = true;
725 /* evict vram memory */
726 radeon_bo_evict_vram(rdev);
728 destroy_workqueue(rdev->wq);
729 vga_switcheroo_unregister_client(rdev->pdev);
730 vga_client_register(rdev->pdev, NULL, NULL, NULL);
732 pci_iounmap(rdev->pdev, rdev->rio_mem);
733 rdev->rio_mem = NULL;
734 iounmap(rdev->rmmio);
742 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
744 struct radeon_device *rdev;
745 struct drm_crtc *crtc;
746 struct drm_connector *connector;
749 if (dev == NULL || dev->dev_private == NULL) {
752 if (state.event == PM_EVENT_PRETHAW) {
755 rdev = dev->dev_private;
757 if (rdev->powered_down)
760 /* turn off display hw */
761 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
762 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
765 /* unpin the front buffers */
766 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
767 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
768 struct radeon_bo *robj;
770 if (rfb == NULL || rfb->obj == NULL) {
773 robj = rfb->obj->driver_private;
774 /* don't unpin kernel fb objects */
775 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
776 r = radeon_bo_reserve(robj, false);
778 radeon_bo_unpin(robj);
779 radeon_bo_unreserve(robj);
783 /* evict vram memory */
784 radeon_bo_evict_vram(rdev);
785 /* wait for gpu to finish processing current batch */
786 radeon_fence_wait_last(rdev);
788 radeon_save_bios_scratch_regs(rdev);
790 radeon_pm_suspend(rdev);
791 radeon_suspend(rdev);
792 radeon_hpd_fini(rdev);
793 /* evict remaining vram memory */
794 radeon_bo_evict_vram(rdev);
796 radeon_agp_suspend(rdev);
798 pci_save_state(dev->pdev);
799 if (state.event == PM_EVENT_SUSPEND) {
800 /* Shut down the device */
801 pci_disable_device(dev->pdev);
802 pci_set_power_state(dev->pdev, PCI_D3hot);
804 acquire_console_sem();
805 radeon_fbdev_set_suspend(rdev, 1);
806 release_console_sem();
810 int radeon_resume_kms(struct drm_device *dev)
812 struct drm_connector *connector;
813 struct radeon_device *rdev = dev->dev_private;
815 if (rdev->powered_down)
818 acquire_console_sem();
819 pci_set_power_state(dev->pdev, PCI_D0);
820 pci_restore_state(dev->pdev);
821 if (pci_enable_device(dev->pdev)) {
822 release_console_sem();
825 pci_set_master(dev->pdev);
826 /* resume AGP if in use */
827 radeon_agp_resume(rdev);
829 radeon_pm_resume(rdev);
830 radeon_restore_bios_scratch_regs(rdev);
832 /* turn on display hw */
833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
834 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
837 radeon_fbdev_set_suspend(rdev, 0);
838 release_console_sem();
840 /* reset hpd state */
841 radeon_hpd_init(rdev);
842 /* blat the mode back in */
843 drm_helper_resume_force_mode(dev);
847 int radeon_gpu_reset(struct radeon_device *rdev)
851 radeon_save_bios_scratch_regs(rdev);
852 radeon_suspend(rdev);
854 r = radeon_asic_reset(rdev);
856 dev_info(rdev->dev, "GPU reset succeed\n");
858 radeon_restore_bios_scratch_regs(rdev);
859 drm_helper_resume_force_mode(rdev->ddev);
862 /* bad news, how to tell it to userspace ? */
863 dev_info(rdev->dev, "GPU reset failed\n");
871 struct radeon_debugfs {
872 struct drm_info_list *files;
875 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
876 static unsigned _radeon_debugfs_count = 0;
878 int radeon_debugfs_add_files(struct radeon_device *rdev,
879 struct drm_info_list *files,
884 for (i = 0; i < _radeon_debugfs_count; i++) {
885 if (_radeon_debugfs[i].files == files) {
886 /* Already registered */
890 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
891 DRM_ERROR("Reached maximum number of debugfs files.\n");
892 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
895 _radeon_debugfs[_radeon_debugfs_count].files = files;
896 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
897 _radeon_debugfs_count++;
898 #if defined(CONFIG_DEBUG_FS)
899 drm_debugfs_create_files(files, nfiles,
900 rdev->ddev->control->debugfs_root,
901 rdev->ddev->control);
902 drm_debugfs_create_files(files, nfiles,
903 rdev->ddev->primary->debugfs_root,
904 rdev->ddev->primary);
909 #if defined(CONFIG_DEBUG_FS)
910 int radeon_debugfs_init(struct drm_minor *minor)
915 void radeon_debugfs_cleanup(struct drm_minor *minor)
919 for (i = 0; i < _radeon_debugfs_count; i++) {
920 drm_debugfs_remove_files(_radeon_debugfs[i].files,
921 _radeon_debugfs[i].num_files, minor);