2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
105 #if defined(CONFIG_VGA_SWITCHEROO)
106 bool radeon_is_px(void);
108 static inline bool radeon_is_px(void) { return false; }
112 * radeon_program_register_sequence - program an array of registers.
114 * @rdev: radeon_device pointer
115 * @registers: pointer to the register array
116 * @array_size: size of the register array
118 * Programs an array or registers with and and or masks.
119 * This is a helper for setting golden registers.
121 void radeon_program_register_sequence(struct radeon_device *rdev,
122 const u32 *registers,
123 const u32 array_size)
125 u32 tmp, reg, and_mask, or_mask;
131 for (i = 0; i < array_size; i +=3) {
132 reg = registers[i + 0];
133 and_mask = registers[i + 1];
134 or_mask = registers[i + 2];
136 if (and_mask == 0xffffffff) {
147 void radeon_pci_config_reset(struct radeon_device *rdev)
149 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
153 * radeon_surface_init - Clear GPU surface registers.
155 * @rdev: radeon_device pointer
157 * Clear GPU surface registers (r1xx-r5xx).
159 void radeon_surface_init(struct radeon_device *rdev)
161 /* FIXME: check this out */
162 if (rdev->family < CHIP_R600) {
165 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
166 if (rdev->surface_regs[i].bo)
167 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
169 radeon_clear_surface_reg(rdev, i);
171 /* enable surfaces */
172 WREG32(RADEON_SURFACE_CNTL, 0);
177 * GPU scratch registers helpers function.
180 * radeon_scratch_init - Init scratch register driver information.
182 * @rdev: radeon_device pointer
184 * Init CP scratch register driver information (r1xx-r5xx)
186 void radeon_scratch_init(struct radeon_device *rdev)
190 /* FIXME: check this out */
191 if (rdev->family < CHIP_R300) {
192 rdev->scratch.num_reg = 5;
194 rdev->scratch.num_reg = 7;
196 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
197 for (i = 0; i < rdev->scratch.num_reg; i++) {
198 rdev->scratch.free[i] = true;
199 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
204 * radeon_scratch_get - Allocate a scratch register
206 * @rdev: radeon_device pointer
207 * @reg: scratch register mmio offset
209 * Allocate a CP scratch register for use by the driver (all asics).
210 * Returns 0 on success or -EINVAL on failure.
212 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
216 for (i = 0; i < rdev->scratch.num_reg; i++) {
217 if (rdev->scratch.free[i]) {
218 rdev->scratch.free[i] = false;
219 *reg = rdev->scratch.reg[i];
227 * radeon_scratch_free - Free a scratch register
229 * @rdev: radeon_device pointer
230 * @reg: scratch register mmio offset
232 * Free a CP scratch register allocated for use by the driver (all asics)
234 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
238 for (i = 0; i < rdev->scratch.num_reg; i++) {
239 if (rdev->scratch.reg[i] == reg) {
240 rdev->scratch.free[i] = true;
247 * GPU doorbell aperture helpers function.
250 * radeon_doorbell_init - Init doorbell driver information.
252 * @rdev: radeon_device pointer
254 * Init doorbell driver information (CIK)
255 * Returns 0 on success, error on failure.
257 static int radeon_doorbell_init(struct radeon_device *rdev)
259 /* doorbell bar mapping */
260 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
261 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
263 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
264 if (rdev->doorbell.num_doorbells == 0)
267 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
268 if (rdev->doorbell.ptr == NULL) {
271 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
272 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
274 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
280 * radeon_doorbell_fini - Tear down doorbell driver information.
282 * @rdev: radeon_device pointer
284 * Tear down doorbell driver information (CIK)
286 static void radeon_doorbell_fini(struct radeon_device *rdev)
288 iounmap(rdev->doorbell.ptr);
289 rdev->doorbell.ptr = NULL;
293 * radeon_doorbell_get - Allocate a doorbell entry
295 * @rdev: radeon_device pointer
296 * @doorbell: doorbell index
298 * Allocate a doorbell for use by the driver (all asics).
299 * Returns 0 on success or -EINVAL on failure.
301 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
303 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
304 if (offset < rdev->doorbell.num_doorbells) {
305 __set_bit(offset, rdev->doorbell.used);
314 * radeon_doorbell_free - Free a doorbell entry
316 * @rdev: radeon_device pointer
317 * @doorbell: doorbell index
319 * Free a doorbell allocated for use by the driver (all asics)
321 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
323 if (doorbell < rdev->doorbell.num_doorbells)
324 __clear_bit(doorbell, rdev->doorbell.used);
329 * Writeback is the the method by which the the GPU updates special pages
330 * in memory with the status of certain GPU events (fences, ring pointers,
335 * radeon_wb_disable - Disable Writeback
337 * @rdev: radeon_device pointer
339 * Disables Writeback (all asics). Used for suspend.
341 void radeon_wb_disable(struct radeon_device *rdev)
343 rdev->wb.enabled = false;
347 * radeon_wb_fini - Disable Writeback and free memory
349 * @rdev: radeon_device pointer
351 * Disables Writeback and frees the Writeback memory (all asics).
352 * Used at driver shutdown.
354 void radeon_wb_fini(struct radeon_device *rdev)
356 radeon_wb_disable(rdev);
357 if (rdev->wb.wb_obj) {
358 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
359 radeon_bo_kunmap(rdev->wb.wb_obj);
360 radeon_bo_unpin(rdev->wb.wb_obj);
361 radeon_bo_unreserve(rdev->wb.wb_obj);
363 radeon_bo_unref(&rdev->wb.wb_obj);
365 rdev->wb.wb_obj = NULL;
370 * radeon_wb_init- Init Writeback driver info and allocate memory
372 * @rdev: radeon_device pointer
374 * Disables Writeback and frees the Writeback memory (all asics).
375 * Used at driver startup.
376 * Returns 0 on success or an -error on failure.
378 int radeon_wb_init(struct radeon_device *rdev)
382 if (rdev->wb.wb_obj == NULL) {
383 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
384 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
386 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
389 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
390 if (unlikely(r != 0)) {
391 radeon_wb_fini(rdev);
394 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
397 radeon_bo_unreserve(rdev->wb.wb_obj);
398 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
399 radeon_wb_fini(rdev);
402 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
403 radeon_bo_unreserve(rdev->wb.wb_obj);
405 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
406 radeon_wb_fini(rdev);
411 /* clear wb memory */
412 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
413 /* disable event_write fences */
414 rdev->wb.use_event = false;
415 /* disabled via module param */
416 if (radeon_no_wb == 1) {
417 rdev->wb.enabled = false;
419 if (rdev->flags & RADEON_IS_AGP) {
420 /* often unreliable on AGP */
421 rdev->wb.enabled = false;
422 } else if (rdev->family < CHIP_R300) {
423 /* often unreliable on pre-r300 */
424 rdev->wb.enabled = false;
426 rdev->wb.enabled = true;
427 /* event_write fences are only available on r600+ */
428 if (rdev->family >= CHIP_R600) {
429 rdev->wb.use_event = true;
433 /* always use writeback/events on NI, APUs */
434 if (rdev->family >= CHIP_PALM) {
435 rdev->wb.enabled = true;
436 rdev->wb.use_event = true;
439 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
445 * radeon_vram_location - try to find VRAM location
446 * @rdev: radeon device structure holding all necessary informations
447 * @mc: memory controller structure holding memory informations
448 * @base: base address at which to put VRAM
450 * Function will place try to place VRAM at base address provided
451 * as parameter (which is so far either PCI aperture address or
452 * for IGP TOM base address).
454 * If there is not enough space to fit the unvisible VRAM in the 32bits
455 * address space then we limit the VRAM size to the aperture.
457 * If we are using AGP and if the AGP aperture doesn't allow us to have
458 * room for all the VRAM than we restrict the VRAM to the PCI aperture
459 * size and print a warning.
461 * This function will never fails, worst case are limiting VRAM.
463 * Note: GTT start, end, size should be initialized before calling this
464 * function on AGP platform.
466 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
467 * this shouldn't be a problem as we are using the PCI aperture as a reference.
468 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
471 * Note: we use mc_vram_size as on some board we need to program the mc to
472 * cover the whole aperture even if VRAM size is inferior to aperture size
473 * Novell bug 204882 + along with lots of ubuntu ones
475 * Note: when limiting vram it's safe to overwritte real_vram_size because
476 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
477 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
480 * Note: IGP TOM addr should be the same as the aperture addr, we don't
481 * explicitly check for that thought.
483 * FIXME: when reducing VRAM size align new size on power of 2.
485 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
487 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
489 mc->vram_start = base;
490 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
491 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
492 mc->real_vram_size = mc->aper_size;
493 mc->mc_vram_size = mc->aper_size;
495 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
496 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
497 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
498 mc->real_vram_size = mc->aper_size;
499 mc->mc_vram_size = mc->aper_size;
501 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
502 if (limit && limit < mc->real_vram_size)
503 mc->real_vram_size = limit;
504 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
505 mc->mc_vram_size >> 20, mc->vram_start,
506 mc->vram_end, mc->real_vram_size >> 20);
510 * radeon_gtt_location - try to find GTT location
511 * @rdev: radeon device structure holding all necessary informations
512 * @mc: memory controller structure holding memory informations
514 * Function will place try to place GTT before or after VRAM.
516 * If GTT size is bigger than space left then we ajust GTT size.
517 * Thus function will never fails.
519 * FIXME: when reducing GTT size align new size on power of 2.
521 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
523 u64 size_af, size_bf;
525 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
526 size_bf = mc->vram_start & ~mc->gtt_base_align;
527 if (size_bf > size_af) {
528 if (mc->gtt_size > size_bf) {
529 dev_warn(rdev->dev, "limiting GTT\n");
530 mc->gtt_size = size_bf;
532 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
534 if (mc->gtt_size > size_af) {
535 dev_warn(rdev->dev, "limiting GTT\n");
536 mc->gtt_size = size_af;
538 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
540 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
541 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
542 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
546 * GPU helpers function.
549 * radeon_card_posted - check if the hw has already been initialized
551 * @rdev: radeon_device pointer
553 * Check if the asic has been initialized (all asics).
554 * Used at driver startup.
555 * Returns true if initialized or false if not.
557 bool radeon_card_posted(struct radeon_device *rdev)
561 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
562 if (efi_enabled(EFI_BOOT) &&
563 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
564 (rdev->family < CHIP_R600))
567 if (ASIC_IS_NODCE(rdev))
570 /* first check CRTCs */
571 if (ASIC_IS_DCE4(rdev)) {
572 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
573 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
574 if (rdev->num_crtc >= 4) {
575 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
576 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
578 if (rdev->num_crtc >= 6) {
579 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
580 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
582 if (reg & EVERGREEN_CRTC_MASTER_EN)
584 } else if (ASIC_IS_AVIVO(rdev)) {
585 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
586 RREG32(AVIVO_D2CRTC_CONTROL);
587 if (reg & AVIVO_CRTC_EN) {
591 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
592 RREG32(RADEON_CRTC2_GEN_CNTL);
593 if (reg & RADEON_CRTC_EN) {
599 /* then check MEM_SIZE, in case the crtcs are off */
600 if (rdev->family >= CHIP_R600)
601 reg = RREG32(R600_CONFIG_MEMSIZE);
603 reg = RREG32(RADEON_CONFIG_MEMSIZE);
613 * radeon_update_bandwidth_info - update display bandwidth params
615 * @rdev: radeon_device pointer
617 * Used when sclk/mclk are switched or display modes are set.
618 * params are used to calculate display watermarks (all asics)
620 void radeon_update_bandwidth_info(struct radeon_device *rdev)
623 u32 sclk = rdev->pm.current_sclk;
624 u32 mclk = rdev->pm.current_mclk;
626 /* sclk/mclk in Mhz */
627 a.full = dfixed_const(100);
628 rdev->pm.sclk.full = dfixed_const(sclk);
629 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
630 rdev->pm.mclk.full = dfixed_const(mclk);
631 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
633 if (rdev->flags & RADEON_IS_IGP) {
634 a.full = dfixed_const(16);
635 /* core_bandwidth = sclk(Mhz) * 16 */
636 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
641 * radeon_boot_test_post_card - check and possibly initialize the hw
643 * @rdev: radeon_device pointer
645 * Check if the asic is initialized and if not, attempt to initialize
647 * Returns true if initialized or false if not.
649 bool radeon_boot_test_post_card(struct radeon_device *rdev)
651 if (radeon_card_posted(rdev))
655 DRM_INFO("GPU not posted. posting now...\n");
656 if (rdev->is_atom_bios)
657 atom_asic_init(rdev->mode_info.atom_context);
659 radeon_combios_asic_init(rdev->ddev);
662 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
668 * radeon_dummy_page_init - init dummy page used by the driver
670 * @rdev: radeon_device pointer
672 * Allocate the dummy page used by the driver (all asics).
673 * This dummy page is used by the driver as a filler for gart entries
674 * when pages are taken out of the GART
675 * Returns 0 on sucess, -ENOMEM on failure.
677 int radeon_dummy_page_init(struct radeon_device *rdev)
679 if (rdev->dummy_page.page)
681 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
682 if (rdev->dummy_page.page == NULL)
684 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
685 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
686 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
687 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
688 __free_page(rdev->dummy_page.page);
689 rdev->dummy_page.page = NULL;
696 * radeon_dummy_page_fini - free dummy page used by the driver
698 * @rdev: radeon_device pointer
700 * Frees the dummy page used by the driver (all asics).
702 void radeon_dummy_page_fini(struct radeon_device *rdev)
704 if (rdev->dummy_page.page == NULL)
706 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
707 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
708 __free_page(rdev->dummy_page.page);
709 rdev->dummy_page.page = NULL;
713 /* ATOM accessor methods */
715 * ATOM is an interpreted byte code stored in tables in the vbios. The
716 * driver registers callbacks to access registers and the interpreter
717 * in the driver parses the tables and executes then to program specific
718 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
719 * atombios.h, and atom.c
723 * cail_pll_read - read PLL register
725 * @info: atom card_info pointer
726 * @reg: PLL register offset
728 * Provides a PLL register accessor for the atom interpreter (r4xx+).
729 * Returns the value of the PLL register.
731 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
733 struct radeon_device *rdev = info->dev->dev_private;
736 r = rdev->pll_rreg(rdev, reg);
741 * cail_pll_write - write PLL register
743 * @info: atom card_info pointer
744 * @reg: PLL register offset
745 * @val: value to write to the pll register
747 * Provides a PLL register accessor for the atom interpreter (r4xx+).
749 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
751 struct radeon_device *rdev = info->dev->dev_private;
753 rdev->pll_wreg(rdev, reg, val);
757 * cail_mc_read - read MC (Memory Controller) register
759 * @info: atom card_info pointer
760 * @reg: MC register offset
762 * Provides an MC register accessor for the atom interpreter (r4xx+).
763 * Returns the value of the MC register.
765 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
767 struct radeon_device *rdev = info->dev->dev_private;
770 r = rdev->mc_rreg(rdev, reg);
775 * cail_mc_write - write MC (Memory Controller) register
777 * @info: atom card_info pointer
778 * @reg: MC register offset
779 * @val: value to write to the pll register
781 * Provides a MC register accessor for the atom interpreter (r4xx+).
783 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
785 struct radeon_device *rdev = info->dev->dev_private;
787 rdev->mc_wreg(rdev, reg, val);
791 * cail_reg_write - write MMIO register
793 * @info: atom card_info pointer
794 * @reg: MMIO register offset
795 * @val: value to write to the pll register
797 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
799 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
801 struct radeon_device *rdev = info->dev->dev_private;
807 * cail_reg_read - read MMIO register
809 * @info: atom card_info pointer
810 * @reg: MMIO register offset
812 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
813 * Returns the value of the MMIO register.
815 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
817 struct radeon_device *rdev = info->dev->dev_private;
825 * cail_ioreg_write - write IO register
827 * @info: atom card_info pointer
828 * @reg: IO register offset
829 * @val: value to write to the pll register
831 * Provides a IO register accessor for the atom interpreter (r4xx+).
833 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
835 struct radeon_device *rdev = info->dev->dev_private;
837 WREG32_IO(reg*4, val);
841 * cail_ioreg_read - read IO register
843 * @info: atom card_info pointer
844 * @reg: IO register offset
846 * Provides an IO register accessor for the atom interpreter (r4xx+).
847 * Returns the value of the IO register.
849 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
851 struct radeon_device *rdev = info->dev->dev_private;
854 r = RREG32_IO(reg*4);
859 * radeon_atombios_init - init the driver info and callbacks for atombios
861 * @rdev: radeon_device pointer
863 * Initializes the driver info and register access callbacks for the
864 * ATOM interpreter (r4xx+).
865 * Returns 0 on sucess, -ENOMEM on failure.
866 * Called at driver startup.
868 int radeon_atombios_init(struct radeon_device *rdev)
870 struct card_info *atom_card_info =
871 kzalloc(sizeof(struct card_info), GFP_KERNEL);
876 rdev->mode_info.atom_card_info = atom_card_info;
877 atom_card_info->dev = rdev->ddev;
878 atom_card_info->reg_read = cail_reg_read;
879 atom_card_info->reg_write = cail_reg_write;
880 /* needed for iio ops */
882 atom_card_info->ioreg_read = cail_ioreg_read;
883 atom_card_info->ioreg_write = cail_ioreg_write;
885 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
886 atom_card_info->ioreg_read = cail_reg_read;
887 atom_card_info->ioreg_write = cail_reg_write;
889 atom_card_info->mc_read = cail_mc_read;
890 atom_card_info->mc_write = cail_mc_write;
891 atom_card_info->pll_read = cail_pll_read;
892 atom_card_info->pll_write = cail_pll_write;
894 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
895 if (!rdev->mode_info.atom_context) {
896 radeon_atombios_fini(rdev);
900 mutex_init(&rdev->mode_info.atom_context->mutex);
901 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
902 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
907 * radeon_atombios_fini - free the driver info and callbacks for atombios
909 * @rdev: radeon_device pointer
911 * Frees the driver info and register access callbacks for the ATOM
912 * interpreter (r4xx+).
913 * Called at driver shutdown.
915 void radeon_atombios_fini(struct radeon_device *rdev)
917 if (rdev->mode_info.atom_context) {
918 kfree(rdev->mode_info.atom_context->scratch);
920 kfree(rdev->mode_info.atom_context);
921 rdev->mode_info.atom_context = NULL;
922 kfree(rdev->mode_info.atom_card_info);
923 rdev->mode_info.atom_card_info = NULL;
928 * COMBIOS is the bios format prior to ATOM. It provides
929 * command tables similar to ATOM, but doesn't have a unified
930 * parser. See radeon_combios.c
934 * radeon_combios_init - init the driver info for combios
936 * @rdev: radeon_device pointer
938 * Initializes the driver info for combios (r1xx-r3xx).
939 * Returns 0 on sucess.
940 * Called at driver startup.
942 int radeon_combios_init(struct radeon_device *rdev)
944 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
949 * radeon_combios_fini - free the driver info for combios
951 * @rdev: radeon_device pointer
953 * Frees the driver info for combios (r1xx-r3xx).
954 * Called at driver shutdown.
956 void radeon_combios_fini(struct radeon_device *rdev)
960 /* if we get transitioned to only one device, take VGA back */
962 * radeon_vga_set_decode - enable/disable vga decode
964 * @cookie: radeon_device pointer
965 * @state: enable/disable vga decode
967 * Enable/disable vga decode (all asics).
968 * Returns VGA resource flags.
970 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
972 struct radeon_device *rdev = cookie;
973 radeon_vga_set_state(rdev, state);
975 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
976 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
978 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
982 * radeon_check_pot_argument - check that argument is a power of two
984 * @arg: value to check
986 * Validates that a certain argument is a power of two (all asics).
987 * Returns true if argument is valid.
989 static bool radeon_check_pot_argument(int arg)
991 return (arg & (arg - 1)) == 0;
995 * radeon_check_arguments - validate module params
997 * @rdev: radeon_device pointer
999 * Validates certain module parameters and updates
1000 * the associated values used by the driver (all asics).
1002 static void radeon_check_arguments(struct radeon_device *rdev)
1004 /* vramlimit must be a power of two */
1005 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1006 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1008 radeon_vram_limit = 0;
1011 if (radeon_gart_size == -1) {
1012 /* default to a larger gart size on newer asics */
1013 if (rdev->family >= CHIP_RV770)
1014 radeon_gart_size = 1024;
1016 radeon_gart_size = 512;
1018 /* gtt size must be power of two and greater or equal to 32M */
1019 if (radeon_gart_size < 32) {
1020 dev_warn(rdev->dev, "gart size (%d) too small\n",
1022 if (rdev->family >= CHIP_RV770)
1023 radeon_gart_size = 1024;
1025 radeon_gart_size = 512;
1026 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1027 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1029 if (rdev->family >= CHIP_RV770)
1030 radeon_gart_size = 1024;
1032 radeon_gart_size = 512;
1034 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1036 /* AGP mode can only be -1, 1, 2, 4, 8 */
1037 switch (radeon_agpmode) {
1046 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1047 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1054 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1055 * needed for waking up.
1057 * @pdev: pci dev pointer
1059 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1062 /* 6600m in a macbook pro */
1063 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1064 pdev->subsystem_device == 0x00e2) {
1065 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1073 * radeon_switcheroo_set_state - set switcheroo state
1075 * @pdev: pci dev pointer
1076 * @state: vga switcheroo state
1078 * Callback for the switcheroo driver. Suspends or resumes the
1079 * the asics before or after it is powered up using ACPI methods.
1081 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1083 struct drm_device *dev = pci_get_drvdata(pdev);
1085 if (radeon_is_px() && state == VGA_SWITCHEROO_OFF)
1088 if (state == VGA_SWITCHEROO_ON) {
1089 unsigned d3_delay = dev->pdev->d3_delay;
1091 printk(KERN_INFO "radeon: switched on\n");
1092 /* don't suspend or resume card normally */
1093 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1095 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1096 dev->pdev->d3_delay = 20;
1098 radeon_resume_kms(dev, true, true);
1100 dev->pdev->d3_delay = d3_delay;
1102 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1103 drm_kms_helper_poll_enable(dev);
1105 printk(KERN_INFO "radeon: switched off\n");
1106 drm_kms_helper_poll_disable(dev);
1107 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1108 radeon_suspend_kms(dev, true, true);
1109 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1114 * radeon_switcheroo_can_switch - see if switcheroo state can change
1116 * @pdev: pci dev pointer
1118 * Callback for the switcheroo driver. Check of the switcheroo
1119 * state can be changed.
1120 * Returns true if the state can be changed, false if not.
1122 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1124 struct drm_device *dev = pci_get_drvdata(pdev);
1127 spin_lock(&dev->count_lock);
1128 can_switch = (dev->open_count == 0);
1129 spin_unlock(&dev->count_lock);
1133 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1134 .set_gpu_state = radeon_switcheroo_set_state,
1136 .can_switch = radeon_switcheroo_can_switch,
1140 * radeon_device_init - initialize the driver
1142 * @rdev: radeon_device pointer
1143 * @pdev: drm dev pointer
1144 * @pdev: pci dev pointer
1145 * @flags: driver flags
1147 * Initializes the driver info and hw (all asics).
1148 * Returns 0 for success or an error on failure.
1149 * Called at driver startup.
1151 int radeon_device_init(struct radeon_device *rdev,
1152 struct drm_device *ddev,
1153 struct pci_dev *pdev,
1158 bool runtime = false;
1160 rdev->shutdown = false;
1161 rdev->dev = &pdev->dev;
1164 rdev->flags = flags;
1165 rdev->family = flags & RADEON_FAMILY_MASK;
1166 rdev->is_atom_bios = false;
1167 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1168 rdev->mc.gtt_size = 512 * 1024 * 1024;
1169 rdev->accel_working = false;
1170 /* set up ring ids */
1171 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1172 rdev->ring[i].idx = i;
1175 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1176 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1177 pdev->subsystem_vendor, pdev->subsystem_device);
1179 /* mutex initialization are all done here so we
1180 * can recall function without having locking issues */
1181 mutex_init(&rdev->ring_lock);
1182 mutex_init(&rdev->dc_hw_i2c_mutex);
1183 atomic_set(&rdev->ih.lock, 0);
1184 mutex_init(&rdev->gem.mutex);
1185 mutex_init(&rdev->pm.mutex);
1186 mutex_init(&rdev->gpu_clock_mutex);
1187 mutex_init(&rdev->srbm_mutex);
1188 init_rwsem(&rdev->pm.mclk_lock);
1189 init_rwsem(&rdev->exclusive_lock);
1190 init_waitqueue_head(&rdev->irq.vblank_queue);
1191 r = radeon_gem_init(rdev);
1195 /* Adjust VM size here.
1196 * Currently set to 4GB ((1 << 20) 4k pages).
1197 * Max GPUVM size for cayman and SI is 40 bits.
1199 rdev->vm_manager.max_pfn = 1 << 20;
1201 /* Set asic functions */
1202 r = radeon_asic_init(rdev);
1205 radeon_check_arguments(rdev);
1207 /* all of the newer IGP chips have an internal gart
1208 * However some rs4xx report as AGP, so remove that here.
1210 if ((rdev->family >= CHIP_RS400) &&
1211 (rdev->flags & RADEON_IS_IGP)) {
1212 rdev->flags &= ~RADEON_IS_AGP;
1215 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1216 radeon_agp_disable(rdev);
1219 /* Set the internal MC address mask
1220 * This is the max address of the GPU's
1221 * internal address space.
1223 if (rdev->family >= CHIP_CAYMAN)
1224 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1225 else if (rdev->family >= CHIP_CEDAR)
1226 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1228 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1230 /* set DMA mask + need_dma32 flags.
1231 * PCIE - can handle 40-bits.
1232 * IGP - can handle 40-bits
1233 * AGP - generally dma32 is safest
1234 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1236 rdev->need_dma32 = false;
1237 if (rdev->flags & RADEON_IS_AGP)
1238 rdev->need_dma32 = true;
1239 if ((rdev->flags & RADEON_IS_PCI) &&
1240 (rdev->family <= CHIP_RS740))
1241 rdev->need_dma32 = true;
1243 dma_bits = rdev->need_dma32 ? 32 : 40;
1244 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1246 rdev->need_dma32 = true;
1248 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1250 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1252 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1253 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1256 /* Registers mapping */
1257 /* TODO: block userspace mapping of io register */
1258 spin_lock_init(&rdev->mmio_idx_lock);
1259 spin_lock_init(&rdev->smc_idx_lock);
1260 spin_lock_init(&rdev->pll_idx_lock);
1261 spin_lock_init(&rdev->mc_idx_lock);
1262 spin_lock_init(&rdev->pcie_idx_lock);
1263 spin_lock_init(&rdev->pciep_idx_lock);
1264 spin_lock_init(&rdev->pif_idx_lock);
1265 spin_lock_init(&rdev->cg_idx_lock);
1266 spin_lock_init(&rdev->uvd_idx_lock);
1267 spin_lock_init(&rdev->rcu_idx_lock);
1268 spin_lock_init(&rdev->didt_idx_lock);
1269 spin_lock_init(&rdev->end_idx_lock);
1270 if (rdev->family >= CHIP_BONAIRE) {
1271 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1272 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1274 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1275 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1277 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1278 if (rdev->rmmio == NULL) {
1281 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1282 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1284 /* doorbell bar mapping */
1285 if (rdev->family >= CHIP_BONAIRE)
1286 radeon_doorbell_init(rdev);
1288 /* io port mapping */
1289 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1290 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1291 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1292 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1296 if (rdev->rio_mem == NULL)
1297 DRM_ERROR("Unable to find PCI I/O BAR\n");
1299 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1300 /* this will fail for cards that aren't VGA class devices, just
1302 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1304 if (radeon_runtime_pm == 1)
1306 if ((radeon_runtime_pm == -1) && radeon_is_px())
1308 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1310 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1312 r = radeon_init(rdev);
1316 r = radeon_ib_ring_tests(rdev);
1318 DRM_ERROR("ib ring test failed (%d).\n", r);
1320 r = radeon_gem_debugfs_init(rdev);
1322 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1325 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1326 /* Acceleration not working on AGP card try again
1327 * with fallback to PCI or PCIE GART
1329 radeon_asic_reset(rdev);
1331 radeon_agp_disable(rdev);
1332 r = radeon_init(rdev);
1337 if ((radeon_testing & 1)) {
1338 if (rdev->accel_working)
1339 radeon_test_moves(rdev);
1341 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1343 if ((radeon_testing & 2)) {
1344 if (rdev->accel_working)
1345 radeon_test_syncing(rdev);
1347 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1349 if (radeon_benchmarking) {
1350 if (rdev->accel_working)
1351 radeon_benchmark(rdev, radeon_benchmarking);
1353 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1358 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1361 * radeon_device_fini - tear down the driver
1363 * @rdev: radeon_device pointer
1365 * Tear down the driver info (all asics).
1366 * Called at driver shutdown.
1368 void radeon_device_fini(struct radeon_device *rdev)
1370 DRM_INFO("radeon: finishing device.\n");
1371 rdev->shutdown = true;
1372 /* evict vram memory */
1373 radeon_bo_evict_vram(rdev);
1375 vga_switcheroo_unregister_client(rdev->pdev);
1376 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1378 pci_iounmap(rdev->pdev, rdev->rio_mem);
1379 rdev->rio_mem = NULL;
1380 iounmap(rdev->rmmio);
1382 if (rdev->family >= CHIP_BONAIRE)
1383 radeon_doorbell_fini(rdev);
1384 radeon_debugfs_remove_files(rdev);
1392 * radeon_suspend_kms - initiate device suspend
1394 * @pdev: drm dev pointer
1395 * @state: suspend state
1397 * Puts the hw in the suspend state (all asics).
1398 * Returns 0 for success or an error on failure.
1399 * Called at driver suspend.
1401 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1403 struct radeon_device *rdev;
1404 struct drm_crtc *crtc;
1405 struct drm_connector *connector;
1407 bool force_completion = false;
1409 if (dev == NULL || dev->dev_private == NULL) {
1413 rdev = dev->dev_private;
1415 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1418 drm_kms_helper_poll_disable(dev);
1420 /* turn off display hw */
1421 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1422 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1425 /* unpin the front buffers */
1426 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1427 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1428 struct radeon_bo *robj;
1430 if (rfb == NULL || rfb->obj == NULL) {
1433 robj = gem_to_radeon_bo(rfb->obj);
1434 /* don't unpin kernel fb objects */
1435 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1436 r = radeon_bo_reserve(robj, false);
1438 radeon_bo_unpin(robj);
1439 radeon_bo_unreserve(robj);
1443 /* evict vram memory */
1444 radeon_bo_evict_vram(rdev);
1446 /* wait for gpu to finish processing current batch */
1447 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1448 r = radeon_fence_wait_empty(rdev, i);
1450 /* delay GPU reset to resume */
1451 force_completion = true;
1454 if (force_completion) {
1455 radeon_fence_driver_force_completion(rdev);
1458 radeon_save_bios_scratch_regs(rdev);
1460 radeon_suspend(rdev);
1461 radeon_hpd_fini(rdev);
1462 /* evict remaining vram memory */
1463 radeon_bo_evict_vram(rdev);
1465 radeon_agp_suspend(rdev);
1467 pci_save_state(dev->pdev);
1469 /* Shut down the device */
1470 pci_disable_device(dev->pdev);
1471 pci_set_power_state(dev->pdev, PCI_D3hot);
1476 radeon_fbdev_set_suspend(rdev, 1);
1483 * radeon_resume_kms - initiate device resume
1485 * @pdev: drm dev pointer
1487 * Bring the hw back to operating state (all asics).
1488 * Returns 0 for success or an error on failure.
1489 * Called at driver resume.
1491 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1493 struct drm_connector *connector;
1494 struct radeon_device *rdev = dev->dev_private;
1497 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1504 pci_set_power_state(dev->pdev, PCI_D0);
1505 pci_restore_state(dev->pdev);
1506 if (pci_enable_device(dev->pdev)) {
1512 /* resume AGP if in use */
1513 radeon_agp_resume(rdev);
1514 radeon_resume(rdev);
1516 r = radeon_ib_ring_tests(rdev);
1518 DRM_ERROR("ib ring test failed (%d).\n", r);
1520 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1521 /* do dpm late init */
1522 r = radeon_pm_late_init(rdev);
1524 rdev->pm.dpm_enabled = false;
1525 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1528 /* resume old pm late */
1529 radeon_pm_resume(rdev);
1532 radeon_restore_bios_scratch_regs(rdev);
1535 radeon_fbdev_set_suspend(rdev, 0);
1539 /* init dig PHYs, disp eng pll */
1540 if (rdev->is_atom_bios) {
1541 radeon_atom_encoder_init(rdev);
1542 radeon_atom_disp_eng_pll_init(rdev);
1543 /* turn on the BL */
1544 if (rdev->mode_info.bl_encoder) {
1545 u8 bl_level = radeon_get_backlight_level(rdev,
1546 rdev->mode_info.bl_encoder);
1547 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1551 /* reset hpd state */
1552 radeon_hpd_init(rdev);
1553 /* blat the mode back in */
1555 drm_helper_resume_force_mode(dev);
1556 /* turn on display hw */
1557 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1558 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1562 drm_kms_helper_poll_enable(dev);
1567 * radeon_gpu_reset - reset the asic
1569 * @rdev: radeon device pointer
1571 * Attempt the reset the GPU if it has hung (all asics).
1572 * Returns 0 for success or an error on failure.
1574 int radeon_gpu_reset(struct radeon_device *rdev)
1576 unsigned ring_sizes[RADEON_NUM_RINGS];
1577 uint32_t *ring_data[RADEON_NUM_RINGS];
1584 down_write(&rdev->exclusive_lock);
1586 if (!rdev->needs_reset) {
1587 up_write(&rdev->exclusive_lock);
1591 rdev->needs_reset = false;
1593 radeon_save_bios_scratch_regs(rdev);
1595 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1596 radeon_pm_suspend(rdev);
1597 radeon_suspend(rdev);
1599 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1600 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1602 if (ring_sizes[i]) {
1604 dev_info(rdev->dev, "Saved %d dwords of commands "
1605 "on ring %d.\n", ring_sizes[i], i);
1610 r = radeon_asic_reset(rdev);
1612 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1613 radeon_resume(rdev);
1616 radeon_restore_bios_scratch_regs(rdev);
1619 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1620 radeon_ring_restore(rdev, &rdev->ring[i],
1621 ring_sizes[i], ring_data[i]);
1623 ring_data[i] = NULL;
1626 r = radeon_ib_ring_tests(rdev);
1628 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1631 radeon_suspend(rdev);
1636 radeon_fence_driver_force_completion(rdev);
1637 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1638 kfree(ring_data[i]);
1642 radeon_pm_resume(rdev);
1643 drm_helper_resume_force_mode(rdev->ddev);
1645 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1647 /* bad news, how to tell it to userspace ? */
1648 dev_info(rdev->dev, "GPU reset failed\n");
1651 up_write(&rdev->exclusive_lock);
1659 int radeon_debugfs_add_files(struct radeon_device *rdev,
1660 struct drm_info_list *files,
1665 for (i = 0; i < rdev->debugfs_count; i++) {
1666 if (rdev->debugfs[i].files == files) {
1667 /* Already registered */
1672 i = rdev->debugfs_count + 1;
1673 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1674 DRM_ERROR("Reached maximum number of debugfs components.\n");
1675 DRM_ERROR("Report so we increase "
1676 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1679 rdev->debugfs[rdev->debugfs_count].files = files;
1680 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1681 rdev->debugfs_count = i;
1682 #if defined(CONFIG_DEBUG_FS)
1683 drm_debugfs_create_files(files, nfiles,
1684 rdev->ddev->control->debugfs_root,
1685 rdev->ddev->control);
1686 drm_debugfs_create_files(files, nfiles,
1687 rdev->ddev->primary->debugfs_root,
1688 rdev->ddev->primary);
1693 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1695 #if defined(CONFIG_DEBUG_FS)
1698 for (i = 0; i < rdev->debugfs_count; i++) {
1699 drm_debugfs_remove_files(rdev->debugfs[i].files,
1700 rdev->debugfs[i].num_files,
1701 rdev->ddev->control);
1702 drm_debugfs_remove_files(rdev->debugfs[i].files,
1703 rdev->debugfs[i].num_files,
1704 rdev->ddev->primary);
1709 #if defined(CONFIG_DEBUG_FS)
1710 int radeon_debugfs_init(struct drm_minor *minor)
1715 void radeon_debugfs_cleanup(struct drm_minor *minor)