2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
105 bool radeon_is_px(struct drm_device *dev)
107 struct radeon_device *rdev = dev->dev_private;
109 if (rdev->flags & RADEON_IS_PX)
115 * radeon_program_register_sequence - program an array of registers.
117 * @rdev: radeon_device pointer
118 * @registers: pointer to the register array
119 * @array_size: size of the register array
121 * Programs an array or registers with and and or masks.
122 * This is a helper for setting golden registers.
124 void radeon_program_register_sequence(struct radeon_device *rdev,
125 const u32 *registers,
126 const u32 array_size)
128 u32 tmp, reg, and_mask, or_mask;
134 for (i = 0; i < array_size; i +=3) {
135 reg = registers[i + 0];
136 and_mask = registers[i + 1];
137 or_mask = registers[i + 2];
139 if (and_mask == 0xffffffff) {
150 void radeon_pci_config_reset(struct radeon_device *rdev)
152 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
156 * radeon_surface_init - Clear GPU surface registers.
158 * @rdev: radeon_device pointer
160 * Clear GPU surface registers (r1xx-r5xx).
162 void radeon_surface_init(struct radeon_device *rdev)
164 /* FIXME: check this out */
165 if (rdev->family < CHIP_R600) {
168 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
169 if (rdev->surface_regs[i].bo)
170 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
172 radeon_clear_surface_reg(rdev, i);
174 /* enable surfaces */
175 WREG32(RADEON_SURFACE_CNTL, 0);
180 * GPU scratch registers helpers function.
183 * radeon_scratch_init - Init scratch register driver information.
185 * @rdev: radeon_device pointer
187 * Init CP scratch register driver information (r1xx-r5xx)
189 void radeon_scratch_init(struct radeon_device *rdev)
193 /* FIXME: check this out */
194 if (rdev->family < CHIP_R300) {
195 rdev->scratch.num_reg = 5;
197 rdev->scratch.num_reg = 7;
199 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
200 for (i = 0; i < rdev->scratch.num_reg; i++) {
201 rdev->scratch.free[i] = true;
202 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
207 * radeon_scratch_get - Allocate a scratch register
209 * @rdev: radeon_device pointer
210 * @reg: scratch register mmio offset
212 * Allocate a CP scratch register for use by the driver (all asics).
213 * Returns 0 on success or -EINVAL on failure.
215 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
219 for (i = 0; i < rdev->scratch.num_reg; i++) {
220 if (rdev->scratch.free[i]) {
221 rdev->scratch.free[i] = false;
222 *reg = rdev->scratch.reg[i];
230 * radeon_scratch_free - Free a scratch register
232 * @rdev: radeon_device pointer
233 * @reg: scratch register mmio offset
235 * Free a CP scratch register allocated for use by the driver (all asics)
237 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
241 for (i = 0; i < rdev->scratch.num_reg; i++) {
242 if (rdev->scratch.reg[i] == reg) {
243 rdev->scratch.free[i] = true;
250 * GPU doorbell aperture helpers function.
253 * radeon_doorbell_init - Init doorbell driver information.
255 * @rdev: radeon_device pointer
257 * Init doorbell driver information (CIK)
258 * Returns 0 on success, error on failure.
260 static int radeon_doorbell_init(struct radeon_device *rdev)
262 /* doorbell bar mapping */
263 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
264 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
266 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
267 if (rdev->doorbell.num_doorbells == 0)
270 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
271 if (rdev->doorbell.ptr == NULL) {
274 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
275 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
277 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
283 * radeon_doorbell_fini - Tear down doorbell driver information.
285 * @rdev: radeon_device pointer
287 * Tear down doorbell driver information (CIK)
289 static void radeon_doorbell_fini(struct radeon_device *rdev)
291 iounmap(rdev->doorbell.ptr);
292 rdev->doorbell.ptr = NULL;
296 * radeon_doorbell_get - Allocate a doorbell entry
298 * @rdev: radeon_device pointer
299 * @doorbell: doorbell index
301 * Allocate a doorbell for use by the driver (all asics).
302 * Returns 0 on success or -EINVAL on failure.
304 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
306 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
307 if (offset < rdev->doorbell.num_doorbells) {
308 __set_bit(offset, rdev->doorbell.used);
317 * radeon_doorbell_free - Free a doorbell entry
319 * @rdev: radeon_device pointer
320 * @doorbell: doorbell index
322 * Free a doorbell allocated for use by the driver (all asics)
324 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
326 if (doorbell < rdev->doorbell.num_doorbells)
327 __clear_bit(doorbell, rdev->doorbell.used);
332 * Writeback is the the method by which the the GPU updates special pages
333 * in memory with the status of certain GPU events (fences, ring pointers,
338 * radeon_wb_disable - Disable Writeback
340 * @rdev: radeon_device pointer
342 * Disables Writeback (all asics). Used for suspend.
344 void radeon_wb_disable(struct radeon_device *rdev)
346 rdev->wb.enabled = false;
350 * radeon_wb_fini - Disable Writeback and free memory
352 * @rdev: radeon_device pointer
354 * Disables Writeback and frees the Writeback memory (all asics).
355 * Used at driver shutdown.
357 void radeon_wb_fini(struct radeon_device *rdev)
359 radeon_wb_disable(rdev);
360 if (rdev->wb.wb_obj) {
361 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
362 radeon_bo_kunmap(rdev->wb.wb_obj);
363 radeon_bo_unpin(rdev->wb.wb_obj);
364 radeon_bo_unreserve(rdev->wb.wb_obj);
366 radeon_bo_unref(&rdev->wb.wb_obj);
368 rdev->wb.wb_obj = NULL;
373 * radeon_wb_init- Init Writeback driver info and allocate memory
375 * @rdev: radeon_device pointer
377 * Disables Writeback and frees the Writeback memory (all asics).
378 * Used at driver startup.
379 * Returns 0 on success or an -error on failure.
381 int radeon_wb_init(struct radeon_device *rdev)
385 if (rdev->wb.wb_obj == NULL) {
386 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
387 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
389 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
392 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
393 if (unlikely(r != 0)) {
394 radeon_wb_fini(rdev);
397 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
400 radeon_bo_unreserve(rdev->wb.wb_obj);
401 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
402 radeon_wb_fini(rdev);
405 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
406 radeon_bo_unreserve(rdev->wb.wb_obj);
408 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
409 radeon_wb_fini(rdev);
414 /* clear wb memory */
415 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
416 /* disable event_write fences */
417 rdev->wb.use_event = false;
418 /* disabled via module param */
419 if (radeon_no_wb == 1) {
420 rdev->wb.enabled = false;
422 if (rdev->flags & RADEON_IS_AGP) {
423 /* often unreliable on AGP */
424 rdev->wb.enabled = false;
425 } else if (rdev->family < CHIP_R300) {
426 /* often unreliable on pre-r300 */
427 rdev->wb.enabled = false;
429 rdev->wb.enabled = true;
430 /* event_write fences are only available on r600+ */
431 if (rdev->family >= CHIP_R600) {
432 rdev->wb.use_event = true;
436 /* always use writeback/events on NI, APUs */
437 if (rdev->family >= CHIP_PALM) {
438 rdev->wb.enabled = true;
439 rdev->wb.use_event = true;
442 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
448 * radeon_vram_location - try to find VRAM location
449 * @rdev: radeon device structure holding all necessary informations
450 * @mc: memory controller structure holding memory informations
451 * @base: base address at which to put VRAM
453 * Function will place try to place VRAM at base address provided
454 * as parameter (which is so far either PCI aperture address or
455 * for IGP TOM base address).
457 * If there is not enough space to fit the unvisible VRAM in the 32bits
458 * address space then we limit the VRAM size to the aperture.
460 * If we are using AGP and if the AGP aperture doesn't allow us to have
461 * room for all the VRAM than we restrict the VRAM to the PCI aperture
462 * size and print a warning.
464 * This function will never fails, worst case are limiting VRAM.
466 * Note: GTT start, end, size should be initialized before calling this
467 * function on AGP platform.
469 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
470 * this shouldn't be a problem as we are using the PCI aperture as a reference.
471 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
474 * Note: we use mc_vram_size as on some board we need to program the mc to
475 * cover the whole aperture even if VRAM size is inferior to aperture size
476 * Novell bug 204882 + along with lots of ubuntu ones
478 * Note: when limiting vram it's safe to overwritte real_vram_size because
479 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
480 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
483 * Note: IGP TOM addr should be the same as the aperture addr, we don't
484 * explicitly check for that thought.
486 * FIXME: when reducing VRAM size align new size on power of 2.
488 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
490 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
492 mc->vram_start = base;
493 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
494 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
495 mc->real_vram_size = mc->aper_size;
496 mc->mc_vram_size = mc->aper_size;
498 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
499 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
500 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
501 mc->real_vram_size = mc->aper_size;
502 mc->mc_vram_size = mc->aper_size;
504 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
505 if (limit && limit < mc->real_vram_size)
506 mc->real_vram_size = limit;
507 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
508 mc->mc_vram_size >> 20, mc->vram_start,
509 mc->vram_end, mc->real_vram_size >> 20);
513 * radeon_gtt_location - try to find GTT location
514 * @rdev: radeon device structure holding all necessary informations
515 * @mc: memory controller structure holding memory informations
517 * Function will place try to place GTT before or after VRAM.
519 * If GTT size is bigger than space left then we ajust GTT size.
520 * Thus function will never fails.
522 * FIXME: when reducing GTT size align new size on power of 2.
524 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
526 u64 size_af, size_bf;
528 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
529 size_bf = mc->vram_start & ~mc->gtt_base_align;
530 if (size_bf > size_af) {
531 if (mc->gtt_size > size_bf) {
532 dev_warn(rdev->dev, "limiting GTT\n");
533 mc->gtt_size = size_bf;
535 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
537 if (mc->gtt_size > size_af) {
538 dev_warn(rdev->dev, "limiting GTT\n");
539 mc->gtt_size = size_af;
541 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
543 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
544 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
545 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
549 * GPU helpers function.
552 * radeon_card_posted - check if the hw has already been initialized
554 * @rdev: radeon_device pointer
556 * Check if the asic has been initialized (all asics).
557 * Used at driver startup.
558 * Returns true if initialized or false if not.
560 bool radeon_card_posted(struct radeon_device *rdev)
564 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
565 if (efi_enabled(EFI_BOOT) &&
566 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
567 (rdev->family < CHIP_R600))
570 if (ASIC_IS_NODCE(rdev))
573 /* first check CRTCs */
574 if (ASIC_IS_DCE4(rdev)) {
575 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
576 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
577 if (rdev->num_crtc >= 4) {
578 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
579 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
581 if (rdev->num_crtc >= 6) {
582 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
583 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
585 if (reg & EVERGREEN_CRTC_MASTER_EN)
587 } else if (ASIC_IS_AVIVO(rdev)) {
588 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
589 RREG32(AVIVO_D2CRTC_CONTROL);
590 if (reg & AVIVO_CRTC_EN) {
594 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
595 RREG32(RADEON_CRTC2_GEN_CNTL);
596 if (reg & RADEON_CRTC_EN) {
602 /* then check MEM_SIZE, in case the crtcs are off */
603 if (rdev->family >= CHIP_R600)
604 reg = RREG32(R600_CONFIG_MEMSIZE);
606 reg = RREG32(RADEON_CONFIG_MEMSIZE);
616 * radeon_update_bandwidth_info - update display bandwidth params
618 * @rdev: radeon_device pointer
620 * Used when sclk/mclk are switched or display modes are set.
621 * params are used to calculate display watermarks (all asics)
623 void radeon_update_bandwidth_info(struct radeon_device *rdev)
626 u32 sclk = rdev->pm.current_sclk;
627 u32 mclk = rdev->pm.current_mclk;
629 /* sclk/mclk in Mhz */
630 a.full = dfixed_const(100);
631 rdev->pm.sclk.full = dfixed_const(sclk);
632 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
633 rdev->pm.mclk.full = dfixed_const(mclk);
634 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
636 if (rdev->flags & RADEON_IS_IGP) {
637 a.full = dfixed_const(16);
638 /* core_bandwidth = sclk(Mhz) * 16 */
639 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
644 * radeon_boot_test_post_card - check and possibly initialize the hw
646 * @rdev: radeon_device pointer
648 * Check if the asic is initialized and if not, attempt to initialize
650 * Returns true if initialized or false if not.
652 bool radeon_boot_test_post_card(struct radeon_device *rdev)
654 if (radeon_card_posted(rdev))
658 DRM_INFO("GPU not posted. posting now...\n");
659 if (rdev->is_atom_bios)
660 atom_asic_init(rdev->mode_info.atom_context);
662 radeon_combios_asic_init(rdev->ddev);
665 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
671 * radeon_dummy_page_init - init dummy page used by the driver
673 * @rdev: radeon_device pointer
675 * Allocate the dummy page used by the driver (all asics).
676 * This dummy page is used by the driver as a filler for gart entries
677 * when pages are taken out of the GART
678 * Returns 0 on sucess, -ENOMEM on failure.
680 int radeon_dummy_page_init(struct radeon_device *rdev)
682 if (rdev->dummy_page.page)
684 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
685 if (rdev->dummy_page.page == NULL)
687 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
688 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
689 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
690 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
691 __free_page(rdev->dummy_page.page);
692 rdev->dummy_page.page = NULL;
699 * radeon_dummy_page_fini - free dummy page used by the driver
701 * @rdev: radeon_device pointer
703 * Frees the dummy page used by the driver (all asics).
705 void radeon_dummy_page_fini(struct radeon_device *rdev)
707 if (rdev->dummy_page.page == NULL)
709 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
710 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
711 __free_page(rdev->dummy_page.page);
712 rdev->dummy_page.page = NULL;
716 /* ATOM accessor methods */
718 * ATOM is an interpreted byte code stored in tables in the vbios. The
719 * driver registers callbacks to access registers and the interpreter
720 * in the driver parses the tables and executes then to program specific
721 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
722 * atombios.h, and atom.c
726 * cail_pll_read - read PLL register
728 * @info: atom card_info pointer
729 * @reg: PLL register offset
731 * Provides a PLL register accessor for the atom interpreter (r4xx+).
732 * Returns the value of the PLL register.
734 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
736 struct radeon_device *rdev = info->dev->dev_private;
739 r = rdev->pll_rreg(rdev, reg);
744 * cail_pll_write - write PLL register
746 * @info: atom card_info pointer
747 * @reg: PLL register offset
748 * @val: value to write to the pll register
750 * Provides a PLL register accessor for the atom interpreter (r4xx+).
752 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
754 struct radeon_device *rdev = info->dev->dev_private;
756 rdev->pll_wreg(rdev, reg, val);
760 * cail_mc_read - read MC (Memory Controller) register
762 * @info: atom card_info pointer
763 * @reg: MC register offset
765 * Provides an MC register accessor for the atom interpreter (r4xx+).
766 * Returns the value of the MC register.
768 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
770 struct radeon_device *rdev = info->dev->dev_private;
773 r = rdev->mc_rreg(rdev, reg);
778 * cail_mc_write - write MC (Memory Controller) register
780 * @info: atom card_info pointer
781 * @reg: MC register offset
782 * @val: value to write to the pll register
784 * Provides a MC register accessor for the atom interpreter (r4xx+).
786 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
788 struct radeon_device *rdev = info->dev->dev_private;
790 rdev->mc_wreg(rdev, reg, val);
794 * cail_reg_write - write MMIO register
796 * @info: atom card_info pointer
797 * @reg: MMIO register offset
798 * @val: value to write to the pll register
800 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
802 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
804 struct radeon_device *rdev = info->dev->dev_private;
810 * cail_reg_read - read MMIO register
812 * @info: atom card_info pointer
813 * @reg: MMIO register offset
815 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
816 * Returns the value of the MMIO register.
818 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
820 struct radeon_device *rdev = info->dev->dev_private;
828 * cail_ioreg_write - write IO register
830 * @info: atom card_info pointer
831 * @reg: IO register offset
832 * @val: value to write to the pll register
834 * Provides a IO register accessor for the atom interpreter (r4xx+).
836 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
838 struct radeon_device *rdev = info->dev->dev_private;
840 WREG32_IO(reg*4, val);
844 * cail_ioreg_read - read IO register
846 * @info: atom card_info pointer
847 * @reg: IO register offset
849 * Provides an IO register accessor for the atom interpreter (r4xx+).
850 * Returns the value of the IO register.
852 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
854 struct radeon_device *rdev = info->dev->dev_private;
857 r = RREG32_IO(reg*4);
862 * radeon_atombios_init - init the driver info and callbacks for atombios
864 * @rdev: radeon_device pointer
866 * Initializes the driver info and register access callbacks for the
867 * ATOM interpreter (r4xx+).
868 * Returns 0 on sucess, -ENOMEM on failure.
869 * Called at driver startup.
871 int radeon_atombios_init(struct radeon_device *rdev)
873 struct card_info *atom_card_info =
874 kzalloc(sizeof(struct card_info), GFP_KERNEL);
879 rdev->mode_info.atom_card_info = atom_card_info;
880 atom_card_info->dev = rdev->ddev;
881 atom_card_info->reg_read = cail_reg_read;
882 atom_card_info->reg_write = cail_reg_write;
883 /* needed for iio ops */
885 atom_card_info->ioreg_read = cail_ioreg_read;
886 atom_card_info->ioreg_write = cail_ioreg_write;
888 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
889 atom_card_info->ioreg_read = cail_reg_read;
890 atom_card_info->ioreg_write = cail_reg_write;
892 atom_card_info->mc_read = cail_mc_read;
893 atom_card_info->mc_write = cail_mc_write;
894 atom_card_info->pll_read = cail_pll_read;
895 atom_card_info->pll_write = cail_pll_write;
897 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
898 if (!rdev->mode_info.atom_context) {
899 radeon_atombios_fini(rdev);
903 mutex_init(&rdev->mode_info.atom_context->mutex);
904 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
905 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
910 * radeon_atombios_fini - free the driver info and callbacks for atombios
912 * @rdev: radeon_device pointer
914 * Frees the driver info and register access callbacks for the ATOM
915 * interpreter (r4xx+).
916 * Called at driver shutdown.
918 void radeon_atombios_fini(struct radeon_device *rdev)
920 if (rdev->mode_info.atom_context) {
921 kfree(rdev->mode_info.atom_context->scratch);
923 kfree(rdev->mode_info.atom_context);
924 rdev->mode_info.atom_context = NULL;
925 kfree(rdev->mode_info.atom_card_info);
926 rdev->mode_info.atom_card_info = NULL;
931 * COMBIOS is the bios format prior to ATOM. It provides
932 * command tables similar to ATOM, but doesn't have a unified
933 * parser. See radeon_combios.c
937 * radeon_combios_init - init the driver info for combios
939 * @rdev: radeon_device pointer
941 * Initializes the driver info for combios (r1xx-r3xx).
942 * Returns 0 on sucess.
943 * Called at driver startup.
945 int radeon_combios_init(struct radeon_device *rdev)
947 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
952 * radeon_combios_fini - free the driver info for combios
954 * @rdev: radeon_device pointer
956 * Frees the driver info for combios (r1xx-r3xx).
957 * Called at driver shutdown.
959 void radeon_combios_fini(struct radeon_device *rdev)
963 /* if we get transitioned to only one device, take VGA back */
965 * radeon_vga_set_decode - enable/disable vga decode
967 * @cookie: radeon_device pointer
968 * @state: enable/disable vga decode
970 * Enable/disable vga decode (all asics).
971 * Returns VGA resource flags.
973 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
975 struct radeon_device *rdev = cookie;
976 radeon_vga_set_state(rdev, state);
978 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
979 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
981 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
985 * radeon_check_pot_argument - check that argument is a power of two
987 * @arg: value to check
989 * Validates that a certain argument is a power of two (all asics).
990 * Returns true if argument is valid.
992 static bool radeon_check_pot_argument(int arg)
994 return (arg & (arg - 1)) == 0;
998 * radeon_check_arguments - validate module params
1000 * @rdev: radeon_device pointer
1002 * Validates certain module parameters and updates
1003 * the associated values used by the driver (all asics).
1005 static void radeon_check_arguments(struct radeon_device *rdev)
1007 /* vramlimit must be a power of two */
1008 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1009 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1011 radeon_vram_limit = 0;
1014 if (radeon_gart_size == -1) {
1015 /* default to a larger gart size on newer asics */
1016 if (rdev->family >= CHIP_RV770)
1017 radeon_gart_size = 1024;
1019 radeon_gart_size = 512;
1021 /* gtt size must be power of two and greater or equal to 32M */
1022 if (radeon_gart_size < 32) {
1023 dev_warn(rdev->dev, "gart size (%d) too small\n",
1025 if (rdev->family >= CHIP_RV770)
1026 radeon_gart_size = 1024;
1028 radeon_gart_size = 512;
1029 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1030 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1032 if (rdev->family >= CHIP_RV770)
1033 radeon_gart_size = 1024;
1035 radeon_gart_size = 512;
1037 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1039 /* AGP mode can only be -1, 1, 2, 4, 8 */
1040 switch (radeon_agpmode) {
1049 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1050 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1057 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1058 * needed for waking up.
1060 * @pdev: pci dev pointer
1062 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1065 /* 6600m in a macbook pro */
1066 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1067 pdev->subsystem_device == 0x00e2) {
1068 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1076 * radeon_switcheroo_set_state - set switcheroo state
1078 * @pdev: pci dev pointer
1079 * @state: vga switcheroo state
1081 * Callback for the switcheroo driver. Suspends or resumes the
1082 * the asics before or after it is powered up using ACPI methods.
1084 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1086 struct drm_device *dev = pci_get_drvdata(pdev);
1088 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1091 if (state == VGA_SWITCHEROO_ON) {
1092 unsigned d3_delay = dev->pdev->d3_delay;
1094 printk(KERN_INFO "radeon: switched on\n");
1095 /* don't suspend or resume card normally */
1096 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1098 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1099 dev->pdev->d3_delay = 20;
1101 radeon_resume_kms(dev, true, true);
1103 dev->pdev->d3_delay = d3_delay;
1105 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1106 drm_kms_helper_poll_enable(dev);
1108 printk(KERN_INFO "radeon: switched off\n");
1109 drm_kms_helper_poll_disable(dev);
1110 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1111 radeon_suspend_kms(dev, true, true);
1112 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1117 * radeon_switcheroo_can_switch - see if switcheroo state can change
1119 * @pdev: pci dev pointer
1121 * Callback for the switcheroo driver. Check of the switcheroo
1122 * state can be changed.
1123 * Returns true if the state can be changed, false if not.
1125 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1127 struct drm_device *dev = pci_get_drvdata(pdev);
1130 spin_lock(&dev->count_lock);
1131 can_switch = (dev->open_count == 0);
1132 spin_unlock(&dev->count_lock);
1136 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1137 .set_gpu_state = radeon_switcheroo_set_state,
1139 .can_switch = radeon_switcheroo_can_switch,
1143 * radeon_device_init - initialize the driver
1145 * @rdev: radeon_device pointer
1146 * @pdev: drm dev pointer
1147 * @pdev: pci dev pointer
1148 * @flags: driver flags
1150 * Initializes the driver info and hw (all asics).
1151 * Returns 0 for success or an error on failure.
1152 * Called at driver startup.
1154 int radeon_device_init(struct radeon_device *rdev,
1155 struct drm_device *ddev,
1156 struct pci_dev *pdev,
1161 bool runtime = false;
1163 rdev->shutdown = false;
1164 rdev->dev = &pdev->dev;
1167 rdev->flags = flags;
1168 rdev->family = flags & RADEON_FAMILY_MASK;
1169 rdev->is_atom_bios = false;
1170 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1171 rdev->mc.gtt_size = 512 * 1024 * 1024;
1172 rdev->accel_working = false;
1173 /* set up ring ids */
1174 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1175 rdev->ring[i].idx = i;
1178 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1179 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1180 pdev->subsystem_vendor, pdev->subsystem_device);
1182 /* mutex initialization are all done here so we
1183 * can recall function without having locking issues */
1184 mutex_init(&rdev->ring_lock);
1185 mutex_init(&rdev->dc_hw_i2c_mutex);
1186 atomic_set(&rdev->ih.lock, 0);
1187 mutex_init(&rdev->gem.mutex);
1188 mutex_init(&rdev->pm.mutex);
1189 mutex_init(&rdev->gpu_clock_mutex);
1190 mutex_init(&rdev->srbm_mutex);
1191 init_rwsem(&rdev->pm.mclk_lock);
1192 init_rwsem(&rdev->exclusive_lock);
1193 init_waitqueue_head(&rdev->irq.vblank_queue);
1194 r = radeon_gem_init(rdev);
1198 /* Adjust VM size here.
1199 * Currently set to 4GB ((1 << 20) 4k pages).
1200 * Max GPUVM size for cayman and SI is 40 bits.
1202 rdev->vm_manager.max_pfn = 1 << 20;
1204 /* Set asic functions */
1205 r = radeon_asic_init(rdev);
1208 radeon_check_arguments(rdev);
1210 /* all of the newer IGP chips have an internal gart
1211 * However some rs4xx report as AGP, so remove that here.
1213 if ((rdev->family >= CHIP_RS400) &&
1214 (rdev->flags & RADEON_IS_IGP)) {
1215 rdev->flags &= ~RADEON_IS_AGP;
1218 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1219 radeon_agp_disable(rdev);
1222 /* Set the internal MC address mask
1223 * This is the max address of the GPU's
1224 * internal address space.
1226 if (rdev->family >= CHIP_CAYMAN)
1227 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1228 else if (rdev->family >= CHIP_CEDAR)
1229 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1231 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1233 /* set DMA mask + need_dma32 flags.
1234 * PCIE - can handle 40-bits.
1235 * IGP - can handle 40-bits
1236 * AGP - generally dma32 is safest
1237 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1239 rdev->need_dma32 = false;
1240 if (rdev->flags & RADEON_IS_AGP)
1241 rdev->need_dma32 = true;
1242 if ((rdev->flags & RADEON_IS_PCI) &&
1243 (rdev->family <= CHIP_RS740))
1244 rdev->need_dma32 = true;
1246 dma_bits = rdev->need_dma32 ? 32 : 40;
1247 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1249 rdev->need_dma32 = true;
1251 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1253 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1255 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1256 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1259 /* Registers mapping */
1260 /* TODO: block userspace mapping of io register */
1261 spin_lock_init(&rdev->mmio_idx_lock);
1262 spin_lock_init(&rdev->smc_idx_lock);
1263 spin_lock_init(&rdev->pll_idx_lock);
1264 spin_lock_init(&rdev->mc_idx_lock);
1265 spin_lock_init(&rdev->pcie_idx_lock);
1266 spin_lock_init(&rdev->pciep_idx_lock);
1267 spin_lock_init(&rdev->pif_idx_lock);
1268 spin_lock_init(&rdev->cg_idx_lock);
1269 spin_lock_init(&rdev->uvd_idx_lock);
1270 spin_lock_init(&rdev->rcu_idx_lock);
1271 spin_lock_init(&rdev->didt_idx_lock);
1272 spin_lock_init(&rdev->end_idx_lock);
1273 if (rdev->family >= CHIP_BONAIRE) {
1274 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1275 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1277 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1278 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1280 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1281 if (rdev->rmmio == NULL) {
1284 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1285 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1287 /* doorbell bar mapping */
1288 if (rdev->family >= CHIP_BONAIRE)
1289 radeon_doorbell_init(rdev);
1291 /* io port mapping */
1292 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1293 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1294 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1295 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1299 if (rdev->rio_mem == NULL)
1300 DRM_ERROR("Unable to find PCI I/O BAR\n");
1302 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1303 /* this will fail for cards that aren't VGA class devices, just
1305 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1307 if (rdev->flags & RADEON_IS_PX)
1309 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1311 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1313 r = radeon_init(rdev);
1317 r = radeon_ib_ring_tests(rdev);
1319 DRM_ERROR("ib ring test failed (%d).\n", r);
1321 r = radeon_gem_debugfs_init(rdev);
1323 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1326 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1327 /* Acceleration not working on AGP card try again
1328 * with fallback to PCI or PCIE GART
1330 radeon_asic_reset(rdev);
1332 radeon_agp_disable(rdev);
1333 r = radeon_init(rdev);
1338 if ((radeon_testing & 1)) {
1339 if (rdev->accel_working)
1340 radeon_test_moves(rdev);
1342 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1344 if ((radeon_testing & 2)) {
1345 if (rdev->accel_working)
1346 radeon_test_syncing(rdev);
1348 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1350 if (radeon_benchmarking) {
1351 if (rdev->accel_working)
1352 radeon_benchmark(rdev, radeon_benchmarking);
1354 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1359 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1362 * radeon_device_fini - tear down the driver
1364 * @rdev: radeon_device pointer
1366 * Tear down the driver info (all asics).
1367 * Called at driver shutdown.
1369 void radeon_device_fini(struct radeon_device *rdev)
1371 DRM_INFO("radeon: finishing device.\n");
1372 rdev->shutdown = true;
1373 /* evict vram memory */
1374 radeon_bo_evict_vram(rdev);
1376 vga_switcheroo_unregister_client(rdev->pdev);
1377 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1379 pci_iounmap(rdev->pdev, rdev->rio_mem);
1380 rdev->rio_mem = NULL;
1381 iounmap(rdev->rmmio);
1383 if (rdev->family >= CHIP_BONAIRE)
1384 radeon_doorbell_fini(rdev);
1385 radeon_debugfs_remove_files(rdev);
1393 * radeon_suspend_kms - initiate device suspend
1395 * @pdev: drm dev pointer
1396 * @state: suspend state
1398 * Puts the hw in the suspend state (all asics).
1399 * Returns 0 for success or an error on failure.
1400 * Called at driver suspend.
1402 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1404 struct radeon_device *rdev;
1405 struct drm_crtc *crtc;
1406 struct drm_connector *connector;
1408 bool force_completion = false;
1410 if (dev == NULL || dev->dev_private == NULL) {
1414 rdev = dev->dev_private;
1416 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1419 drm_kms_helper_poll_disable(dev);
1421 /* turn off display hw */
1422 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1423 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1426 /* unpin the front buffers */
1427 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1428 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1429 struct radeon_bo *robj;
1431 if (rfb == NULL || rfb->obj == NULL) {
1434 robj = gem_to_radeon_bo(rfb->obj);
1435 /* don't unpin kernel fb objects */
1436 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1437 r = radeon_bo_reserve(robj, false);
1439 radeon_bo_unpin(robj);
1440 radeon_bo_unreserve(robj);
1444 /* evict vram memory */
1445 radeon_bo_evict_vram(rdev);
1447 /* wait for gpu to finish processing current batch */
1448 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1449 r = radeon_fence_wait_empty(rdev, i);
1451 /* delay GPU reset to resume */
1452 force_completion = true;
1455 if (force_completion) {
1456 radeon_fence_driver_force_completion(rdev);
1459 radeon_save_bios_scratch_regs(rdev);
1461 radeon_suspend(rdev);
1462 radeon_hpd_fini(rdev);
1463 /* evict remaining vram memory */
1464 radeon_bo_evict_vram(rdev);
1466 radeon_agp_suspend(rdev);
1468 pci_save_state(dev->pdev);
1470 /* Shut down the device */
1471 pci_disable_device(dev->pdev);
1472 pci_set_power_state(dev->pdev, PCI_D3hot);
1477 radeon_fbdev_set_suspend(rdev, 1);
1484 * radeon_resume_kms - initiate device resume
1486 * @pdev: drm dev pointer
1488 * Bring the hw back to operating state (all asics).
1489 * Returns 0 for success or an error on failure.
1490 * Called at driver resume.
1492 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1494 struct drm_connector *connector;
1495 struct radeon_device *rdev = dev->dev_private;
1498 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1505 pci_set_power_state(dev->pdev, PCI_D0);
1506 pci_restore_state(dev->pdev);
1507 if (pci_enable_device(dev->pdev)) {
1513 /* resume AGP if in use */
1514 radeon_agp_resume(rdev);
1515 radeon_resume(rdev);
1517 r = radeon_ib_ring_tests(rdev);
1519 DRM_ERROR("ib ring test failed (%d).\n", r);
1521 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1522 /* do dpm late init */
1523 r = radeon_pm_late_init(rdev);
1525 rdev->pm.dpm_enabled = false;
1526 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1529 /* resume old pm late */
1530 radeon_pm_resume(rdev);
1533 radeon_restore_bios_scratch_regs(rdev);
1536 radeon_fbdev_set_suspend(rdev, 0);
1540 /* init dig PHYs, disp eng pll */
1541 if (rdev->is_atom_bios) {
1542 radeon_atom_encoder_init(rdev);
1543 radeon_atom_disp_eng_pll_init(rdev);
1544 /* turn on the BL */
1545 if (rdev->mode_info.bl_encoder) {
1546 u8 bl_level = radeon_get_backlight_level(rdev,
1547 rdev->mode_info.bl_encoder);
1548 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1552 /* reset hpd state */
1553 radeon_hpd_init(rdev);
1554 /* blat the mode back in */
1556 drm_helper_resume_force_mode(dev);
1557 /* turn on display hw */
1558 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1559 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1563 drm_kms_helper_poll_enable(dev);
1568 * radeon_gpu_reset - reset the asic
1570 * @rdev: radeon device pointer
1572 * Attempt the reset the GPU if it has hung (all asics).
1573 * Returns 0 for success or an error on failure.
1575 int radeon_gpu_reset(struct radeon_device *rdev)
1577 unsigned ring_sizes[RADEON_NUM_RINGS];
1578 uint32_t *ring_data[RADEON_NUM_RINGS];
1585 down_write(&rdev->exclusive_lock);
1587 if (!rdev->needs_reset) {
1588 up_write(&rdev->exclusive_lock);
1592 rdev->needs_reset = false;
1594 radeon_save_bios_scratch_regs(rdev);
1596 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1597 radeon_pm_suspend(rdev);
1598 radeon_suspend(rdev);
1600 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1601 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1603 if (ring_sizes[i]) {
1605 dev_info(rdev->dev, "Saved %d dwords of commands "
1606 "on ring %d.\n", ring_sizes[i], i);
1611 r = radeon_asic_reset(rdev);
1613 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1614 radeon_resume(rdev);
1617 radeon_restore_bios_scratch_regs(rdev);
1620 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1621 radeon_ring_restore(rdev, &rdev->ring[i],
1622 ring_sizes[i], ring_data[i]);
1624 ring_data[i] = NULL;
1627 r = radeon_ib_ring_tests(rdev);
1629 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1632 radeon_suspend(rdev);
1637 radeon_fence_driver_force_completion(rdev);
1638 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1639 kfree(ring_data[i]);
1643 radeon_pm_resume(rdev);
1644 drm_helper_resume_force_mode(rdev->ddev);
1646 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1648 /* bad news, how to tell it to userspace ? */
1649 dev_info(rdev->dev, "GPU reset failed\n");
1652 up_write(&rdev->exclusive_lock);
1660 int radeon_debugfs_add_files(struct radeon_device *rdev,
1661 struct drm_info_list *files,
1666 for (i = 0; i < rdev->debugfs_count; i++) {
1667 if (rdev->debugfs[i].files == files) {
1668 /* Already registered */
1673 i = rdev->debugfs_count + 1;
1674 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1675 DRM_ERROR("Reached maximum number of debugfs components.\n");
1676 DRM_ERROR("Report so we increase "
1677 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1680 rdev->debugfs[rdev->debugfs_count].files = files;
1681 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1682 rdev->debugfs_count = i;
1683 #if defined(CONFIG_DEBUG_FS)
1684 drm_debugfs_create_files(files, nfiles,
1685 rdev->ddev->control->debugfs_root,
1686 rdev->ddev->control);
1687 drm_debugfs_create_files(files, nfiles,
1688 rdev->ddev->primary->debugfs_root,
1689 rdev->ddev->primary);
1694 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1696 #if defined(CONFIG_DEBUG_FS)
1699 for (i = 0; i < rdev->debugfs_count; i++) {
1700 drm_debugfs_remove_files(rdev->debugfs[i].files,
1701 rdev->debugfs[i].num_files,
1702 rdev->ddev->control);
1703 drm_debugfs_remove_files(rdev->debugfs[i].files,
1704 rdev->debugfs[i].num_files,
1705 rdev->ddev->primary);
1710 #if defined(CONFIG_DEBUG_FS)
1711 int radeon_debugfs_init(struct drm_minor *minor)
1716 void radeon_debugfs_cleanup(struct drm_minor *minor)