drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  37 {
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39         struct drm_device *dev = crtc->dev;
  40         struct radeon_device *rdev = dev->dev_private;
  41         int i;
  42
  43         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  44         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  45
  46         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  47         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  51         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  53
  54         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  55         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  56         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  57
  58         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  59         for (i = 0; i < 256; i++) {
  60                 WREG32(AVIVO_DC_LUT_30_COLOR,
  61                              (radeon_crtc->lut_r[i] << 20) |
  62                              (radeon_crtc->lut_g[i] << 10) |
  63                              (radeon_crtc->lut_b[i] << 0));
  64         }
  65
  66         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  67 }
  68
  69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  70 {
  71         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  72         struct drm_device *dev = crtc->dev;
  73         struct radeon_device *rdev = dev->dev_private;
  74         int i;
  75
  76         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  77         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  78
  79         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  80         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  82
  83         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  84         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  86
  87         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  88         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  91         for (i = 0; i < 256; i++) {
  92                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  93                        (radeon_crtc->lut_r[i] << 20) |
  94                        (radeon_crtc->lut_g[i] << 10) |
  95                        (radeon_crtc->lut_b[i] << 0));
  96         }
  97 }
  98
  99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 100 {
 101         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 102         struct drm_device *dev = crtc->dev;
 103         struct radeon_device *rdev = dev->dev_private;
 104         int i;
 105
 106         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 107
 108         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 109                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 110                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 111         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 112                NI_GRPH_PRESCALE_BYPASS);
 113         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 114                NI_OVL_PRESCALE_BYPASS);
 115         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 116                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 117                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 118
 119         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 120
 121         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 122         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 124
 125         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 126         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 128
 129         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 130         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 133         for (i = 0; i < 256; i++) {
 134                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 135                        (radeon_crtc->lut_r[i] << 20) |
 136                        (radeon_crtc->lut_g[i] << 10) |
 137                        (radeon_crtc->lut_b[i] << 0));
 138         }
 139
 140         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 142                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 143                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 144                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 145         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 147                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 148         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 150                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 151         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 153                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 154         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 155         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 156
 157 }
 158
 159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 160 {
 161         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 162         struct drm_device *dev = crtc->dev;
 163         struct radeon_device *rdev = dev->dev_private;
 164         int i;
 165         uint32_t dac2_cntl;
 166
 167         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 168         if (radeon_crtc->crtc_id == 0)
 169                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 170         else
 171                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 172         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 173
 174         WREG8(RADEON_PALETTE_INDEX, 0);
 175         for (i = 0; i < 256; i++) {
 176                 WREG32(RADEON_PALETTE_30_DATA,
 177                              (radeon_crtc->lut_r[i] << 20) |
 178                              (radeon_crtc->lut_g[i] << 10) |
 179                              (radeon_crtc->lut_b[i] << 0));
 180         }
 181 }
 182
 183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 184 {
 185         struct drm_device *dev = crtc->dev;
 186         struct radeon_device *rdev = dev->dev_private;
 187
 188         if (!crtc->enabled)
 189                 return;
 190
 191         if (ASIC_IS_DCE5(rdev))
 192                 dce5_crtc_load_lut(crtc);
 193         else if (ASIC_IS_DCE4(rdev))
 194                 dce4_crtc_load_lut(crtc);
 195         else if (ASIC_IS_AVIVO(rdev))
 196                 avivo_crtc_load_lut(crtc);
 197         else
 198                 legacy_crtc_load_lut(crtc);
 199 }
 200
 201 /** Sets the color ramps on behalf of fbcon */
 202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 203                               u16 blue, int regno)
 204 {
 205         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 206
 207         radeon_crtc->lut_r[regno] = red >> 6;
 208         radeon_crtc->lut_g[regno] = green >> 6;
 209         radeon_crtc->lut_b[regno] = blue >> 6;
 210 }
 211
 212 /** Gets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 214                               u16 *blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         *red = radeon_crtc->lut_r[regno] << 6;
 219         *green = radeon_crtc->lut_g[regno] << 6;
 220         *blue = radeon_crtc->lut_b[regno] << 6;
 221 }
 222
 223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 224                                   u16 *blue, uint32_t start, uint32_t size)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         int end = (start + size > 256) ? 256 : start + size, i;
 228
 229         /* userspace palettes are always correct as is */
 230         for (i = start; i < end; i++) {
 231                 radeon_crtc->lut_r[i] = red[i] >> 6;
 232                 radeon_crtc->lut_g[i] = green[i] >> 6;
 233                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 234         }
 235         radeon_crtc_load_lut(crtc);
 236 }
 237
 238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 239 {
 240         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 241
 242         drm_crtc_cleanup(crtc);
 243         kfree(radeon_crtc);
 244 }
 245
 246 /*
 247  * Handle unpin events outside the interrupt handler proper.
 248  */
 249 static void radeon_unpin_work_func(struct work_struct *__work)
 250 {
 251         struct radeon_unpin_work *work =
 252                 container_of(__work, struct radeon_unpin_work, work);
 253         int r;
 254
 255         /* unpin of the old buffer */
 256         r = radeon_bo_reserve(work->old_rbo, false);
 257         if (likely(r == 0)) {
 258                 r = radeon_bo_unpin(work->old_rbo);
 259                 if (unlikely(r != 0)) {
 260                         DRM_ERROR("failed to unpin buffer after flip\n");
 261                 }
 262                 radeon_bo_unreserve(work->old_rbo);
 263         } else
 264                 DRM_ERROR("failed to reserve buffer after flip\n");
 265
 266         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 267         kfree(work);
 268 }
 269
 270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 271 {
 272         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 273         struct radeon_unpin_work *work;
 274         struct drm_pending_vblank_event *e;
 275         struct timeval now;
 276         unsigned long flags;
 277         u32 update_pending;
 278         int vpos, hpos;
 279
 280         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 281         work = radeon_crtc->unpin_work;
 282         if (work == NULL ||
 283             (work->fence && !radeon_fence_signaled(work->fence))) {
 284                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 285                 return;
 286         }
 287         /* New pageflip, or just completion of a previous one? */
 288         if (!radeon_crtc->deferred_flip_completion) {
 289                 /* do the flip (mmio) */
 290                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 291         } else {
 292                 /* This is just a completion of a flip queued in crtc
 293                  * at last invocation. Make sure we go directly to
 294                  * completion routine.
 295                  */
 296                 update_pending = 0;
 297                 radeon_crtc->deferred_flip_completion = 0;
 298         }
 299
 300         /* Has the pageflip already completed in crtc, or is it certain
 301          * to complete in this vblank?
 302          */
 303         if (update_pending &&
 304             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 305                                                                &vpos, &hpos)) &&
 306             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 307              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 308                 /* crtc didn't flip in this target vblank interval,
 309                  * but flip is pending in crtc. Based on the current
 310                  * scanout position we know that the current frame is
 311                  * (nearly) complete and the flip will (likely)
 312                  * complete before the start of the next frame.
 313                  */
 314                 update_pending = 0;
 315         }
 316         if (update_pending) {
 317                 /* crtc didn't flip in this target vblank interval,
 318                  * but flip is pending in crtc. It will complete it
 319                  * in next vblank interval, so complete the flip at
 320                  * next vblank irq.
 321                  */
 322                 radeon_crtc->deferred_flip_completion = 1;
 323                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 324                 return;
 325         }
 326
 327         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 328         radeon_crtc->unpin_work = NULL;
 329
 330         /* wakeup userspace */
 331         if (work->event) {
 332                 e = work->event;
 333                 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
 334                 e->event.tv_sec = now.tv_sec;
 335                 e->event.tv_usec = now.tv_usec;
 336                 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 337                 wake_up_interruptible(&e->base.file_priv->event_wait);
 338         }
 339         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 340
 341         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 342         radeon_fence_unref(&work->fence);
 343         radeon_post_page_flip(work->rdev, work->crtc_id);
 344         schedule_work(&work->work);
 345 }
 346
 347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 348                                  struct drm_framebuffer *fb,
 349                                  struct drm_pending_vblank_event *event)
 350 {
 351         struct drm_device *dev = crtc->dev;
 352         struct radeon_device *rdev = dev->dev_private;
 353         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 354         struct radeon_framebuffer *old_radeon_fb;
 355         struct radeon_framebuffer *new_radeon_fb;
 356         struct drm_gem_object *obj;
 357         struct radeon_bo *rbo;
 358         struct radeon_unpin_work *work;
 359         unsigned long flags;
 360         u32 tiling_flags, pitch_pixels;
 361         u64 base;
 362         int r;
 363
 364         work = kzalloc(sizeof *work, GFP_KERNEL);
 365         if (work == NULL)
 366                 return -ENOMEM;
 367
 368         work->event = event;
 369         work->rdev = rdev;
 370         work->crtc_id = radeon_crtc->crtc_id;
 371         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 372         new_radeon_fb = to_radeon_framebuffer(fb);
 373         /* schedule unpin of the old buffer */
 374         obj = old_radeon_fb->obj;
 375         /* take a reference to the old object */
 376         drm_gem_object_reference(obj);
 377         rbo = gem_to_radeon_bo(obj);
 378         work->old_rbo = rbo;
 379         obj = new_radeon_fb->obj;
 380         rbo = gem_to_radeon_bo(obj);
 381         if (rbo->tbo.sync_obj)
 382                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 383         INIT_WORK(&work->work, radeon_unpin_work_func);
 384
 385         /* We borrow the event spin lock for protecting unpin_work */
 386         spin_lock_irqsave(&dev->event_lock, flags);
 387         if (radeon_crtc->unpin_work) {
 388                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 389                 r = -EBUSY;
 390                 goto unlock_free;
 391         }
 392         radeon_crtc->unpin_work = work;
 393         radeon_crtc->deferred_flip_completion = 0;
 394         spin_unlock_irqrestore(&dev->event_lock, flags);
 395
 396         /* pin the new buffer */
 397         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 398                          work->old_rbo, rbo);
 399
 400         r = radeon_bo_reserve(rbo, false);
 401         if (unlikely(r != 0)) {
 402                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 403                 goto pflip_cleanup;
 404         }
 405         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 406         if (unlikely(r != 0)) {
 407                 radeon_bo_unreserve(rbo);
 408                 r = -EINVAL;
 409                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 413         radeon_bo_unreserve(rbo);
 414
 415         if (!ASIC_IS_AVIVO(rdev)) {
 416                 /* crtc offset is from display base addr not FB location */
 417                 base -= radeon_crtc->legacy_display_base_addr;
 418                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 419
 420                 if (tiling_flags & RADEON_TILING_MACRO) {
 421                         if (ASIC_IS_R300(rdev)) {
 422                                 base &= ~0x7ff;
 423                         } else {
 424                                 int byteshift = fb->bits_per_pixel >> 4;
 425                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 426                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 427                         }
 428                 } else {
 429                         int offset = crtc->y * pitch_pixels + crtc->x;
 430                         switch (fb->bits_per_pixel) {
 431                         case 8:
 432                         default:
 433                                 offset *= 1;
 434                                 break;
 435                         case 15:
 436                         case 16:
 437                                 offset *= 2;
 438                                 break;
 439                         case 24:
 440                                 offset *= 3;
 441                                 break;
 442                         case 32:
 443                                 offset *= 4;
 444                                 break;
 445                         }
 446                         base += offset;
 447                 }
 448                 base &= ~7;
 449         }
 450
 451         spin_lock_irqsave(&dev->event_lock, flags);
 452         work->new_crtc_base = base;
 453         spin_unlock_irqrestore(&dev->event_lock, flags);
 454
 455         /* update crtc fb */
 456         crtc->fb = fb;
 457
 458         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 459         if (r) {
 460                 DRM_ERROR("failed to get vblank before flip\n");
 461                 goto pflip_cleanup1;
 462         }
 463
 464         /* set the proper interrupt */
 465         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 466
 467         return 0;
 468
 469 pflip_cleanup1:
 470         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 471                 DRM_ERROR("failed to reserve new rbo in error path\n");
 472                 goto pflip_cleanup;
 473         }
 474         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 475                 DRM_ERROR("failed to unpin new rbo in error path\n");
 476         }
 477         radeon_bo_unreserve(rbo);
 478
 479 pflip_cleanup:
 480         spin_lock_irqsave(&dev->event_lock, flags);
 481         radeon_crtc->unpin_work = NULL;
 482 unlock_free:
 483         spin_unlock_irqrestore(&dev->event_lock, flags);
 484         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 485         radeon_fence_unref(&work->fence);
 486         kfree(work);
 487
 488         return r;
 489 }
 490
 491 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 492         .cursor_set = radeon_crtc_cursor_set,
 493         .cursor_move = radeon_crtc_cursor_move,
 494         .gamma_set = radeon_crtc_gamma_set,
 495         .set_config = drm_crtc_helper_set_config,
 496         .destroy = radeon_crtc_destroy,
 497         .page_flip = radeon_crtc_page_flip,
 498 };
 499
 500 static void radeon_crtc_init(struct drm_device *dev, int index)
 501 {
 502         struct radeon_device *rdev = dev->dev_private;
 503         struct radeon_crtc *radeon_crtc;
 504         int i;
 505
 506         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 507         if (radeon_crtc == NULL)
 508                 return;
 509
 510         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 511
 512         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 513         radeon_crtc->crtc_id = index;
 514         rdev->mode_info.crtcs[index] = radeon_crtc;
 515
 516 #if 0
 517         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 518         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 519         radeon_crtc->mode_set.num_connectors = 0;
 520 #endif
 521
 522         for (i = 0; i < 256; i++) {
 523                 radeon_crtc->lut_r[i] = i << 2;
 524                 radeon_crtc->lut_g[i] = i << 2;
 525                 radeon_crtc->lut_b[i] = i << 2;
 526         }
 527
 528         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 529                 radeon_atombios_init_crtc(dev, radeon_crtc);
 530         else
 531                 radeon_legacy_init_crtc(dev, radeon_crtc);
 532 }
 533
 534 static const char *encoder_names[36] = {
 535         "NONE",
 536         "INTERNAL_LVDS",
 537         "INTERNAL_TMDS1",
 538         "INTERNAL_TMDS2",
 539         "INTERNAL_DAC1",
 540         "INTERNAL_DAC2",
 541         "INTERNAL_SDVOA",
 542         "INTERNAL_SDVOB",
 543         "SI170B",
 544         "CH7303",
 545         "CH7301",
 546         "INTERNAL_DVO1",
 547         "EXTERNAL_SDVOA",
 548         "EXTERNAL_SDVOB",
 549         "TITFP513",
 550         "INTERNAL_LVTM1",
 551         "VT1623",
 552         "HDMI_SI1930",
 553         "HDMI_INTERNAL",
 554         "INTERNAL_KLDSCP_TMDS1",
 555         "INTERNAL_KLDSCP_DVO1",
 556         "INTERNAL_KLDSCP_DAC1",
 557         "INTERNAL_KLDSCP_DAC2",
 558         "SI178",
 559         "MVPU_FPGA",
 560         "INTERNAL_DDI",
 561         "VT1625",
 562         "HDMI_SI1932",
 563         "DP_AN9801",
 564         "DP_DP501",
 565         "INTERNAL_UNIPHY",
 566         "INTERNAL_KLDSCP_LVTMA",
 567         "INTERNAL_UNIPHY1",
 568         "INTERNAL_UNIPHY2",
 569         "NUTMEG",
 570         "TRAVIS",
 571 };
 572
 573 static const char *connector_names[15] = {
 574         "Unknown",
 575         "VGA",
 576         "DVI-I",
 577         "DVI-D",
 578         "DVI-A",
 579         "Composite",
 580         "S-video",
 581         "LVDS",
 582         "Component",
 583         "DIN",
 584         "DisplayPort",
 585         "HDMI-A",
 586         "HDMI-B",
 587         "TV",
 588         "eDP",
 589 };
 590
 591 static const char *hpd_names[6] = {
 592         "HPD1",
 593         "HPD2",
 594         "HPD3",
 595         "HPD4",
 596         "HPD5",
 597         "HPD6",
 598 };
 599
 600 static void radeon_print_display_setup(struct drm_device *dev)
 601 {
 602         struct drm_connector *connector;
 603         struct radeon_connector *radeon_connector;
 604         struct drm_encoder *encoder;
 605         struct radeon_encoder *radeon_encoder;
 606         uint32_t devices;
 607         int i = 0;
 608
 609         DRM_INFO("Radeon Display Connectors\n");
 610         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 611                 radeon_connector = to_radeon_connector(connector);
 612                 DRM_INFO("Connector %d:\n", i);
 613                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 614                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 615                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 616                 if (radeon_connector->ddc_bus) {
 617                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 618                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 619                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 620                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 621                                  radeon_connector->ddc_bus->rec.a_data_reg,
 622                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 623                                  radeon_connector->ddc_bus->rec.en_data_reg,
 624                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 625                                  radeon_connector->ddc_bus->rec.y_data_reg);
 626                         if (radeon_connector->router.ddc_valid)
 627                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 628                                          radeon_connector->router.ddc_mux_control_pin,
 629                                          radeon_connector->router.ddc_mux_state);
 630                         if (radeon_connector->router.cd_valid)
 631                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 632                                          radeon_connector->router.cd_mux_control_pin,
 633                                          radeon_connector->router.cd_mux_state);
 634                 } else {
 635                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 636                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 637                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 638                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 639                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 640                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 641                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 642                 }
 643                 DRM_INFO("  Encoders:\n");
 644                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 645                         radeon_encoder = to_radeon_encoder(encoder);
 646                         devices = radeon_encoder->devices & radeon_connector->devices;
 647                         if (devices) {
 648                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 649                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 650                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 651                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 652                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 653                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 654                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 655                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 656                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 657                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 658                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 659                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 660                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 661                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 662                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 663                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 664                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 665                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 666                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 667                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 668                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 669                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 670                         }
 671                 }
 672                 i++;
 673         }
 674 }
 675
 676 static bool radeon_setup_enc_conn(struct drm_device *dev)
 677 {
 678         struct radeon_device *rdev = dev->dev_private;
 679         bool ret = false;
 680
 681         if (rdev->bios) {
 682                 if (rdev->is_atom_bios) {
 683                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 684                         if (ret == false)
 685                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 686                 } else {
 687                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 688                         if (ret == false)
 689                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 690                 }
 691         } else {
 692                 if (!ASIC_IS_AVIVO(rdev))
 693                         ret = radeon_get_legacy_connector_info_from_table(dev);
 694         }
 695         if (ret) {
 696                 radeon_setup_encoder_clones(dev);
 697                 radeon_print_display_setup(dev);
 698         }
 699
 700         return ret;
 701 }
 702
 703 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 704 {
 705         struct drm_device *dev = radeon_connector->base.dev;
 706         struct radeon_device *rdev = dev->dev_private;
 707         int ret = 0;
 708
 709         /* on hw with routers, select right port */
 710         if (radeon_connector->router.ddc_valid)
 711                 radeon_router_select_ddc_port(radeon_connector);
 712
 713         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 714             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
 715             (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 716              ENCODER_OBJECT_ID_NONE)) {
 717                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 718
 719                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 720                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 721                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 722                                                               &dig->dp_i2c_bus->adapter);
 723                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 724                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 725                                                               &radeon_connector->ddc_bus->adapter);
 726         } else {
 727                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 728                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 729                                                               &radeon_connector->ddc_bus->adapter);
 730         }
 731
 732         if (!radeon_connector->edid) {
 733                 if (rdev->is_atom_bios) {
 734                         /* some laptops provide a hardcoded edid in rom for LCDs */
 735                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 736                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 737                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 738                 } else
 739                         /* some servers provide a hardcoded edid in rom for KVMs */
 740                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 741         }
 742         if (radeon_connector->edid) {
 743                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 744                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 745                 return ret;
 746         }
 747         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 748         return 0;
 749 }
 750
 751 /* avivo */
 752 static void avivo_get_fb_div(struct radeon_pll *pll,
 753                              u32 target_clock,
 754                              u32 post_div,
 755                              u32 ref_div,
 756                              u32 *fb_div,
 757                              u32 *frac_fb_div)
 758 {
 759         u32 tmp = post_div * ref_div;
 760
 761         tmp *= target_clock;
 762         *fb_div = tmp / pll->reference_freq;
 763         *frac_fb_div = tmp % pll->reference_freq;
 764
 765         if (*fb_div > pll->max_feedback_div)
 766                 *fb_div = pll->max_feedback_div;
 767         else if (*fb_div < pll->min_feedback_div)
 768                 *fb_div = pll->min_feedback_div;
 769 }
 770
 771 static u32 avivo_get_post_div(struct radeon_pll *pll,
 772                               u32 target_clock)
 773 {
 774         u32 vco, post_div, tmp;
 775
 776         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 777                 return pll->post_div;
 778
 779         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 780                 if (pll->flags & RADEON_PLL_IS_LCD)
 781                         vco = pll->lcd_pll_out_min;
 782                 else
 783                         vco = pll->pll_out_min;
 784         } else {
 785                 if (pll->flags & RADEON_PLL_IS_LCD)
 786                         vco = pll->lcd_pll_out_max;
 787                 else
 788                         vco = pll->pll_out_max;
 789         }
 790
 791         post_div = vco / target_clock;
 792         tmp = vco % target_clock;
 793
 794         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 795                 if (tmp)
 796                         post_div++;
 797         } else {
 798                 if (!tmp)
 799                         post_div--;
 800         }
 801
 802         if (post_div > pll->max_post_div)
 803                 post_div = pll->max_post_div;
 804         else if (post_div < pll->min_post_div)
 805                 post_div = pll->min_post_div;
 806
 807         return post_div;
 808 }
 809
 810 #define MAX_TOLERANCE 10
 811
 812 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 813                               u32 freq,
 814                               u32 *dot_clock_p,
 815                               u32 *fb_div_p,
 816                               u32 *frac_fb_div_p,
 817                               u32 *ref_div_p,
 818                               u32 *post_div_p)
 819 {
 820         u32 target_clock = freq / 10;
 821         u32 post_div = avivo_get_post_div(pll, target_clock);
 822         u32 ref_div = pll->min_ref_div;
 823         u32 fb_div = 0, frac_fb_div = 0, tmp;
 824
 825         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 826                 ref_div = pll->reference_div;
 827
 828         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 829                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 830                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 831                 if (frac_fb_div >= 5) {
 832                         frac_fb_div -= 5;
 833                         frac_fb_div = frac_fb_div / 10;
 834                         frac_fb_div++;
 835                 }
 836                 if (frac_fb_div >= 10) {
 837                         fb_div++;
 838                         frac_fb_div = 0;
 839                 }
 840         } else {
 841                 while (ref_div <= pll->max_ref_div) {
 842                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 843                                          &fb_div, &frac_fb_div);
 844                         if (frac_fb_div >= (pll->reference_freq / 2))
 845                                 fb_div++;
 846                         frac_fb_div = 0;
 847                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 848                         tmp = (tmp * 10000) / target_clock;
 849
 850                         if (tmp > (10000 + MAX_TOLERANCE))
 851                                 ref_div++;
 852                         else if (tmp >= (10000 - MAX_TOLERANCE))
 853                                 break;
 854                         else
 855                                 ref_div++;
 856                 }
 857         }
 858
 859         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 860                 (ref_div * post_div * 10);
 861         *fb_div_p = fb_div;
 862         *frac_fb_div_p = frac_fb_div;
 863         *ref_div_p = ref_div;
 864         *post_div_p = post_div;
 865         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 866                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 867 }
 868
 869 /* pre-avivo */
 870 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 871 {
 872         uint64_t mod;
 873
 874         n += d / 2;
 875
 876         mod = do_div(n, d);
 877         return n;
 878 }
 879
 880 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 881                                uint64_t freq,
 882                                uint32_t *dot_clock_p,
 883                                uint32_t *fb_div_p,
 884                                uint32_t *frac_fb_div_p,
 885                                uint32_t *ref_div_p,
 886                                uint32_t *post_div_p)
 887 {
 888         uint32_t min_ref_div = pll->min_ref_div;
 889         uint32_t max_ref_div = pll->max_ref_div;
 890         uint32_t min_post_div = pll->min_post_div;
 891         uint32_t max_post_div = pll->max_post_div;
 892         uint32_t min_fractional_feed_div = 0;
 893         uint32_t max_fractional_feed_div = 0;
 894         uint32_t best_vco = pll->best_vco;
 895         uint32_t best_post_div = 1;
 896         uint32_t best_ref_div = 1;
 897         uint32_t best_feedback_div = 1;
 898         uint32_t best_frac_feedback_div = 0;
 899         uint32_t best_freq = -1;
 900         uint32_t best_error = 0xffffffff;
 901         uint32_t best_vco_diff = 1;
 902         uint32_t post_div;
 903         u32 pll_out_min, pll_out_max;
 904
 905         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 906         freq = freq * 1000;
 907
 908         if (pll->flags & RADEON_PLL_IS_LCD) {
 909                 pll_out_min = pll->lcd_pll_out_min;
 910                 pll_out_max = pll->lcd_pll_out_max;
 911         } else {
 912                 pll_out_min = pll->pll_out_min;
 913                 pll_out_max = pll->pll_out_max;
 914         }
 915
 916         if (pll_out_min > 64800)
 917                 pll_out_min = 64800;
 918
 919         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 920                 min_ref_div = max_ref_div = pll->reference_div;
 921         else {
 922                 while (min_ref_div < max_ref_div-1) {
 923                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 924                         uint32_t pll_in = pll->reference_freq / mid;
 925                         if (pll_in < pll->pll_in_min)
 926                                 max_ref_div = mid;
 927                         else if (pll_in > pll->pll_in_max)
 928                                 min_ref_div = mid;
 929                         else
 930                                 break;
 931                 }
 932         }
 933
 934         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 935                 min_post_div = max_post_div = pll->post_div;
 936
 937         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 938                 min_fractional_feed_div = pll->min_frac_feedback_div;
 939                 max_fractional_feed_div = pll->max_frac_feedback_div;
 940         }
 941
 942         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 943                 uint32_t ref_div;
 944
 945                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 946                         continue;
 947
 948                 /* legacy radeons only have a few post_divs */
 949                 if (pll->flags & RADEON_PLL_LEGACY) {
 950                         if ((post_div == 5) ||
 951                             (post_div == 7) ||
 952                             (post_div == 9) ||
 953                             (post_div == 10) ||
 954                             (post_div == 11) ||
 955                             (post_div == 13) ||
 956                             (post_div == 14) ||
 957                             (post_div == 15))
 958                                 continue;
 959                 }
 960
 961                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 962                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 963                         uint32_t pll_in = pll->reference_freq / ref_div;
 964                         uint32_t min_feed_div = pll->min_feedback_div;
 965                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 966
 967                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 968                                 continue;
 969
 970                         while (min_feed_div < max_feed_div) {
 971                                 uint32_t vco;
 972                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 973                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 974                                 uint32_t frac_feedback_div;
 975                                 uint64_t tmp;
 976
 977                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 978
 979                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 980                                 vco = radeon_div(tmp, ref_div);
 981
 982                                 if (vco < pll_out_min) {
 983                                         min_feed_div = feedback_div + 1;
 984                                         continue;
 985                                 } else if (vco > pll_out_max) {
 986                                         max_feed_div = feedback_div;
 987                                         continue;
 988                                 }
 989
 990                                 while (min_frac_feed_div < max_frac_feed_div) {
 991                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 992                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 993                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 994                                         current_freq = radeon_div(tmp, ref_div * post_div);
 995
 996                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 997                                                 if (freq < current_freq)
 998                                                         error = 0xffffffff;
 999                                                 else
1000                                                         error = freq - current_freq;
1001                                         } else
1002                                                 error = abs(current_freq - freq);
1003                                         vco_diff = abs(vco - best_vco);
1004
1005                                         if ((best_vco == 0 && error < best_error) ||
1006                                             (best_vco != 0 &&
1007                                              ((best_error > 100 && error < best_error - 100) ||
1008                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1009                                                 best_post_div = post_div;
1010                                                 best_ref_div = ref_div;
1011                                                 best_feedback_div = feedback_div;
1012                                                 best_frac_feedback_div = frac_feedback_div;
1013                                                 best_freq = current_freq;
1014                                                 best_error = error;
1015                                                 best_vco_diff = vco_diff;
1016                                         } else if (current_freq == freq) {
1017                                                 if (best_freq == -1) {
1018                                                         best_post_div = post_div;
1019                                                         best_ref_div = ref_div;
1020                                                         best_feedback_div = feedback_div;
1021                                                         best_frac_feedback_div = frac_feedback_div;
1022                                                         best_freq = current_freq;
1023                                                         best_error = error;
1024                                                         best_vco_diff = vco_diff;
1025                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1026                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1027                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1028                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1029                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1030                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1031                                                         best_post_div = post_div;
1032                                                         best_ref_div = ref_div;
1033                                                         best_feedback_div = feedback_div;
1034                                                         best_frac_feedback_div = frac_feedback_div;
1035                                                         best_freq = current_freq;
1036                                                         best_error = error;
1037                                                         best_vco_diff = vco_diff;
1038                                                 }
1039                                         }
1040                                         if (current_freq < freq)
1041                                                 min_frac_feed_div = frac_feedback_div + 1;
1042                                         else
1043                                                 max_frac_feed_div = frac_feedback_div;
1044                                 }
1045                                 if (current_freq < freq)
1046                                         min_feed_div = feedback_div + 1;
1047                                 else
1048                                         max_feed_div = feedback_div;
1049                         }
1050                 }
1051         }
1052
1053         *dot_clock_p = best_freq / 10000;
1054         *fb_div_p = best_feedback_div;
1055         *frac_fb_div_p = best_frac_feedback_div;
1056         *ref_div_p = best_ref_div;
1057         *post_div_p = best_post_div;
1058         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1059                       (long long)freq,
1060                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1061                       best_ref_div, best_post_div);
1062
1063 }
1064
1065 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1066 {
1067         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1068
1069         if (radeon_fb->obj) {
1070                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1071         }
1072         drm_framebuffer_cleanup(fb);
1073         kfree(radeon_fb);
1074 }
1075
1076 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1077                                                   struct drm_file *file_priv,
1078                                                   unsigned int *handle)
1079 {
1080         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1081
1082         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1083 }
1084
1085 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1086         .destroy = radeon_user_framebuffer_destroy,
1087         .create_handle = radeon_user_framebuffer_create_handle,
1088 };
1089
1090 int
1091 radeon_framebuffer_init(struct drm_device *dev,
1092                         struct radeon_framebuffer *rfb,
1093                         struct drm_mode_fb_cmd2 *mode_cmd,
1094                         struct drm_gem_object *obj)
1095 {
1096         int ret;
1097         rfb->obj = obj;
1098         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1099         if (ret) {
1100                 rfb->obj = NULL;
1101                 return ret;
1102         }
1103         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1104         return 0;
1105 }
1106
1107 static struct drm_framebuffer *
1108 radeon_user_framebuffer_create(struct drm_device *dev,
1109                                struct drm_file *file_priv,
1110                                struct drm_mode_fb_cmd2 *mode_cmd)
1111 {
1112         struct drm_gem_object *obj;
1113         struct radeon_framebuffer *radeon_fb;
1114         int ret;
1115
1116         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1117         if (obj ==  NULL) {
1118                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1119                         "can't create framebuffer\n", mode_cmd->handles[0]);
1120                 return ERR_PTR(-ENOENT);
1121         }
1122
1123         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1124         if (radeon_fb == NULL)
1125                 return ERR_PTR(-ENOMEM);
1126
1127         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1128         if (ret) {
1129                 kfree(radeon_fb);
1130                 drm_gem_object_unreference_unlocked(obj);
1131                 return NULL;
1132         }
1133
1134         return &radeon_fb->base;
1135 }
1136
1137 static void radeon_output_poll_changed(struct drm_device *dev)
1138 {
1139         struct radeon_device *rdev = dev->dev_private;
1140         radeon_fb_output_poll_changed(rdev);
1141 }
1142
1143 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1144         .fb_create = radeon_user_framebuffer_create,
1145         .output_poll_changed = radeon_output_poll_changed
1146 };
1147
1148 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1149 {       { 0, "driver" },
1150         { 1, "bios" },
1151 };
1152
1153 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1154 {       { TV_STD_NTSC, "ntsc" },
1155         { TV_STD_PAL, "pal" },
1156         { TV_STD_PAL_M, "pal-m" },
1157         { TV_STD_PAL_60, "pal-60" },
1158         { TV_STD_NTSC_J, "ntsc-j" },
1159         { TV_STD_SCART_PAL, "scart-pal" },
1160         { TV_STD_PAL_CN, "pal-cn" },
1161         { TV_STD_SECAM, "secam" },
1162 };
1163
1164 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1165 {       { UNDERSCAN_OFF, "off" },
1166         { UNDERSCAN_ON, "on" },
1167         { UNDERSCAN_AUTO, "auto" },
1168 };
1169
1170 static int radeon_modeset_create_props(struct radeon_device *rdev)
1171 {
1172         int sz;
1173
1174         if (rdev->is_atom_bios) {
1175                 rdev->mode_info.coherent_mode_property =
1176                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1177                 if (!rdev->mode_info.coherent_mode_property)
1178                         return -ENOMEM;
1179         }
1180
1181         if (!ASIC_IS_AVIVO(rdev)) {
1182                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1183                 rdev->mode_info.tmds_pll_property =
1184                         drm_property_create_enum(rdev->ddev, 0,
1185                                             "tmds_pll",
1186                                             radeon_tmds_pll_enum_list, sz);
1187         }
1188
1189         rdev->mode_info.load_detect_property =
1190                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1191         if (!rdev->mode_info.load_detect_property)
1192                 return -ENOMEM;
1193
1194         drm_mode_create_scaling_mode_property(rdev->ddev);
1195
1196         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1197         rdev->mode_info.tv_std_property =
1198                 drm_property_create_enum(rdev->ddev, 0,
1199                                     "tv standard",
1200                                     radeon_tv_std_enum_list, sz);
1201
1202         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1203         rdev->mode_info.underscan_property =
1204                 drm_property_create_enum(rdev->ddev, 0,
1205                                     "underscan",
1206                                     radeon_underscan_enum_list, sz);
1207
1208         rdev->mode_info.underscan_hborder_property =
1209                 drm_property_create_range(rdev->ddev, 0,
1210                                         "underscan hborder", 0, 128);
1211         if (!rdev->mode_info.underscan_hborder_property)
1212                 return -ENOMEM;
1213
1214         rdev->mode_info.underscan_vborder_property =
1215                 drm_property_create_range(rdev->ddev, 0,
1216                                         "underscan vborder", 0, 128);
1217         if (!rdev->mode_info.underscan_vborder_property)
1218                 return -ENOMEM;
1219
1220         return 0;
1221 }
1222
1223 void radeon_update_display_priority(struct radeon_device *rdev)
1224 {
1225         /* adjustment options for the display watermarks */
1226         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1227                 /* set display priority to high for r3xx, rv515 chips
1228                  * this avoids flickering due to underflow to the
1229                  * display controllers during heavy acceleration.
1230                  * Don't force high on rs4xx igp chips as it seems to
1231                  * affect the sound card.  See kernel bug 15982.
1232                  */
1233                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1234                     !(rdev->flags & RADEON_IS_IGP))
1235                         rdev->disp_priority = 2;
1236                 else
1237                         rdev->disp_priority = 0;
1238         } else
1239                 rdev->disp_priority = radeon_disp_priority;
1240
1241 }
1242
1243 int radeon_modeset_init(struct radeon_device *rdev)
1244 {
1245         int i;
1246         int ret;
1247
1248         drm_mode_config_init(rdev->ddev);
1249         rdev->mode_info.mode_config_initialized = true;
1250
1251         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1252
1253         if (ASIC_IS_DCE5(rdev)) {
1254                 rdev->ddev->mode_config.max_width = 16384;
1255                 rdev->ddev->mode_config.max_height = 16384;
1256         } else if (ASIC_IS_AVIVO(rdev)) {
1257                 rdev->ddev->mode_config.max_width = 8192;
1258                 rdev->ddev->mode_config.max_height = 8192;
1259         } else {
1260                 rdev->ddev->mode_config.max_width = 4096;
1261                 rdev->ddev->mode_config.max_height = 4096;
1262         }
1263
1264         rdev->ddev->mode_config.preferred_depth = 24;
1265         rdev->ddev->mode_config.prefer_shadow = 1;
1266
1267         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1268
1269         ret = radeon_modeset_create_props(rdev);
1270         if (ret) {
1271                 return ret;
1272         }
1273
1274         /* init i2c buses */
1275         radeon_i2c_init(rdev);
1276
1277         /* check combios for a valid hardcoded EDID - Sun servers */
1278         if (!rdev->is_atom_bios) {
1279                 /* check for hardcoded EDID in BIOS */
1280                 radeon_combios_check_hardcoded_edid(rdev);
1281         }
1282
1283         /* allocate crtcs */
1284         for (i = 0; i < rdev->num_crtc; i++) {
1285                 radeon_crtc_init(rdev->ddev, i);
1286         }
1287
1288         /* okay we should have all the bios connectors */
1289         ret = radeon_setup_enc_conn(rdev->ddev);
1290         if (!ret) {
1291                 return ret;
1292         }
1293
1294         /* init dig PHYs, disp eng pll */
1295         if (rdev->is_atom_bios) {
1296                 radeon_atom_encoder_init(rdev);
1297                 radeon_atom_dcpll_init(rdev);
1298         }
1299
1300         /* initialize hpd */
1301         radeon_hpd_init(rdev);
1302
1303         /* Initialize power management */
1304         radeon_pm_init(rdev);
1305
1306         radeon_fbdev_init(rdev);
1307         drm_kms_helper_poll_init(rdev->ddev);
1308
1309         return 0;
1310 }
1311
1312 void radeon_modeset_fini(struct radeon_device *rdev)
1313 {
1314         radeon_fbdev_fini(rdev);
1315         kfree(rdev->mode_info.bios_hardcoded_edid);
1316         radeon_pm_fini(rdev);
1317
1318         if (rdev->mode_info.mode_config_initialized) {
1319                 drm_kms_helper_poll_fini(rdev->ddev);
1320                 radeon_hpd_fini(rdev);
1321                 drm_mode_config_cleanup(rdev->ddev);
1322                 rdev->mode_info.mode_config_initialized = false;
1323         }
1324         /* free i2c buses */
1325         radeon_i2c_fini(rdev);
1326 }
1327
1328 static bool is_hdtv_mode(struct drm_display_mode *mode)
1329 {
1330         /* try and guess if this is a tv or a monitor */
1331         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1332             (mode->vdisplay == 576) || /* 576p */
1333             (mode->vdisplay == 720) || /* 720p */
1334             (mode->vdisplay == 1080)) /* 1080p */
1335                 return true;
1336         else
1337                 return false;
1338 }
1339
1340 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1341                                 struct drm_display_mode *mode,
1342                                 struct drm_display_mode *adjusted_mode)
1343 {
1344         struct drm_device *dev = crtc->dev;
1345         struct radeon_device *rdev = dev->dev_private;
1346         struct drm_encoder *encoder;
1347         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1348         struct radeon_encoder *radeon_encoder;
1349         struct drm_connector *connector;
1350         struct radeon_connector *radeon_connector;
1351         bool first = true;
1352         u32 src_v = 1, dst_v = 1;
1353         u32 src_h = 1, dst_h = 1;
1354
1355         radeon_crtc->h_border = 0;
1356         radeon_crtc->v_border = 0;
1357
1358         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1359                 if (encoder->crtc != crtc)
1360                         continue;
1361                 radeon_encoder = to_radeon_encoder(encoder);
1362                 connector = radeon_get_connector_for_encoder(encoder);
1363                 radeon_connector = to_radeon_connector(connector);
1364
1365                 if (first) {
1366                         /* set scaling */
1367                         if (radeon_encoder->rmx_type == RMX_OFF)
1368                                 radeon_crtc->rmx_type = RMX_OFF;
1369                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1370                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1371                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1372                         else
1373                                 radeon_crtc->rmx_type = RMX_OFF;
1374                         /* copy native mode */
1375                         memcpy(&radeon_crtc->native_mode,
1376                                &radeon_encoder->native_mode,
1377                                 sizeof(struct drm_display_mode));
1378                         src_v = crtc->mode.vdisplay;
1379                         dst_v = radeon_crtc->native_mode.vdisplay;
1380                         src_h = crtc->mode.hdisplay;
1381                         dst_h = radeon_crtc->native_mode.hdisplay;
1382
1383                         /* fix up for overscan on hdmi */
1384                         if (ASIC_IS_AVIVO(rdev) &&
1385                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1386                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1387                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1388                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1389                               is_hdtv_mode(mode)))) {
1390                                 if (radeon_encoder->underscan_hborder != 0)
1391                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1392                                 else
1393                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1394                                 if (radeon_encoder->underscan_vborder != 0)
1395                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1396                                 else
1397                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1398                                 radeon_crtc->rmx_type = RMX_FULL;
1399                                 src_v = crtc->mode.vdisplay;
1400                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1401                                 src_h = crtc->mode.hdisplay;
1402                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1403                         }
1404                         first = false;
1405                 } else {
1406                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1407                                 /* WARNING: Right now this can't happen but
1408                                  * in the future we need to check that scaling
1409                                  * are consistent across different encoder
1410                                  * (ie all encoder can work with the same
1411                                  *  scaling).
1412                                  */
1413                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1414                                 return false;
1415                         }
1416                 }
1417         }
1418         if (radeon_crtc->rmx_type != RMX_OFF) {
1419                 fixed20_12 a, b;
1420                 a.full = dfixed_const(src_v);
1421                 b.full = dfixed_const(dst_v);
1422                 radeon_crtc->vsc.full = dfixed_div(a, b);
1423                 a.full = dfixed_const(src_h);
1424                 b.full = dfixed_const(dst_h);
1425                 radeon_crtc->hsc.full = dfixed_div(a, b);
1426         } else {
1427                 radeon_crtc->vsc.full = dfixed_const(1);
1428                 radeon_crtc->hsc.full = dfixed_const(1);
1429         }
1430         return true;
1431 }
1432
1433 /*
1434  * Retrieve current video scanout position of crtc on a given gpu.
1435  *
1436  * \param dev Device to query.
1437  * \param crtc Crtc to query.
1438  * \param *vpos Location where vertical scanout position should be stored.
1439  * \param *hpos Location where horizontal scanout position should go.
1440  *
1441  * Returns vpos as a positive number while in active scanout area.
1442  * Returns vpos as a negative number inside vblank, counting the number
1443  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1444  * until start of active scanout / end of vblank."
1445  *
1446  * \return Flags, or'ed together as follows:
1447  *
1448  * DRM_SCANOUTPOS_VALID = Query successful.
1449  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1450  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1451  * this flag means that returned position may be offset by a constant but
1452  * unknown small number of scanlines wrt. real scanout position.
1453  *
1454  */
1455 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1456 {
1457         u32 stat_crtc = 0, vbl = 0, position = 0;
1458         int vbl_start, vbl_end, vtotal, ret = 0;
1459         bool in_vbl = true;
1460
1461         struct radeon_device *rdev = dev->dev_private;
1462
1463         if (ASIC_IS_DCE4(rdev)) {
1464                 if (crtc == 0) {
1465                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1466                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1467                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1468                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1469                         ret |= DRM_SCANOUTPOS_VALID;
1470                 }
1471                 if (crtc == 1) {
1472                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1473                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1474                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1475                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1476                         ret |= DRM_SCANOUTPOS_VALID;
1477                 }
1478                 if (crtc == 2) {
1479                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1480                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1481                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1482                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1483                         ret |= DRM_SCANOUTPOS_VALID;
1484                 }
1485                 if (crtc == 3) {
1486                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1487                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1488                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1489                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1490                         ret |= DRM_SCANOUTPOS_VALID;
1491                 }
1492                 if (crtc == 4) {
1493                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1494                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1495                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1496                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1497                         ret |= DRM_SCANOUTPOS_VALID;
1498                 }
1499                 if (crtc == 5) {
1500                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1501                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1502                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1503                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1504                         ret |= DRM_SCANOUTPOS_VALID;
1505                 }
1506         } else if (ASIC_IS_AVIVO(rdev)) {
1507                 if (crtc == 0) {
1508                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1509                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1510                         ret |= DRM_SCANOUTPOS_VALID;
1511                 }
1512                 if (crtc == 1) {
1513                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1514                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1515                         ret |= DRM_SCANOUTPOS_VALID;
1516                 }
1517         } else {
1518                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1519                 if (crtc == 0) {
1520                         /* Assume vbl_end == 0, get vbl_start from
1521                          * upper 16 bits.
1522                          */
1523                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1524                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1525                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1526                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1527                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1528                         if (!(stat_crtc & 1))
1529                                 in_vbl = false;
1530
1531                         ret |= DRM_SCANOUTPOS_VALID;
1532                 }
1533                 if (crtc == 1) {
1534                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1535                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1536                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1537                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1538                         if (!(stat_crtc & 1))
1539                                 in_vbl = false;
1540
1541                         ret |= DRM_SCANOUTPOS_VALID;
1542                 }
1543         }
1544
1545         /* Decode into vertical and horizontal scanout position. */
1546         *vpos = position & 0x1fff;
1547         *hpos = (position >> 16) & 0x1fff;
1548
1549         /* Valid vblank area boundaries from gpu retrieved? */
1550         if (vbl > 0) {
1551                 /* Yes: Decode. */
1552                 ret |= DRM_SCANOUTPOS_ACCURATE;
1553                 vbl_start = vbl & 0x1fff;
1554                 vbl_end = (vbl >> 16) & 0x1fff;
1555         }
1556         else {
1557                 /* No: Fake something reasonable which gives at least ok results. */
1558                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1559                 vbl_end = 0;
1560         }
1561
1562         /* Test scanout position against vblank region. */
1563         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1564                 in_vbl = false;
1565
1566         /* Check if inside vblank area and apply corrective offsets:
1567          * vpos will then be >=0 in video scanout area, but negative
1568          * within vblank area, counting down the number of lines until
1569          * start of scanout.
1570          */
1571
1572         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1573         if (in_vbl && (*vpos >= vbl_start)) {
1574                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1575                 *vpos = *vpos - vtotal;
1576         }
1577
1578         /* Correct for shifted end of vbl at vbl_end. */
1579         *vpos = *vpos - vbl_end;
1580
1581         /* In vblank? */
1582         if (in_vbl)
1583                 ret |= DRM_SCANOUTPOS_INVBL;
1584
1585         return ret;
1586 }