2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector *connector);
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
78 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
138 legacy_crtc_load_lut(crtc);
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t size)
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
173 /* userspace palettes are always correct as is */
174 for (i = 0; i < 256; i++) {
175 radeon_crtc->lut_r[i] = red[i] >> 6;
176 radeon_crtc->lut_g[i] = green[i] >> 6;
177 radeon_crtc->lut_b[i] = blue[i] >> 6;
179 radeon_crtc_load_lut(crtc);
182 static void radeon_crtc_destroy(struct drm_crtc *crtc)
184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
186 drm_crtc_cleanup(crtc);
190 static const struct drm_crtc_funcs radeon_crtc_funcs = {
191 .cursor_set = radeon_crtc_cursor_set,
192 .cursor_move = radeon_crtc_cursor_move,
193 .gamma_set = radeon_crtc_gamma_set,
194 .set_config = drm_crtc_helper_set_config,
195 .destroy = radeon_crtc_destroy,
198 static void radeon_crtc_init(struct drm_device *dev, int index)
200 struct radeon_device *rdev = dev->dev_private;
201 struct radeon_crtc *radeon_crtc;
204 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
205 if (radeon_crtc == NULL)
208 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
210 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
211 radeon_crtc->crtc_id = index;
212 rdev->mode_info.crtcs[index] = radeon_crtc;
215 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
216 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
217 radeon_crtc->mode_set.num_connectors = 0;
220 for (i = 0; i < 256; i++) {
221 radeon_crtc->lut_r[i] = i << 2;
222 radeon_crtc->lut_g[i] = i << 2;
223 radeon_crtc->lut_b[i] = i << 2;
226 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
227 radeon_atombios_init_crtc(dev, radeon_crtc);
229 radeon_legacy_init_crtc(dev, radeon_crtc);
232 static const char *encoder_names[34] = {
252 "INTERNAL_KLDSCP_TMDS1",
253 "INTERNAL_KLDSCP_DVO1",
254 "INTERNAL_KLDSCP_DAC1",
255 "INTERNAL_KLDSCP_DAC2",
264 "INTERNAL_KLDSCP_LVTMA",
269 static const char *connector_names[15] = {
287 static const char *hpd_names[7] = {
297 static void radeon_print_display_setup(struct drm_device *dev)
299 struct drm_connector *connector;
300 struct radeon_connector *radeon_connector;
301 struct drm_encoder *encoder;
302 struct radeon_encoder *radeon_encoder;
306 DRM_INFO("Radeon Display Connectors\n");
307 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
308 radeon_connector = to_radeon_connector(connector);
309 DRM_INFO("Connector %d:\n", i);
310 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
311 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
312 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
313 if (radeon_connector->ddc_bus) {
314 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
315 radeon_connector->ddc_bus->rec.mask_clk_reg,
316 radeon_connector->ddc_bus->rec.mask_data_reg,
317 radeon_connector->ddc_bus->rec.a_clk_reg,
318 radeon_connector->ddc_bus->rec.a_data_reg,
319 radeon_connector->ddc_bus->rec.en_clk_reg,
320 radeon_connector->ddc_bus->rec.en_data_reg,
321 radeon_connector->ddc_bus->rec.y_clk_reg,
322 radeon_connector->ddc_bus->rec.y_data_reg);
324 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
325 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
326 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
327 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
329 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
330 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
332 DRM_INFO(" Encoders:\n");
333 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
334 radeon_encoder = to_radeon_encoder(encoder);
335 devices = radeon_encoder->devices & radeon_connector->devices;
337 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
338 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
339 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
340 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
341 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
342 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
343 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
344 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
345 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
346 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
347 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
348 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
349 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
350 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
351 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
352 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
353 if (devices & ATOM_DEVICE_TV1_SUPPORT)
354 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
355 if (devices & ATOM_DEVICE_CV_SUPPORT)
356 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
363 static bool radeon_setup_enc_conn(struct drm_device *dev)
365 struct radeon_device *rdev = dev->dev_private;
366 struct drm_connector *drm_connector;
370 if (rdev->is_atom_bios) {
371 if (rdev->family >= CHIP_R600)
372 ret = radeon_get_atom_connector_info_from_object_table(dev);
374 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
376 ret = radeon_get_legacy_connector_info_from_bios(dev);
378 ret = radeon_get_legacy_connector_info_from_table(dev);
381 if (!ASIC_IS_AVIVO(rdev))
382 ret = radeon_get_legacy_connector_info_from_table(dev);
385 radeon_setup_encoder_clones(dev);
386 radeon_print_display_setup(dev);
387 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
388 radeon_ddc_dump(drm_connector);
394 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
396 struct drm_device *dev = radeon_connector->base.dev;
397 struct radeon_device *rdev = dev->dev_private;
400 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
401 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
402 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
403 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
404 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
405 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
407 if (!radeon_connector->ddc_bus)
409 if (!radeon_connector->edid) {
410 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
412 /* some servers provide a hardcoded edid in rom for KVMs */
413 if (!radeon_connector->edid)
414 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
415 if (radeon_connector->edid) {
416 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
417 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
420 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
424 static int radeon_ddc_dump(struct drm_connector *connector)
427 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
430 if (!radeon_connector->ddc_bus)
432 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
439 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
449 static void radeon_compute_pll_legacy(struct radeon_pll *pll,
451 uint32_t *dot_clock_p,
453 uint32_t *frac_fb_div_p,
455 uint32_t *post_div_p)
457 uint32_t min_ref_div = pll->min_ref_div;
458 uint32_t max_ref_div = pll->max_ref_div;
459 uint32_t min_post_div = pll->min_post_div;
460 uint32_t max_post_div = pll->max_post_div;
461 uint32_t min_fractional_feed_div = 0;
462 uint32_t max_fractional_feed_div = 0;
463 uint32_t best_vco = pll->best_vco;
464 uint32_t best_post_div = 1;
465 uint32_t best_ref_div = 1;
466 uint32_t best_feedback_div = 1;
467 uint32_t best_frac_feedback_div = 0;
468 uint32_t best_freq = -1;
469 uint32_t best_error = 0xffffffff;
470 uint32_t best_vco_diff = 1;
472 u32 pll_out_min, pll_out_max;
474 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
477 if (pll->flags & RADEON_PLL_IS_LCD) {
478 pll_out_min = pll->lcd_pll_out_min;
479 pll_out_max = pll->lcd_pll_out_max;
481 pll_out_min = pll->pll_out_min;
482 pll_out_max = pll->pll_out_max;
485 if (pll->flags & RADEON_PLL_USE_REF_DIV)
486 min_ref_div = max_ref_div = pll->reference_div;
488 while (min_ref_div < max_ref_div-1) {
489 uint32_t mid = (min_ref_div + max_ref_div) / 2;
490 uint32_t pll_in = pll->reference_freq / mid;
491 if (pll_in < pll->pll_in_min)
493 else if (pll_in > pll->pll_in_max)
500 if (pll->flags & RADEON_PLL_USE_POST_DIV)
501 min_post_div = max_post_div = pll->post_div;
503 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
504 min_fractional_feed_div = pll->min_frac_feedback_div;
505 max_fractional_feed_div = pll->max_frac_feedback_div;
508 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
511 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
514 /* legacy radeons only have a few post_divs */
515 if (pll->flags & RADEON_PLL_LEGACY) {
516 if ((post_div == 5) ||
527 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
528 uint32_t feedback_div, current_freq = 0, error, vco_diff;
529 uint32_t pll_in = pll->reference_freq / ref_div;
530 uint32_t min_feed_div = pll->min_feedback_div;
531 uint32_t max_feed_div = pll->max_feedback_div + 1;
533 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
536 while (min_feed_div < max_feed_div) {
538 uint32_t min_frac_feed_div = min_fractional_feed_div;
539 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
540 uint32_t frac_feedback_div;
543 feedback_div = (min_feed_div + max_feed_div) / 2;
545 tmp = (uint64_t)pll->reference_freq * feedback_div;
546 vco = radeon_div(tmp, ref_div);
548 if (vco < pll_out_min) {
549 min_feed_div = feedback_div + 1;
551 } else if (vco > pll_out_max) {
552 max_feed_div = feedback_div;
556 while (min_frac_feed_div < max_frac_feed_div) {
557 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
558 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
559 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
560 current_freq = radeon_div(tmp, ref_div * post_div);
562 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
563 error = freq - current_freq;
564 error = error < 0 ? 0xffffffff : error;
566 error = abs(current_freq - freq);
567 vco_diff = abs(vco - best_vco);
569 if ((best_vco == 0 && error < best_error) ||
571 (error < best_error - 100 ||
572 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
573 best_post_div = post_div;
574 best_ref_div = ref_div;
575 best_feedback_div = feedback_div;
576 best_frac_feedback_div = frac_feedback_div;
577 best_freq = current_freq;
579 best_vco_diff = vco_diff;
580 } else if (current_freq == freq) {
581 if (best_freq == -1) {
582 best_post_div = post_div;
583 best_ref_div = ref_div;
584 best_feedback_div = feedback_div;
585 best_frac_feedback_div = frac_feedback_div;
586 best_freq = current_freq;
588 best_vco_diff = vco_diff;
589 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
590 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
591 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
592 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
593 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
594 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
595 best_post_div = post_div;
596 best_ref_div = ref_div;
597 best_feedback_div = feedback_div;
598 best_frac_feedback_div = frac_feedback_div;
599 best_freq = current_freq;
601 best_vco_diff = vco_diff;
604 if (current_freq < freq)
605 min_frac_feed_div = frac_feedback_div + 1;
607 max_frac_feed_div = frac_feedback_div;
609 if (current_freq < freq)
610 min_feed_div = feedback_div + 1;
612 max_feed_div = feedback_div;
617 *dot_clock_p = best_freq / 10000;
618 *fb_div_p = best_feedback_div;
619 *frac_fb_div_p = best_frac_feedback_div;
620 *ref_div_p = best_ref_div;
621 *post_div_p = best_post_div;
625 calc_fb_div(struct radeon_pll *pll,
630 uint32_t *fb_div_frac)
632 fixed20_12 feedback_divider, a, b;
635 vco_freq = freq * post_div;
636 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
637 a.full = rfixed_const(pll->reference_freq);
638 feedback_divider.full = rfixed_const(vco_freq);
639 feedback_divider.full = rfixed_div(feedback_divider, a);
640 a.full = rfixed_const(ref_div);
641 feedback_divider.full = rfixed_mul(feedback_divider, a);
643 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
644 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
645 a.full = rfixed_const(10);
646 feedback_divider.full = rfixed_mul(feedback_divider, a);
647 feedback_divider.full += rfixed_const_half(0);
648 feedback_divider.full = rfixed_floor(feedback_divider);
649 feedback_divider.full = rfixed_div(feedback_divider, a);
651 /* *fb_div = floor(feedback_divider); */
652 a.full = rfixed_floor(feedback_divider);
653 *fb_div = rfixed_trunc(a);
654 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
655 a.full = rfixed_const(10);
656 b.full = rfixed_mul(feedback_divider, a);
658 feedback_divider.full = rfixed_floor(feedback_divider);
659 feedback_divider.full = rfixed_mul(feedback_divider, a);
660 feedback_divider.full = b.full - feedback_divider.full;
661 *fb_div_frac = rfixed_trunc(feedback_divider);
663 /* *fb_div = floor(feedback_divider + 0.5); */
664 feedback_divider.full += rfixed_const_half(0);
665 feedback_divider.full = rfixed_floor(feedback_divider);
667 *fb_div = rfixed_trunc(feedback_divider);
671 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
678 calc_fb_ref_div(struct radeon_pll *pll,
682 uint32_t *fb_div_frac,
685 fixed20_12 ffreq, max_error, error, pll_out, a;
687 u32 pll_out_min, pll_out_max;
689 if (pll->flags & RADEON_PLL_IS_LCD) {
690 pll_out_min = pll->lcd_pll_out_min;
691 pll_out_max = pll->lcd_pll_out_max;
693 pll_out_min = pll->pll_out_min;
694 pll_out_max = pll->pll_out_max;
697 ffreq.full = rfixed_const(freq);
698 /* max_error = ffreq * 0.0025; */
699 a.full = rfixed_const(400);
700 max_error.full = rfixed_div(ffreq, a);
702 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
703 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
704 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
705 vco = vco / ((*ref_div) * 10);
707 if ((vco < pll_out_min) || (vco > pll_out_max))
710 /* pll_out = vco / post_div; */
711 a.full = rfixed_const(post_div);
712 pll_out.full = rfixed_const(vco);
713 pll_out.full = rfixed_div(pll_out, a);
715 if (pll_out.full >= ffreq.full) {
716 error.full = pll_out.full - ffreq.full;
717 if (error.full <= max_error.full)
725 static void radeon_compute_pll_new(struct radeon_pll *pll,
727 uint32_t *dot_clock_p,
729 uint32_t *frac_fb_div_p,
731 uint32_t *post_div_p)
733 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
734 u32 best_freq = 0, vco_frequency;
735 u32 pll_out_min, pll_out_max;
737 if (pll->flags & RADEON_PLL_IS_LCD) {
738 pll_out_min = pll->lcd_pll_out_min;
739 pll_out_max = pll->lcd_pll_out_max;
741 pll_out_min = pll->pll_out_min;
742 pll_out_max = pll->pll_out_max;
745 /* freq = freq / 10; */
748 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
749 post_div = pll->post_div;
750 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
753 vco_frequency = freq * post_div;
754 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
757 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
758 ref_div = pll->reference_div;
759 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
761 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
765 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
766 if (pll->flags & RADEON_PLL_LEGACY) {
767 if ((post_div == 5) ||
775 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
778 vco_frequency = freq * post_div;
779 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
781 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
782 ref_div = pll->reference_div;
783 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
785 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
788 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
794 best_freq = pll->reference_freq * 10 * fb_div;
795 best_freq += pll->reference_freq * fb_div_frac;
796 best_freq = best_freq / (ref_div * post_div);
800 DRM_ERROR("Couldn't find valid PLL dividers\n");
802 *dot_clock_p = best_freq / 10;
804 *frac_fb_div_p = fb_div_frac;
805 *ref_div_p = ref_div;
806 *post_div_p = post_div;
808 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
811 void radeon_compute_pll(struct radeon_pll *pll,
813 uint32_t *dot_clock_p,
815 uint32_t *frac_fb_div_p,
817 uint32_t *post_div_p)
821 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
822 frac_fb_div_p, ref_div_p, post_div_p);
824 case PLL_ALGO_LEGACY:
826 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
827 frac_fb_div_p, ref_div_p, post_div_p);
832 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
834 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
835 struct drm_device *dev = fb->dev;
838 radeonfb_remove(dev, fb);
841 drm_gem_object_unreference_unlocked(radeon_fb->obj);
842 drm_framebuffer_cleanup(fb);
846 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
847 struct drm_file *file_priv,
848 unsigned int *handle)
850 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
852 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
855 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
856 .destroy = radeon_user_framebuffer_destroy,
857 .create_handle = radeon_user_framebuffer_create_handle,
860 struct drm_framebuffer *
861 radeon_framebuffer_create(struct drm_device *dev,
862 struct drm_mode_fb_cmd *mode_cmd,
863 struct drm_gem_object *obj)
865 struct radeon_framebuffer *radeon_fb;
867 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
868 if (radeon_fb == NULL) {
871 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
872 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
873 radeon_fb->obj = obj;
874 return &radeon_fb->base;
877 static struct drm_framebuffer *
878 radeon_user_framebuffer_create(struct drm_device *dev,
879 struct drm_file *file_priv,
880 struct drm_mode_fb_cmd *mode_cmd)
882 struct drm_gem_object *obj;
884 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
886 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
887 "can't create framebuffer\n", mode_cmd->handle);
890 return radeon_framebuffer_create(dev, mode_cmd, obj);
893 static const struct drm_mode_config_funcs radeon_mode_funcs = {
894 .fb_create = radeon_user_framebuffer_create,
895 .fb_changed = radeonfb_probe,
898 struct drm_prop_enum_list {
903 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
908 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
909 { { TV_STD_NTSC, "ntsc" },
910 { TV_STD_PAL, "pal" },
911 { TV_STD_PAL_M, "pal-m" },
912 { TV_STD_PAL_60, "pal-60" },
913 { TV_STD_NTSC_J, "ntsc-j" },
914 { TV_STD_SCART_PAL, "scart-pal" },
915 { TV_STD_PAL_CN, "pal-cn" },
916 { TV_STD_SECAM, "secam" },
919 static int radeon_modeset_create_props(struct radeon_device *rdev)
923 if (rdev->is_atom_bios) {
924 rdev->mode_info.coherent_mode_property =
925 drm_property_create(rdev->ddev,
928 if (!rdev->mode_info.coherent_mode_property)
931 rdev->mode_info.coherent_mode_property->values[0] = 0;
932 rdev->mode_info.coherent_mode_property->values[1] = 1;
935 if (!ASIC_IS_AVIVO(rdev)) {
936 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
937 rdev->mode_info.tmds_pll_property =
938 drm_property_create(rdev->ddev,
941 for (i = 0; i < sz; i++) {
942 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
944 radeon_tmds_pll_enum_list[i].type,
945 radeon_tmds_pll_enum_list[i].name);
949 rdev->mode_info.load_detect_property =
950 drm_property_create(rdev->ddev,
952 "load detection", 2);
953 if (!rdev->mode_info.load_detect_property)
955 rdev->mode_info.load_detect_property->values[0] = 0;
956 rdev->mode_info.load_detect_property->values[1] = 1;
958 drm_mode_create_scaling_mode_property(rdev->ddev);
960 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
961 rdev->mode_info.tv_std_property =
962 drm_property_create(rdev->ddev,
965 for (i = 0; i < sz; i++) {
966 drm_property_add_enum(rdev->mode_info.tv_std_property,
968 radeon_tv_std_enum_list[i].type,
969 radeon_tv_std_enum_list[i].name);
975 int radeon_modeset_init(struct radeon_device *rdev)
980 drm_mode_config_init(rdev->ddev);
981 rdev->mode_info.mode_config_initialized = true;
983 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
985 if (ASIC_IS_AVIVO(rdev)) {
986 rdev->ddev->mode_config.max_width = 8192;
987 rdev->ddev->mode_config.max_height = 8192;
989 rdev->ddev->mode_config.max_width = 4096;
990 rdev->ddev->mode_config.max_height = 4096;
993 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
995 ret = radeon_modeset_create_props(rdev);
1000 /* check combios for a valid hardcoded EDID - Sun servers */
1001 if (!rdev->is_atom_bios) {
1002 /* check for hardcoded EDID in BIOS */
1003 radeon_combios_check_hardcoded_edid(rdev);
1006 /* allocate crtcs */
1007 for (i = 0; i < rdev->num_crtc; i++) {
1008 radeon_crtc_init(rdev->ddev, i);
1011 /* okay we should have all the bios connectors */
1012 ret = radeon_setup_enc_conn(rdev->ddev);
1016 /* initialize hpd */
1017 radeon_hpd_init(rdev);
1018 drm_helper_initial_config(rdev->ddev);
1022 void radeon_modeset_fini(struct radeon_device *rdev)
1024 kfree(rdev->mode_info.bios_hardcoded_edid);
1026 if (rdev->mode_info.mode_config_initialized) {
1027 radeon_hpd_fini(rdev);
1028 drm_mode_config_cleanup(rdev->ddev);
1029 rdev->mode_info.mode_config_initialized = false;
1033 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1034 struct drm_display_mode *mode,
1035 struct drm_display_mode *adjusted_mode)
1037 struct drm_device *dev = crtc->dev;
1038 struct drm_encoder *encoder;
1039 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1040 struct radeon_encoder *radeon_encoder;
1043 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1044 radeon_encoder = to_radeon_encoder(encoder);
1045 if (encoder->crtc != crtc)
1049 if (radeon_encoder->rmx_type == RMX_OFF)
1050 radeon_crtc->rmx_type = RMX_OFF;
1051 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1052 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1053 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1055 radeon_crtc->rmx_type = RMX_OFF;
1056 /* copy native mode */
1057 memcpy(&radeon_crtc->native_mode,
1058 &radeon_encoder->native_mode,
1059 sizeof(struct drm_display_mode));
1062 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1063 /* WARNING: Right now this can't happen but
1064 * in the future we need to check that scaling
1065 * are consistent accross different encoder
1066 * (ie all encoder can work with the same
1069 DRM_ERROR("Scaling not consistent accross encoder.\n");
1074 if (radeon_crtc->rmx_type != RMX_OFF) {
1076 a.full = rfixed_const(crtc->mode.vdisplay);
1077 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
1078 radeon_crtc->vsc.full = rfixed_div(a, b);
1079 a.full = rfixed_const(crtc->mode.hdisplay);
1080 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
1081 radeon_crtc->hsc.full = rfixed_div(a, b);
1083 radeon_crtc->vsc.full = rfixed_const(1);
1084 radeon_crtc->hsc.full = rfixed_const(1);