drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35
  36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  37 {
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39         struct drm_device *dev = crtc->dev;
  40         struct radeon_device *rdev = dev->dev_private;
  41         int i;
  42
  43         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  44         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  45
  46         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  47         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  51         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  53
  54         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  55         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  56         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  57
  58         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  59         for (i = 0; i < 256; i++) {
  60                 WREG32(AVIVO_DC_LUT_30_COLOR,
  61                              (radeon_crtc->lut_r[i] << 20) |
  62                              (radeon_crtc->lut_g[i] << 10) |
  63                              (radeon_crtc->lut_b[i] << 0));
  64         }
  65
  66         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  67 }
  68
  69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  70 {
  71         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  72         struct drm_device *dev = crtc->dev;
  73         struct radeon_device *rdev = dev->dev_private;
  74         int i;
  75
  76         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  77         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  78
  79         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  80         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  82
  83         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  84         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  86
  87         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  88         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  91         for (i = 0; i < 256; i++) {
  92                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  93                        (radeon_crtc->lut_r[i] << 20) |
  94                        (radeon_crtc->lut_g[i] << 10) |
  95                        (radeon_crtc->lut_b[i] << 0));
  96         }
  97 }
  98
  99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 100 {
 101         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 102         struct drm_device *dev = crtc->dev;
 103         struct radeon_device *rdev = dev->dev_private;
 104         int i;
 105
 106         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 107
 108         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 109                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 110                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 111         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 112                NI_GRPH_PRESCALE_BYPASS);
 113         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 114                NI_OVL_PRESCALE_BYPASS);
 115         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 116                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 117                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 118
 119         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 120
 121         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 122         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 124
 125         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 126         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 128
 129         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 130         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 133         for (i = 0; i < 256; i++) {
 134                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 135                        (radeon_crtc->lut_r[i] << 20) |
 136                        (radeon_crtc->lut_g[i] << 10) |
 137                        (radeon_crtc->lut_b[i] << 0));
 138         }
 139
 140         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 142                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 143                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 144                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 145         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 147                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 148         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 150                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 151         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 153                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 154         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 155         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 156
 157 }
 158
 159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 160 {
 161         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 162         struct drm_device *dev = crtc->dev;
 163         struct radeon_device *rdev = dev->dev_private;
 164         int i;
 165         uint32_t dac2_cntl;
 166
 167         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 168         if (radeon_crtc->crtc_id == 0)
 169                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 170         else
 171                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 172         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 173
 174         WREG8(RADEON_PALETTE_INDEX, 0);
 175         for (i = 0; i < 256; i++) {
 176                 WREG32(RADEON_PALETTE_30_DATA,
 177                              (radeon_crtc->lut_r[i] << 20) |
 178                              (radeon_crtc->lut_g[i] << 10) |
 179                              (radeon_crtc->lut_b[i] << 0));
 180         }
 181 }
 182
 183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 184 {
 185         struct drm_device *dev = crtc->dev;
 186         struct radeon_device *rdev = dev->dev_private;
 187
 188         if (!crtc->enabled)
 189                 return;
 190
 191         if (ASIC_IS_DCE5(rdev))
 192                 dce5_crtc_load_lut(crtc);
 193         else if (ASIC_IS_DCE4(rdev))
 194                 dce4_crtc_load_lut(crtc);
 195         else if (ASIC_IS_AVIVO(rdev))
 196                 avivo_crtc_load_lut(crtc);
 197         else
 198                 legacy_crtc_load_lut(crtc);
 199 }
 200
 201 /** Sets the color ramps on behalf of fbcon */
 202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 203                               u16 blue, int regno)
 204 {
 205         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 206
 207         radeon_crtc->lut_r[regno] = red >> 6;
 208         radeon_crtc->lut_g[regno] = green >> 6;
 209         radeon_crtc->lut_b[regno] = blue >> 6;
 210 }
 211
 212 /** Gets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 214                               u16 *blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         *red = radeon_crtc->lut_r[regno] << 6;
 219         *green = radeon_crtc->lut_g[regno] << 6;
 220         *blue = radeon_crtc->lut_b[regno] << 6;
 221 }
 222
 223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 224                                   u16 *blue, uint32_t start, uint32_t size)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         int end = (start + size > 256) ? 256 : start + size, i;
 228
 229         /* userspace palettes are always correct as is */
 230         for (i = start; i < end; i++) {
 231                 radeon_crtc->lut_r[i] = red[i] >> 6;
 232                 radeon_crtc->lut_g[i] = green[i] >> 6;
 233                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 234         }
 235         radeon_crtc_load_lut(crtc);
 236 }
 237
 238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 239 {
 240         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 241
 242         drm_crtc_cleanup(crtc);
 243         kfree(radeon_crtc);
 244 }
 245
 246 /*
 247  * Handle unpin events outside the interrupt handler proper.
 248  */
 249 static void radeon_unpin_work_func(struct work_struct *__work)
 250 {
 251         struct radeon_unpin_work *work =
 252                 container_of(__work, struct radeon_unpin_work, work);
 253         int r;
 254
 255         /* unpin of the old buffer */
 256         r = radeon_bo_reserve(work->old_rbo, false);
 257         if (likely(r == 0)) {
 258                 r = radeon_bo_unpin(work->old_rbo);
 259                 if (unlikely(r != 0)) {
 260                         DRM_ERROR("failed to unpin buffer after flip\n");
 261                 }
 262                 radeon_bo_unreserve(work->old_rbo);
 263         } else
 264                 DRM_ERROR("failed to reserve buffer after flip\n");
 265
 266         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 267         kfree(work);
 268 }
 269
 270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 271 {
 272         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 273         struct radeon_unpin_work *work;
 274         unsigned long flags;
 275         u32 update_pending;
 276         int vpos, hpos;
 277
 278         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 279         work = radeon_crtc->unpin_work;
 280         if (work == NULL ||
 281             (work->fence && !radeon_fence_signaled(work->fence))) {
 282                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 283                 return;
 284         }
 285         /* New pageflip, or just completion of a previous one? */
 286         if (!radeon_crtc->deferred_flip_completion) {
 287                 /* do the flip (mmio) */
 288                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 289         } else {
 290                 /* This is just a completion of a flip queued in crtc
 291                  * at last invocation. Make sure we go directly to
 292                  * completion routine.
 293                  */
 294                 update_pending = 0;
 295                 radeon_crtc->deferred_flip_completion = 0;
 296         }
 297
 298         /* Has the pageflip already completed in crtc, or is it certain
 299          * to complete in this vblank?
 300          */
 301         if (update_pending &&
 302             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 303                                                                &vpos, &hpos)) &&
 304             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 305              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 306                 /* crtc didn't flip in this target vblank interval,
 307                  * but flip is pending in crtc. Based on the current
 308                  * scanout position we know that the current frame is
 309                  * (nearly) complete and the flip will (likely)
 310                  * complete before the start of the next frame.
 311                  */
 312                 update_pending = 0;
 313         }
 314         if (update_pending) {
 315                 /* crtc didn't flip in this target vblank interval,
 316                  * but flip is pending in crtc. It will complete it
 317                  * in next vblank interval, so complete the flip at
 318                  * next vblank irq.
 319                  */
 320                 radeon_crtc->deferred_flip_completion = 1;
 321                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 322                 return;
 323         }
 324
 325         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 326         radeon_crtc->unpin_work = NULL;
 327
 328         /* wakeup userspace */
 329         if (work->event)
 330                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 331
 332         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 333
 334         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 335         radeon_fence_unref(&work->fence);
 336         radeon_post_page_flip(work->rdev, work->crtc_id);
 337         schedule_work(&work->work);
 338 }
 339
 340 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 341                                  struct drm_framebuffer *fb,
 342                                  struct drm_pending_vblank_event *event)
 343 {
 344         struct drm_device *dev = crtc->dev;
 345         struct radeon_device *rdev = dev->dev_private;
 346         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 347         struct radeon_framebuffer *old_radeon_fb;
 348         struct radeon_framebuffer *new_radeon_fb;
 349         struct drm_gem_object *obj;
 350         struct radeon_bo *rbo;
 351         struct radeon_unpin_work *work;
 352         unsigned long flags;
 353         u32 tiling_flags, pitch_pixels;
 354         u64 base;
 355         int r;
 356
 357         work = kzalloc(sizeof *work, GFP_KERNEL);
 358         if (work == NULL)
 359                 return -ENOMEM;
 360
 361         work->event = event;
 362         work->rdev = rdev;
 363         work->crtc_id = radeon_crtc->crtc_id;
 364         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 365         new_radeon_fb = to_radeon_framebuffer(fb);
 366         /* schedule unpin of the old buffer */
 367         obj = old_radeon_fb->obj;
 368         /* take a reference to the old object */
 369         drm_gem_object_reference(obj);
 370         rbo = gem_to_radeon_bo(obj);
 371         work->old_rbo = rbo;
 372         obj = new_radeon_fb->obj;
 373         rbo = gem_to_radeon_bo(obj);
 374
 375         spin_lock(&rbo->tbo.bdev->fence_lock);
 376         if (rbo->tbo.sync_obj)
 377                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 378         spin_unlock(&rbo->tbo.bdev->fence_lock);
 379
 380         INIT_WORK(&work->work, radeon_unpin_work_func);
 381
 382         /* We borrow the event spin lock for protecting unpin_work */
 383         spin_lock_irqsave(&dev->event_lock, flags);
 384         if (radeon_crtc->unpin_work) {
 385                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 386                 r = -EBUSY;
 387                 goto unlock_free;
 388         }
 389         radeon_crtc->unpin_work = work;
 390         radeon_crtc->deferred_flip_completion = 0;
 391         spin_unlock_irqrestore(&dev->event_lock, flags);
 392
 393         /* pin the new buffer */
 394         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 395                          work->old_rbo, rbo);
 396
 397         r = radeon_bo_reserve(rbo, false);
 398         if (unlikely(r != 0)) {
 399                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 400                 goto pflip_cleanup;
 401         }
 402         /* Only 27 bit offset for legacy CRTC */
 403         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 404                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 405         if (unlikely(r != 0)) {
 406                 radeon_bo_unreserve(rbo);
 407                 r = -EINVAL;
 408                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 409                 goto pflip_cleanup;
 410         }
 411         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 412         radeon_bo_unreserve(rbo);
 413
 414         if (!ASIC_IS_AVIVO(rdev)) {
 415                 /* crtc offset is from display base addr not FB location */
 416                 base -= radeon_crtc->legacy_display_base_addr;
 417                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 418
 419                 if (tiling_flags & RADEON_TILING_MACRO) {
 420                         if (ASIC_IS_R300(rdev)) {
 421                                 base &= ~0x7ff;
 422                         } else {
 423                                 int byteshift = fb->bits_per_pixel >> 4;
 424                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 425                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 426                         }
 427                 } else {
 428                         int offset = crtc->y * pitch_pixels + crtc->x;
 429                         switch (fb->bits_per_pixel) {
 430                         case 8:
 431                         default:
 432                                 offset *= 1;
 433                                 break;
 434                         case 15:
 435                         case 16:
 436                                 offset *= 2;
 437                                 break;
 438                         case 24:
 439                                 offset *= 3;
 440                                 break;
 441                         case 32:
 442                                 offset *= 4;
 443                                 break;
 444                         }
 445                         base += offset;
 446                 }
 447                 base &= ~7;
 448         }
 449
 450         spin_lock_irqsave(&dev->event_lock, flags);
 451         work->new_crtc_base = base;
 452         spin_unlock_irqrestore(&dev->event_lock, flags);
 453
 454         /* update crtc fb */
 455         crtc->fb = fb;
 456
 457         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 458         if (r) {
 459                 DRM_ERROR("failed to get vblank before flip\n");
 460                 goto pflip_cleanup1;
 461         }
 462
 463         /* set the proper interrupt */
 464         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 465
 466         return 0;
 467
 468 pflip_cleanup1:
 469         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 470                 DRM_ERROR("failed to reserve new rbo in error path\n");
 471                 goto pflip_cleanup;
 472         }
 473         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 474                 DRM_ERROR("failed to unpin new rbo in error path\n");
 475         }
 476         radeon_bo_unreserve(rbo);
 477
 478 pflip_cleanup:
 479         spin_lock_irqsave(&dev->event_lock, flags);
 480         radeon_crtc->unpin_work = NULL;
 481 unlock_free:
 482         spin_unlock_irqrestore(&dev->event_lock, flags);
 483         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 484         radeon_fence_unref(&work->fence);
 485         kfree(work);
 486
 487         return r;
 488 }
 489
 490 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 491         .cursor_set = radeon_crtc_cursor_set,
 492         .cursor_move = radeon_crtc_cursor_move,
 493         .gamma_set = radeon_crtc_gamma_set,
 494         .set_config = drm_crtc_helper_set_config,
 495         .destroy = radeon_crtc_destroy,
 496         .page_flip = radeon_crtc_page_flip,
 497 };
 498
 499 static void radeon_crtc_init(struct drm_device *dev, int index)
 500 {
 501         struct radeon_device *rdev = dev->dev_private;
 502         struct radeon_crtc *radeon_crtc;
 503         int i;
 504
 505         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 506         if (radeon_crtc == NULL)
 507                 return;
 508
 509         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 510
 511         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 512         radeon_crtc->crtc_id = index;
 513         rdev->mode_info.crtcs[index] = radeon_crtc;
 514
 515 #if 0
 516         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 517         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 518         radeon_crtc->mode_set.num_connectors = 0;
 519 #endif
 520
 521         for (i = 0; i < 256; i++) {
 522                 radeon_crtc->lut_r[i] = i << 2;
 523                 radeon_crtc->lut_g[i] = i << 2;
 524                 radeon_crtc->lut_b[i] = i << 2;
 525         }
 526
 527         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 528                 radeon_atombios_init_crtc(dev, radeon_crtc);
 529         else
 530                 radeon_legacy_init_crtc(dev, radeon_crtc);
 531 }
 532
 533 static const char *encoder_names[37] = {
 534         "NONE",
 535         "INTERNAL_LVDS",
 536         "INTERNAL_TMDS1",
 537         "INTERNAL_TMDS2",
 538         "INTERNAL_DAC1",
 539         "INTERNAL_DAC2",
 540         "INTERNAL_SDVOA",
 541         "INTERNAL_SDVOB",
 542         "SI170B",
 543         "CH7303",
 544         "CH7301",
 545         "INTERNAL_DVO1",
 546         "EXTERNAL_SDVOA",
 547         "EXTERNAL_SDVOB",
 548         "TITFP513",
 549         "INTERNAL_LVTM1",
 550         "VT1623",
 551         "HDMI_SI1930",
 552         "HDMI_INTERNAL",
 553         "INTERNAL_KLDSCP_TMDS1",
 554         "INTERNAL_KLDSCP_DVO1",
 555         "INTERNAL_KLDSCP_DAC1",
 556         "INTERNAL_KLDSCP_DAC2",
 557         "SI178",
 558         "MVPU_FPGA",
 559         "INTERNAL_DDI",
 560         "VT1625",
 561         "HDMI_SI1932",
 562         "DP_AN9801",
 563         "DP_DP501",
 564         "INTERNAL_UNIPHY",
 565         "INTERNAL_KLDSCP_LVTMA",
 566         "INTERNAL_UNIPHY1",
 567         "INTERNAL_UNIPHY2",
 568         "NUTMEG",
 569         "TRAVIS",
 570         "INTERNAL_VCE"
 571 };
 572
 573 static const char *hpd_names[6] = {
 574         "HPD1",
 575         "HPD2",
 576         "HPD3",
 577         "HPD4",
 578         "HPD5",
 579         "HPD6",
 580 };
 581
 582 static void radeon_print_display_setup(struct drm_device *dev)
 583 {
 584         struct drm_connector *connector;
 585         struct radeon_connector *radeon_connector;
 586         struct drm_encoder *encoder;
 587         struct radeon_encoder *radeon_encoder;
 588         uint32_t devices;
 589         int i = 0;
 590
 591         DRM_INFO("Radeon Display Connectors\n");
 592         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 593                 radeon_connector = to_radeon_connector(connector);
 594                 DRM_INFO("Connector %d:\n", i);
 595                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 596                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 597                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 598                 if (radeon_connector->ddc_bus) {
 599                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 600                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 601                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 602                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 603                                  radeon_connector->ddc_bus->rec.a_data_reg,
 604                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 605                                  radeon_connector->ddc_bus->rec.en_data_reg,
 606                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 607                                  radeon_connector->ddc_bus->rec.y_data_reg);
 608                         if (radeon_connector->router.ddc_valid)
 609                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 610                                          radeon_connector->router.ddc_mux_control_pin,
 611                                          radeon_connector->router.ddc_mux_state);
 612                         if (radeon_connector->router.cd_valid)
 613                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 614                                          radeon_connector->router.cd_mux_control_pin,
 615                                          radeon_connector->router.cd_mux_state);
 616                 } else {
 617                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 618                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 619                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 620                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 621                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 622                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 623                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 624                 }
 625                 DRM_INFO("  Encoders:\n");
 626                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 627                         radeon_encoder = to_radeon_encoder(encoder);
 628                         devices = radeon_encoder->devices & radeon_connector->devices;
 629                         if (devices) {
 630                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 631                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 632                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 633                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 634                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 635                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 636                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 637                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 638                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 639                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 640                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 641                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 642                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 643                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 644                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 645                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 646                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 647                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 648                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 649                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 650                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 651                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 652                         }
 653                 }
 654                 i++;
 655         }
 656 }
 657
 658 static bool radeon_setup_enc_conn(struct drm_device *dev)
 659 {
 660         struct radeon_device *rdev = dev->dev_private;
 661         bool ret = false;
 662
 663         if (rdev->bios) {
 664                 if (rdev->is_atom_bios) {
 665                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 666                         if (ret == false)
 667                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 668                 } else {
 669                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 670                         if (ret == false)
 671                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 672                 }
 673         } else {
 674                 if (!ASIC_IS_AVIVO(rdev))
 675                         ret = radeon_get_legacy_connector_info_from_table(dev);
 676         }
 677         if (ret) {
 678                 radeon_setup_encoder_clones(dev);
 679                 radeon_print_display_setup(dev);
 680         }
 681
 682         return ret;
 683 }
 684
 685 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 686 {
 687         struct drm_device *dev = radeon_connector->base.dev;
 688         struct radeon_device *rdev = dev->dev_private;
 689         int ret = 0;
 690
 691         /* on hw with routers, select right port */
 692         if (radeon_connector->router.ddc_valid)
 693                 radeon_router_select_ddc_port(radeon_connector);
 694
 695         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 696             ENCODER_OBJECT_ID_NONE) {
 697                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 698
 699                 if (dig->dp_i2c_bus)
 700                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 701                                                               &dig->dp_i2c_bus->adapter);
 702         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 703                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 704                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 705
 706                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 707                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 708                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 709                                                               &dig->dp_i2c_bus->adapter);
 710                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 711                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 712                                                               &radeon_connector->ddc_bus->adapter);
 713         } else {
 714                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 715                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 716                                                               &radeon_connector->ddc_bus->adapter);
 717         }
 718
 719         if (!radeon_connector->edid) {
 720                 if (rdev->is_atom_bios) {
 721                         /* some laptops provide a hardcoded edid in rom for LCDs */
 722                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 723                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 724                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 725                 } else
 726                         /* some servers provide a hardcoded edid in rom for KVMs */
 727                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 728         }
 729         if (radeon_connector->edid) {
 730                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 731                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 732                 return ret;
 733         }
 734         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 735         return 0;
 736 }
 737
 738 /* avivo */
 739 static void avivo_get_fb_div(struct radeon_pll *pll,
 740                              u32 target_clock,
 741                              u32 post_div,
 742                              u32 ref_div,
 743                              u32 *fb_div,
 744                              u32 *frac_fb_div)
 745 {
 746         u32 tmp = post_div * ref_div;
 747
 748         tmp *= target_clock;
 749         *fb_div = tmp / pll->reference_freq;
 750         *frac_fb_div = tmp % pll->reference_freq;
 751
 752         if (*fb_div > pll->max_feedback_div)
 753                 *fb_div = pll->max_feedback_div;
 754         else if (*fb_div < pll->min_feedback_div)
 755                 *fb_div = pll->min_feedback_div;
 756 }
 757
 758 static u32 avivo_get_post_div(struct radeon_pll *pll,
 759                               u32 target_clock)
 760 {
 761         u32 vco, post_div, tmp;
 762
 763         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 764                 return pll->post_div;
 765
 766         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 767                 if (pll->flags & RADEON_PLL_IS_LCD)
 768                         vco = pll->lcd_pll_out_min;
 769                 else
 770                         vco = pll->pll_out_min;
 771         } else {
 772                 if (pll->flags & RADEON_PLL_IS_LCD)
 773                         vco = pll->lcd_pll_out_max;
 774                 else
 775                         vco = pll->pll_out_max;
 776         }
 777
 778         post_div = vco / target_clock;
 779         tmp = vco % target_clock;
 780
 781         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 782                 if (tmp)
 783                         post_div++;
 784         } else {
 785                 if (!tmp)
 786                         post_div--;
 787         }
 788
 789         if (post_div > pll->max_post_div)
 790                 post_div = pll->max_post_div;
 791         else if (post_div < pll->min_post_div)
 792                 post_div = pll->min_post_div;
 793
 794         return post_div;
 795 }
 796
 797 #define MAX_TOLERANCE 10
 798
 799 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 800                               u32 freq,
 801                               u32 *dot_clock_p,
 802                               u32 *fb_div_p,
 803                               u32 *frac_fb_div_p,
 804                               u32 *ref_div_p,
 805                               u32 *post_div_p)
 806 {
 807         u32 target_clock = freq / 10;
 808         u32 post_div = avivo_get_post_div(pll, target_clock);
 809         u32 ref_div = pll->min_ref_div;
 810         u32 fb_div = 0, frac_fb_div = 0, tmp;
 811
 812         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 813                 ref_div = pll->reference_div;
 814
 815         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 816                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 817                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 818                 if (frac_fb_div >= 5) {
 819                         frac_fb_div -= 5;
 820                         frac_fb_div = frac_fb_div / 10;
 821                         frac_fb_div++;
 822                 }
 823                 if (frac_fb_div >= 10) {
 824                         fb_div++;
 825                         frac_fb_div = 0;
 826                 }
 827         } else {
 828                 while (ref_div <= pll->max_ref_div) {
 829                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 830                                          &fb_div, &frac_fb_div);
 831                         if (frac_fb_div >= (pll->reference_freq / 2))
 832                                 fb_div++;
 833                         frac_fb_div = 0;
 834                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 835                         tmp = (tmp * 10000) / target_clock;
 836
 837                         if (tmp > (10000 + MAX_TOLERANCE))
 838                                 ref_div++;
 839                         else if (tmp >= (10000 - MAX_TOLERANCE))
 840                                 break;
 841                         else
 842                                 ref_div++;
 843                 }
 844         }
 845
 846         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 847                 (ref_div * post_div * 10);
 848         *fb_div_p = fb_div;
 849         *frac_fb_div_p = frac_fb_div;
 850         *ref_div_p = ref_div;
 851         *post_div_p = post_div;
 852         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 853                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 854 }
 855
 856 /* pre-avivo */
 857 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 858 {
 859         uint64_t mod;
 860
 861         n += d / 2;
 862
 863         mod = do_div(n, d);
 864         return n;
 865 }
 866
 867 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 868                                uint64_t freq,
 869                                uint32_t *dot_clock_p,
 870                                uint32_t *fb_div_p,
 871                                uint32_t *frac_fb_div_p,
 872                                uint32_t *ref_div_p,
 873                                uint32_t *post_div_p)
 874 {
 875         uint32_t min_ref_div = pll->min_ref_div;
 876         uint32_t max_ref_div = pll->max_ref_div;
 877         uint32_t min_post_div = pll->min_post_div;
 878         uint32_t max_post_div = pll->max_post_div;
 879         uint32_t min_fractional_feed_div = 0;
 880         uint32_t max_fractional_feed_div = 0;
 881         uint32_t best_vco = pll->best_vco;
 882         uint32_t best_post_div = 1;
 883         uint32_t best_ref_div = 1;
 884         uint32_t best_feedback_div = 1;
 885         uint32_t best_frac_feedback_div = 0;
 886         uint32_t best_freq = -1;
 887         uint32_t best_error = 0xffffffff;
 888         uint32_t best_vco_diff = 1;
 889         uint32_t post_div;
 890         u32 pll_out_min, pll_out_max;
 891
 892         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 893         freq = freq * 1000;
 894
 895         if (pll->flags & RADEON_PLL_IS_LCD) {
 896                 pll_out_min = pll->lcd_pll_out_min;
 897                 pll_out_max = pll->lcd_pll_out_max;
 898         } else {
 899                 pll_out_min = pll->pll_out_min;
 900                 pll_out_max = pll->pll_out_max;
 901         }
 902
 903         if (pll_out_min > 64800)
 904                 pll_out_min = 64800;
 905
 906         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 907                 min_ref_div = max_ref_div = pll->reference_div;
 908         else {
 909                 while (min_ref_div < max_ref_div-1) {
 910                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 911                         uint32_t pll_in = pll->reference_freq / mid;
 912                         if (pll_in < pll->pll_in_min)
 913                                 max_ref_div = mid;
 914                         else if (pll_in > pll->pll_in_max)
 915                                 min_ref_div = mid;
 916                         else
 917                                 break;
 918                 }
 919         }
 920
 921         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 922                 min_post_div = max_post_div = pll->post_div;
 923
 924         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 925                 min_fractional_feed_div = pll->min_frac_feedback_div;
 926                 max_fractional_feed_div = pll->max_frac_feedback_div;
 927         }
 928
 929         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 930                 uint32_t ref_div;
 931
 932                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 933                         continue;
 934
 935                 /* legacy radeons only have a few post_divs */
 936                 if (pll->flags & RADEON_PLL_LEGACY) {
 937                         if ((post_div == 5) ||
 938                             (post_div == 7) ||
 939                             (post_div == 9) ||
 940                             (post_div == 10) ||
 941                             (post_div == 11) ||
 942                             (post_div == 13) ||
 943                             (post_div == 14) ||
 944                             (post_div == 15))
 945                                 continue;
 946                 }
 947
 948                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 949                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 950                         uint32_t pll_in = pll->reference_freq / ref_div;
 951                         uint32_t min_feed_div = pll->min_feedback_div;
 952                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 953
 954                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 955                                 continue;
 956
 957                         while (min_feed_div < max_feed_div) {
 958                                 uint32_t vco;
 959                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 960                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 961                                 uint32_t frac_feedback_div;
 962                                 uint64_t tmp;
 963
 964                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 965
 966                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 967                                 vco = radeon_div(tmp, ref_div);
 968
 969                                 if (vco < pll_out_min) {
 970                                         min_feed_div = feedback_div + 1;
 971                                         continue;
 972                                 } else if (vco > pll_out_max) {
 973                                         max_feed_div = feedback_div;
 974                                         continue;
 975                                 }
 976
 977                                 while (min_frac_feed_div < max_frac_feed_div) {
 978                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 979                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 980                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 981                                         current_freq = radeon_div(tmp, ref_div * post_div);
 982
 983                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 984                                                 if (freq < current_freq)
 985                                                         error = 0xffffffff;
 986                                                 else
 987                                                         error = freq - current_freq;
 988                                         } else
 989                                                 error = abs(current_freq - freq);
 990                                         vco_diff = abs(vco - best_vco);
 991
 992                                         if ((best_vco == 0 && error < best_error) ||
 993                                             (best_vco != 0 &&
 994                                              ((best_error > 100 && error < best_error - 100) ||
 995                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 996                                                 best_post_div = post_div;
 997                                                 best_ref_div = ref_div;
 998                                                 best_feedback_div = feedback_div;
 999                                                 best_frac_feedback_div = frac_feedback_div;
1000                                                 best_freq = current_freq;
1001                                                 best_error = error;
1002                                                 best_vco_diff = vco_diff;
1003                                         } else if (current_freq == freq) {
1004                                                 if (best_freq == -1) {
1005                                                         best_post_div = post_div;
1006                                                         best_ref_div = ref_div;
1007                                                         best_feedback_div = feedback_div;
1008                                                         best_frac_feedback_div = frac_feedback_div;
1009                                                         best_freq = current_freq;
1010                                                         best_error = error;
1011                                                         best_vco_diff = vco_diff;
1012                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1013                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1014                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1015                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1016                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1017                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1018                                                         best_post_div = post_div;
1019                                                         best_ref_div = ref_div;
1020                                                         best_feedback_div = feedback_div;
1021                                                         best_frac_feedback_div = frac_feedback_div;
1022                                                         best_freq = current_freq;
1023                                                         best_error = error;
1024                                                         best_vco_diff = vco_diff;
1025                                                 }
1026                                         }
1027                                         if (current_freq < freq)
1028                                                 min_frac_feed_div = frac_feedback_div + 1;
1029                                         else
1030                                                 max_frac_feed_div = frac_feedback_div;
1031                                 }
1032                                 if (current_freq < freq)
1033                                         min_feed_div = feedback_div + 1;
1034                                 else
1035                                         max_feed_div = feedback_div;
1036                         }
1037                 }
1038         }
1039
1040         *dot_clock_p = best_freq / 10000;
1041         *fb_div_p = best_feedback_div;
1042         *frac_fb_div_p = best_frac_feedback_div;
1043         *ref_div_p = best_ref_div;
1044         *post_div_p = best_post_div;
1045         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1046                       (long long)freq,
1047                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1048                       best_ref_div, best_post_div);
1049
1050 }
1051
1052 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1053 {
1054         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1055
1056         if (radeon_fb->obj) {
1057                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1058         }
1059         drm_framebuffer_cleanup(fb);
1060         kfree(radeon_fb);
1061 }
1062
1063 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1064                                                   struct drm_file *file_priv,
1065                                                   unsigned int *handle)
1066 {
1067         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1068
1069         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1070 }
1071
1072 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1073         .destroy = radeon_user_framebuffer_destroy,
1074         .create_handle = radeon_user_framebuffer_create_handle,
1075 };
1076
1077 int
1078 radeon_framebuffer_init(struct drm_device *dev,
1079                         struct radeon_framebuffer *rfb,
1080                         struct drm_mode_fb_cmd2 *mode_cmd,
1081                         struct drm_gem_object *obj)
1082 {
1083         int ret;
1084         rfb->obj = obj;
1085         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1086         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1087         if (ret) {
1088                 rfb->obj = NULL;
1089                 return ret;
1090         }
1091         return 0;
1092 }
1093
1094 static struct drm_framebuffer *
1095 radeon_user_framebuffer_create(struct drm_device *dev,
1096                                struct drm_file *file_priv,
1097                                struct drm_mode_fb_cmd2 *mode_cmd)
1098 {
1099         struct drm_gem_object *obj;
1100         struct radeon_framebuffer *radeon_fb;
1101         int ret;
1102
1103         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1104         if (obj ==  NULL) {
1105                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1106                         "can't create framebuffer\n", mode_cmd->handles[0]);
1107                 return ERR_PTR(-ENOENT);
1108         }
1109
1110         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1111         if (radeon_fb == NULL) {
1112                 drm_gem_object_unreference_unlocked(obj);
1113                 return ERR_PTR(-ENOMEM);
1114         }
1115
1116         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1117         if (ret) {
1118                 kfree(radeon_fb);
1119                 drm_gem_object_unreference_unlocked(obj);
1120                 return ERR_PTR(ret);
1121         }
1122
1123         return &radeon_fb->base;
1124 }
1125
1126 static void radeon_output_poll_changed(struct drm_device *dev)
1127 {
1128         struct radeon_device *rdev = dev->dev_private;
1129         radeon_fb_output_poll_changed(rdev);
1130 }
1131
1132 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1133         .fb_create = radeon_user_framebuffer_create,
1134         .output_poll_changed = radeon_output_poll_changed
1135 };
1136
1137 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1138 {       { 0, "driver" },
1139         { 1, "bios" },
1140 };
1141
1142 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1143 {       { TV_STD_NTSC, "ntsc" },
1144         { TV_STD_PAL, "pal" },
1145         { TV_STD_PAL_M, "pal-m" },
1146         { TV_STD_PAL_60, "pal-60" },
1147         { TV_STD_NTSC_J, "ntsc-j" },
1148         { TV_STD_SCART_PAL, "scart-pal" },
1149         { TV_STD_PAL_CN, "pal-cn" },
1150         { TV_STD_SECAM, "secam" },
1151 };
1152
1153 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1154 {       { UNDERSCAN_OFF, "off" },
1155         { UNDERSCAN_ON, "on" },
1156         { UNDERSCAN_AUTO, "auto" },
1157 };
1158
1159 static int radeon_modeset_create_props(struct radeon_device *rdev)
1160 {
1161         int sz;
1162
1163         if (rdev->is_atom_bios) {
1164                 rdev->mode_info.coherent_mode_property =
1165                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1166                 if (!rdev->mode_info.coherent_mode_property)
1167                         return -ENOMEM;
1168         }
1169
1170         if (!ASIC_IS_AVIVO(rdev)) {
1171                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1172                 rdev->mode_info.tmds_pll_property =
1173                         drm_property_create_enum(rdev->ddev, 0,
1174                                             "tmds_pll",
1175                                             radeon_tmds_pll_enum_list, sz);
1176         }
1177
1178         rdev->mode_info.load_detect_property =
1179                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1180         if (!rdev->mode_info.load_detect_property)
1181                 return -ENOMEM;
1182
1183         drm_mode_create_scaling_mode_property(rdev->ddev);
1184
1185         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1186         rdev->mode_info.tv_std_property =
1187                 drm_property_create_enum(rdev->ddev, 0,
1188                                     "tv standard",
1189                                     radeon_tv_std_enum_list, sz);
1190
1191         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1192         rdev->mode_info.underscan_property =
1193                 drm_property_create_enum(rdev->ddev, 0,
1194                                     "underscan",
1195                                     radeon_underscan_enum_list, sz);
1196
1197         rdev->mode_info.underscan_hborder_property =
1198                 drm_property_create_range(rdev->ddev, 0,
1199                                         "underscan hborder", 0, 128);
1200         if (!rdev->mode_info.underscan_hborder_property)
1201                 return -ENOMEM;
1202
1203         rdev->mode_info.underscan_vborder_property =
1204                 drm_property_create_range(rdev->ddev, 0,
1205                                         "underscan vborder", 0, 128);
1206         if (!rdev->mode_info.underscan_vborder_property)
1207                 return -ENOMEM;
1208
1209         return 0;
1210 }
1211
1212 void radeon_update_display_priority(struct radeon_device *rdev)
1213 {
1214         /* adjustment options for the display watermarks */
1215         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1216                 /* set display priority to high for r3xx, rv515 chips
1217                  * this avoids flickering due to underflow to the
1218                  * display controllers during heavy acceleration.
1219                  * Don't force high on rs4xx igp chips as it seems to
1220                  * affect the sound card.  See kernel bug 15982.
1221                  */
1222                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1223                     !(rdev->flags & RADEON_IS_IGP))
1224                         rdev->disp_priority = 2;
1225                 else
1226                         rdev->disp_priority = 0;
1227         } else
1228                 rdev->disp_priority = radeon_disp_priority;
1229
1230 }
1231
1232 /*
1233  * Allocate hdmi structs and determine register offsets
1234  */
1235 static void radeon_afmt_init(struct radeon_device *rdev)
1236 {
1237         int i;
1238
1239         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1240                 rdev->mode_info.afmt[i] = NULL;
1241
1242         if (ASIC_IS_DCE6(rdev)) {
1243                 /* todo */
1244         } else if (ASIC_IS_DCE4(rdev)) {
1245                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1246                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1247                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1248                 if (rdev->mode_info.afmt[0]) {
1249                         rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1250                         rdev->mode_info.afmt[0]->id = 0;
1251                 }
1252                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1253                 if (rdev->mode_info.afmt[1]) {
1254                         rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1255                         rdev->mode_info.afmt[1]->id = 1;
1256                 }
1257                 if (!ASIC_IS_DCE41(rdev)) {
1258                         rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1259                         if (rdev->mode_info.afmt[2]) {
1260                                 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1261                                 rdev->mode_info.afmt[2]->id = 2;
1262                         }
1263                         rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1264                         if (rdev->mode_info.afmt[3]) {
1265                                 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1266                                 rdev->mode_info.afmt[3]->id = 3;
1267                         }
1268                         rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1269                         if (rdev->mode_info.afmt[4]) {
1270                                 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1271                                 rdev->mode_info.afmt[4]->id = 4;
1272                         }
1273                         rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1274                         if (rdev->mode_info.afmt[5]) {
1275                                 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1276                                 rdev->mode_info.afmt[5]->id = 5;
1277                         }
1278                 }
1279         } else if (ASIC_IS_DCE3(rdev)) {
1280                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1281                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1282                 if (rdev->mode_info.afmt[0]) {
1283                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1284                         rdev->mode_info.afmt[0]->id = 0;
1285                 }
1286                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1287                 if (rdev->mode_info.afmt[1]) {
1288                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1289                         rdev->mode_info.afmt[1]->id = 1;
1290                 }
1291         } else if (ASIC_IS_DCE2(rdev)) {
1292                 /* DCE2 has at least 1 routable audio block */
1293                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1294                 if (rdev->mode_info.afmt[0]) {
1295                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1296                         rdev->mode_info.afmt[0]->id = 0;
1297                 }
1298                 /* r6xx has 2 routable audio blocks */
1299                 if (rdev->family >= CHIP_R600) {
1300                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1301                         if (rdev->mode_info.afmt[1]) {
1302                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1303                                 rdev->mode_info.afmt[1]->id = 1;
1304                         }
1305                 }
1306         }
1307 }
1308
1309 static void radeon_afmt_fini(struct radeon_device *rdev)
1310 {
1311         int i;
1312
1313         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1314                 kfree(rdev->mode_info.afmt[i]);
1315                 rdev->mode_info.afmt[i] = NULL;
1316         }
1317 }
1318
1319 int radeon_modeset_init(struct radeon_device *rdev)
1320 {
1321         int i;
1322         int ret;
1323
1324         drm_mode_config_init(rdev->ddev);
1325         rdev->mode_info.mode_config_initialized = true;
1326
1327         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1328
1329         if (ASIC_IS_DCE5(rdev)) {
1330                 rdev->ddev->mode_config.max_width = 16384;
1331                 rdev->ddev->mode_config.max_height = 16384;
1332         } else if (ASIC_IS_AVIVO(rdev)) {
1333                 rdev->ddev->mode_config.max_width = 8192;
1334                 rdev->ddev->mode_config.max_height = 8192;
1335         } else {
1336                 rdev->ddev->mode_config.max_width = 4096;
1337                 rdev->ddev->mode_config.max_height = 4096;
1338         }
1339
1340         rdev->ddev->mode_config.preferred_depth = 24;
1341         rdev->ddev->mode_config.prefer_shadow = 1;
1342
1343         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1344
1345         ret = radeon_modeset_create_props(rdev);
1346         if (ret) {
1347                 return ret;
1348         }
1349
1350         /* init i2c buses */
1351         radeon_i2c_init(rdev);
1352
1353         /* check combios for a valid hardcoded EDID - Sun servers */
1354         if (!rdev->is_atom_bios) {
1355                 /* check for hardcoded EDID in BIOS */
1356                 radeon_combios_check_hardcoded_edid(rdev);
1357         }
1358
1359         /* allocate crtcs */
1360         for (i = 0; i < rdev->num_crtc; i++) {
1361                 radeon_crtc_init(rdev->ddev, i);
1362         }
1363
1364         /* okay we should have all the bios connectors */
1365         ret = radeon_setup_enc_conn(rdev->ddev);
1366         if (!ret) {
1367                 return ret;
1368         }
1369
1370         /* init dig PHYs, disp eng pll */
1371         if (rdev->is_atom_bios) {
1372                 radeon_atom_encoder_init(rdev);
1373                 radeon_atom_disp_eng_pll_init(rdev);
1374         }
1375
1376         /* initialize hpd */
1377         radeon_hpd_init(rdev);
1378
1379         /* setup afmt */
1380         radeon_afmt_init(rdev);
1381
1382         /* Initialize power management */
1383         radeon_pm_init(rdev);
1384
1385         radeon_fbdev_init(rdev);
1386         drm_kms_helper_poll_init(rdev->ddev);
1387
1388         return 0;
1389 }
1390
1391 void radeon_modeset_fini(struct radeon_device *rdev)
1392 {
1393         radeon_fbdev_fini(rdev);
1394         kfree(rdev->mode_info.bios_hardcoded_edid);
1395         radeon_pm_fini(rdev);
1396
1397         if (rdev->mode_info.mode_config_initialized) {
1398                 radeon_afmt_fini(rdev);
1399                 drm_kms_helper_poll_fini(rdev->ddev);
1400                 radeon_hpd_fini(rdev);
1401                 drm_mode_config_cleanup(rdev->ddev);
1402                 rdev->mode_info.mode_config_initialized = false;
1403         }
1404         /* free i2c buses */
1405         radeon_i2c_fini(rdev);
1406 }
1407
1408 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1409 {
1410         /* try and guess if this is a tv or a monitor */
1411         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1412             (mode->vdisplay == 576) || /* 576p */
1413             (mode->vdisplay == 720) || /* 720p */
1414             (mode->vdisplay == 1080)) /* 1080p */
1415                 return true;
1416         else
1417                 return false;
1418 }
1419
1420 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1421                                 const struct drm_display_mode *mode,
1422                                 struct drm_display_mode *adjusted_mode)
1423 {
1424         struct drm_device *dev = crtc->dev;
1425         struct radeon_device *rdev = dev->dev_private;
1426         struct drm_encoder *encoder;
1427         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1428         struct radeon_encoder *radeon_encoder;
1429         struct drm_connector *connector;
1430         struct radeon_connector *radeon_connector;
1431         bool first = true;
1432         u32 src_v = 1, dst_v = 1;
1433         u32 src_h = 1, dst_h = 1;
1434
1435         radeon_crtc->h_border = 0;
1436         radeon_crtc->v_border = 0;
1437
1438         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1439                 if (encoder->crtc != crtc)
1440                         continue;
1441                 radeon_encoder = to_radeon_encoder(encoder);
1442                 connector = radeon_get_connector_for_encoder(encoder);
1443                 radeon_connector = to_radeon_connector(connector);
1444
1445                 if (first) {
1446                         /* set scaling */
1447                         if (radeon_encoder->rmx_type == RMX_OFF)
1448                                 radeon_crtc->rmx_type = RMX_OFF;
1449                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1450                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1451                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1452                         else
1453                                 radeon_crtc->rmx_type = RMX_OFF;
1454                         /* copy native mode */
1455                         memcpy(&radeon_crtc->native_mode,
1456                                &radeon_encoder->native_mode,
1457                                 sizeof(struct drm_display_mode));
1458                         src_v = crtc->mode.vdisplay;
1459                         dst_v = radeon_crtc->native_mode.vdisplay;
1460                         src_h = crtc->mode.hdisplay;
1461                         dst_h = radeon_crtc->native_mode.hdisplay;
1462
1463                         /* fix up for overscan on hdmi */
1464                         if (ASIC_IS_AVIVO(rdev) &&
1465                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1466                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1467                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1468                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1469                               is_hdtv_mode(mode)))) {
1470                                 if (radeon_encoder->underscan_hborder != 0)
1471                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1472                                 else
1473                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1474                                 if (radeon_encoder->underscan_vborder != 0)
1475                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1476                                 else
1477                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1478                                 radeon_crtc->rmx_type = RMX_FULL;
1479                                 src_v = crtc->mode.vdisplay;
1480                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1481                                 src_h = crtc->mode.hdisplay;
1482                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1483                         }
1484                         first = false;
1485                 } else {
1486                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1487                                 /* WARNING: Right now this can't happen but
1488                                  * in the future we need to check that scaling
1489                                  * are consistent across different encoder
1490                                  * (ie all encoder can work with the same
1491                                  *  scaling).
1492                                  */
1493                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1494                                 return false;
1495                         }
1496                 }
1497         }
1498         if (radeon_crtc->rmx_type != RMX_OFF) {
1499                 fixed20_12 a, b;
1500                 a.full = dfixed_const(src_v);
1501                 b.full = dfixed_const(dst_v);
1502                 radeon_crtc->vsc.full = dfixed_div(a, b);
1503                 a.full = dfixed_const(src_h);
1504                 b.full = dfixed_const(dst_h);
1505                 radeon_crtc->hsc.full = dfixed_div(a, b);
1506         } else {
1507                 radeon_crtc->vsc.full = dfixed_const(1);
1508                 radeon_crtc->hsc.full = dfixed_const(1);
1509         }
1510         return true;
1511 }
1512
1513 /*
1514  * Retrieve current video scanout position of crtc on a given gpu.
1515  *
1516  * \param dev Device to query.
1517  * \param crtc Crtc to query.
1518  * \param *vpos Location where vertical scanout position should be stored.
1519  * \param *hpos Location where horizontal scanout position should go.
1520  *
1521  * Returns vpos as a positive number while in active scanout area.
1522  * Returns vpos as a negative number inside vblank, counting the number
1523  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1524  * until start of active scanout / end of vblank."
1525  *
1526  * \return Flags, or'ed together as follows:
1527  *
1528  * DRM_SCANOUTPOS_VALID = Query successful.
1529  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1530  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1531  * this flag means that returned position may be offset by a constant but
1532  * unknown small number of scanlines wrt. real scanout position.
1533  *
1534  */
1535 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1536 {
1537         u32 stat_crtc = 0, vbl = 0, position = 0;
1538         int vbl_start, vbl_end, vtotal, ret = 0;
1539         bool in_vbl = true;
1540
1541         struct radeon_device *rdev = dev->dev_private;
1542
1543         if (ASIC_IS_DCE4(rdev)) {
1544                 if (crtc == 0) {
1545                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1546                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1547                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1548                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1549                         ret |= DRM_SCANOUTPOS_VALID;
1550                 }
1551                 if (crtc == 1) {
1552                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1553                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1554                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1555                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1556                         ret |= DRM_SCANOUTPOS_VALID;
1557                 }
1558                 if (crtc == 2) {
1559                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1560                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1561                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1562                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1563                         ret |= DRM_SCANOUTPOS_VALID;
1564                 }
1565                 if (crtc == 3) {
1566                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1567                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1568                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1569                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1570                         ret |= DRM_SCANOUTPOS_VALID;
1571                 }
1572                 if (crtc == 4) {
1573                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1574                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1575                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1576                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1577                         ret |= DRM_SCANOUTPOS_VALID;
1578                 }
1579                 if (crtc == 5) {
1580                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1581                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1582                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1583                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1584                         ret |= DRM_SCANOUTPOS_VALID;
1585                 }
1586         } else if (ASIC_IS_AVIVO(rdev)) {
1587                 if (crtc == 0) {
1588                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1589                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1590                         ret |= DRM_SCANOUTPOS_VALID;
1591                 }
1592                 if (crtc == 1) {
1593                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1594                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1595                         ret |= DRM_SCANOUTPOS_VALID;
1596                 }
1597         } else {
1598                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1599                 if (crtc == 0) {
1600                         /* Assume vbl_end == 0, get vbl_start from
1601                          * upper 16 bits.
1602                          */
1603                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1604                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1605                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1606                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1607                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1608                         if (!(stat_crtc & 1))
1609                                 in_vbl = false;
1610
1611                         ret |= DRM_SCANOUTPOS_VALID;
1612                 }
1613                 if (crtc == 1) {
1614                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1615                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1616                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1617                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1618                         if (!(stat_crtc & 1))
1619                                 in_vbl = false;
1620
1621                         ret |= DRM_SCANOUTPOS_VALID;
1622                 }
1623         }
1624
1625         /* Decode into vertical and horizontal scanout position. */
1626         *vpos = position & 0x1fff;
1627         *hpos = (position >> 16) & 0x1fff;
1628
1629         /* Valid vblank area boundaries from gpu retrieved? */
1630         if (vbl > 0) {
1631                 /* Yes: Decode. */
1632                 ret |= DRM_SCANOUTPOS_ACCURATE;
1633                 vbl_start = vbl & 0x1fff;
1634                 vbl_end = (vbl >> 16) & 0x1fff;
1635         }
1636         else {
1637                 /* No: Fake something reasonable which gives at least ok results. */
1638                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1639                 vbl_end = 0;
1640         }
1641
1642         /* Test scanout position against vblank region. */
1643         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1644                 in_vbl = false;
1645
1646         /* Check if inside vblank area and apply corrective offsets:
1647          * vpos will then be >=0 in video scanout area, but negative
1648          * within vblank area, counting down the number of lines until
1649          * start of scanout.
1650          */
1651
1652         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1653         if (in_vbl && (*vpos >= vbl_start)) {
1654                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1655                 *vpos = *vpos - vtotal;
1656         }
1657
1658         /* Correct for shifted end of vbl at vbl_end. */
1659         *vpos = *vpos - vbl_end;
1660
1661         /* In vblank? */
1662         if (in_vbl)
1663                 ret |= DRM_SCANOUTPOS_INVBL;
1664
1665         return ret;
1666 }