2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
91 for (i = 0; i < 256; i++) {
92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
163 struct radeon_device *rdev = dev->dev_private;
167 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
168 if (radeon_crtc->crtc_id == 0)
169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
172 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
174 WREG8(RADEON_PALETTE_INDEX, 0);
175 for (i = 0; i < 256; i++) {
176 WREG32(RADEON_PALETTE_30_DATA,
177 (radeon_crtc->lut_r[i] << 20) |
178 (radeon_crtc->lut_g[i] << 10) |
179 (radeon_crtc->lut_b[i] << 0));
183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
185 struct drm_device *dev = crtc->dev;
186 struct radeon_device *rdev = dev->dev_private;
191 if (ASIC_IS_DCE5(rdev))
192 dce5_crtc_load_lut(crtc);
193 else if (ASIC_IS_DCE4(rdev))
194 dce4_crtc_load_lut(crtc);
195 else if (ASIC_IS_AVIVO(rdev))
196 avivo_crtc_load_lut(crtc);
198 legacy_crtc_load_lut(crtc);
201 /** Sets the color ramps on behalf of fbcon */
202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
207 radeon_crtc->lut_r[regno] = red >> 6;
208 radeon_crtc->lut_g[regno] = green >> 6;
209 radeon_crtc->lut_b[regno] = blue >> 6;
212 /** Gets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
214 u16 *blue, int regno)
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
218 *red = radeon_crtc->lut_r[regno] << 6;
219 *green = radeon_crtc->lut_g[regno] << 6;
220 *blue = radeon_crtc->lut_b[regno] << 6;
223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, uint32_t start, uint32_t size)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 int end = (start + size > 256) ? 256 : start + size, i;
229 /* userspace palettes are always correct as is */
230 for (i = start; i < end; i++) {
231 radeon_crtc->lut_r[i] = red[i] >> 6;
232 radeon_crtc->lut_g[i] = green[i] >> 6;
233 radeon_crtc->lut_b[i] = blue[i] >> 6;
235 radeon_crtc_load_lut(crtc);
238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
242 drm_crtc_cleanup(crtc);
247 * Handle unpin events outside the interrupt handler proper.
249 static void radeon_unpin_work_func(struct work_struct *__work)
251 struct radeon_unpin_work *work =
252 container_of(__work, struct radeon_unpin_work, work);
255 /* unpin of the old buffer */
256 r = radeon_bo_reserve(work->old_rbo, false);
257 if (likely(r == 0)) {
258 r = radeon_bo_unpin(work->old_rbo);
259 if (unlikely(r != 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
262 radeon_bo_unreserve(work->old_rbo);
264 DRM_ERROR("failed to reserve buffer after flip\n");
266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273 struct radeon_unpin_work *work;
274 struct drm_pending_vblank_event *e;
280 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281 work = radeon_crtc->unpin_work;
283 (work->fence && !radeon_fence_signaled(work->fence))) {
284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc->deferred_flip_completion) {
289 /* do the flip (mmio) */
290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
297 radeon_crtc->deferred_flip_completion = 0;
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
303 if (update_pending &&
304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
306 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
307 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. Based on the current
310 * scanout position we know that the current frame is
311 * (nearly) complete and the flip will (likely)
312 * complete before the start of the next frame.
316 if (update_pending) {
317 /* crtc didn't flip in this target vblank interval,
318 * but flip is pending in crtc. It will complete it
319 * in next vblank interval, so complete the flip at
322 radeon_crtc->deferred_flip_completion = 1;
323 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
328 radeon_crtc->unpin_work = NULL;
330 /* wakeup userspace */
333 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
334 e->event.tv_sec = now.tv_sec;
335 e->event.tv_usec = now.tv_usec;
336 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
337 wake_up_interruptible(&e->base.file_priv->event_wait);
339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 schedule_work(&work->work);
347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
349 struct drm_pending_vblank_event *event)
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 struct radeon_framebuffer *old_radeon_fb;
355 struct radeon_framebuffer *new_radeon_fb;
356 struct drm_gem_object *obj;
357 struct radeon_bo *rbo;
358 struct radeon_unpin_work *work;
360 u32 tiling_flags, pitch_pixels;
364 work = kzalloc(sizeof *work, GFP_KERNEL);
370 work->crtc_id = radeon_crtc->crtc_id;
371 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
372 new_radeon_fb = to_radeon_framebuffer(fb);
373 /* schedule unpin of the old buffer */
374 obj = old_radeon_fb->obj;
375 /* take a reference to the old object */
376 drm_gem_object_reference(obj);
377 rbo = gem_to_radeon_bo(obj);
379 obj = new_radeon_fb->obj;
380 rbo = gem_to_radeon_bo(obj);
381 if (rbo->tbo.sync_obj)
382 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
383 INIT_WORK(&work->work, radeon_unpin_work_func);
385 /* We borrow the event spin lock for protecting unpin_work */
386 spin_lock_irqsave(&dev->event_lock, flags);
387 if (radeon_crtc->unpin_work) {
388 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
392 radeon_crtc->unpin_work = work;
393 radeon_crtc->deferred_flip_completion = 0;
394 spin_unlock_irqrestore(&dev->event_lock, flags);
396 /* pin the new buffer */
397 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
400 r = radeon_bo_reserve(rbo, false);
401 if (unlikely(r != 0)) {
402 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
405 /* Only 27 bit offset for legacy CRTC */
406 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
407 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
408 if (unlikely(r != 0)) {
409 radeon_bo_unreserve(rbo);
411 DRM_ERROR("failed to pin new rbo buffer before flip\n");
414 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
415 radeon_bo_unreserve(rbo);
417 if (!ASIC_IS_AVIVO(rdev)) {
418 /* crtc offset is from display base addr not FB location */
419 base -= radeon_crtc->legacy_display_base_addr;
420 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
422 if (tiling_flags & RADEON_TILING_MACRO) {
423 if (ASIC_IS_R300(rdev)) {
426 int byteshift = fb->bits_per_pixel >> 4;
427 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
428 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
431 int offset = crtc->y * pitch_pixels + crtc->x;
432 switch (fb->bits_per_pixel) {
453 spin_lock_irqsave(&dev->event_lock, flags);
454 work->new_crtc_base = base;
455 spin_unlock_irqrestore(&dev->event_lock, flags);
460 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
462 DRM_ERROR("failed to get vblank before flip\n");
466 /* set the proper interrupt */
467 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
472 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
473 DRM_ERROR("failed to reserve new rbo in error path\n");
476 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
477 DRM_ERROR("failed to unpin new rbo in error path\n");
479 radeon_bo_unreserve(rbo);
482 spin_lock_irqsave(&dev->event_lock, flags);
483 radeon_crtc->unpin_work = NULL;
485 spin_unlock_irqrestore(&dev->event_lock, flags);
486 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
487 radeon_fence_unref(&work->fence);
493 static const struct drm_crtc_funcs radeon_crtc_funcs = {
494 .cursor_set = radeon_crtc_cursor_set,
495 .cursor_move = radeon_crtc_cursor_move,
496 .gamma_set = radeon_crtc_gamma_set,
497 .set_config = drm_crtc_helper_set_config,
498 .destroy = radeon_crtc_destroy,
499 .page_flip = radeon_crtc_page_flip,
502 static void radeon_crtc_init(struct drm_device *dev, int index)
504 struct radeon_device *rdev = dev->dev_private;
505 struct radeon_crtc *radeon_crtc;
508 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
509 if (radeon_crtc == NULL)
512 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
514 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
515 radeon_crtc->crtc_id = index;
516 rdev->mode_info.crtcs[index] = radeon_crtc;
519 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
520 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
521 radeon_crtc->mode_set.num_connectors = 0;
524 for (i = 0; i < 256; i++) {
525 radeon_crtc->lut_r[i] = i << 2;
526 radeon_crtc->lut_g[i] = i << 2;
527 radeon_crtc->lut_b[i] = i << 2;
530 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
531 radeon_atombios_init_crtc(dev, radeon_crtc);
533 radeon_legacy_init_crtc(dev, radeon_crtc);
536 static const char *encoder_names[36] = {
556 "INTERNAL_KLDSCP_TMDS1",
557 "INTERNAL_KLDSCP_DVO1",
558 "INTERNAL_KLDSCP_DAC1",
559 "INTERNAL_KLDSCP_DAC2",
568 "INTERNAL_KLDSCP_LVTMA",
575 static const char *connector_names[15] = {
593 static const char *hpd_names[6] = {
602 static void radeon_print_display_setup(struct drm_device *dev)
604 struct drm_connector *connector;
605 struct radeon_connector *radeon_connector;
606 struct drm_encoder *encoder;
607 struct radeon_encoder *radeon_encoder;
611 DRM_INFO("Radeon Display Connectors\n");
612 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
613 radeon_connector = to_radeon_connector(connector);
614 DRM_INFO("Connector %d:\n", i);
615 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
616 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
617 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
618 if (radeon_connector->ddc_bus) {
619 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
620 radeon_connector->ddc_bus->rec.mask_clk_reg,
621 radeon_connector->ddc_bus->rec.mask_data_reg,
622 radeon_connector->ddc_bus->rec.a_clk_reg,
623 radeon_connector->ddc_bus->rec.a_data_reg,
624 radeon_connector->ddc_bus->rec.en_clk_reg,
625 radeon_connector->ddc_bus->rec.en_data_reg,
626 radeon_connector->ddc_bus->rec.y_clk_reg,
627 radeon_connector->ddc_bus->rec.y_data_reg);
628 if (radeon_connector->router.ddc_valid)
629 DRM_INFO(" DDC Router 0x%x/0x%x\n",
630 radeon_connector->router.ddc_mux_control_pin,
631 radeon_connector->router.ddc_mux_state);
632 if (radeon_connector->router.cd_valid)
633 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
634 radeon_connector->router.cd_mux_control_pin,
635 radeon_connector->router.cd_mux_state);
637 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
638 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
639 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
640 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
641 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
642 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
643 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
645 DRM_INFO(" Encoders:\n");
646 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
647 radeon_encoder = to_radeon_encoder(encoder);
648 devices = radeon_encoder->devices & radeon_connector->devices;
650 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
651 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
652 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
653 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
654 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
655 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
656 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
657 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
658 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
659 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
660 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
661 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
662 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
663 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
664 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
665 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
666 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
667 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
668 if (devices & ATOM_DEVICE_TV1_SUPPORT)
669 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
670 if (devices & ATOM_DEVICE_CV_SUPPORT)
671 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
678 static bool radeon_setup_enc_conn(struct drm_device *dev)
680 struct radeon_device *rdev = dev->dev_private;
684 if (rdev->is_atom_bios) {
685 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
687 ret = radeon_get_atom_connector_info_from_object_table(dev);
689 ret = radeon_get_legacy_connector_info_from_bios(dev);
691 ret = radeon_get_legacy_connector_info_from_table(dev);
694 if (!ASIC_IS_AVIVO(rdev))
695 ret = radeon_get_legacy_connector_info_from_table(dev);
698 radeon_setup_encoder_clones(dev);
699 radeon_print_display_setup(dev);
705 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
707 struct drm_device *dev = radeon_connector->base.dev;
708 struct radeon_device *rdev = dev->dev_private;
711 /* on hw with routers, select right port */
712 if (radeon_connector->router.ddc_valid)
713 radeon_router_select_ddc_port(radeon_connector);
715 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
716 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
717 (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
718 ENCODER_OBJECT_ID_NONE)) {
719 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
721 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
722 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
723 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
724 &dig->dp_i2c_bus->adapter);
725 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
726 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
727 &radeon_connector->ddc_bus->adapter);
729 if (radeon_connector->ddc_bus && !radeon_connector->edid)
730 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
731 &radeon_connector->ddc_bus->adapter);
734 if (!radeon_connector->edid) {
735 if (rdev->is_atom_bios) {
736 /* some laptops provide a hardcoded edid in rom for LCDs */
737 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
738 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
739 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
741 /* some servers provide a hardcoded edid in rom for KVMs */
742 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
744 if (radeon_connector->edid) {
745 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
746 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
749 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
754 static void avivo_get_fb_div(struct radeon_pll *pll,
761 u32 tmp = post_div * ref_div;
764 *fb_div = tmp / pll->reference_freq;
765 *frac_fb_div = tmp % pll->reference_freq;
767 if (*fb_div > pll->max_feedback_div)
768 *fb_div = pll->max_feedback_div;
769 else if (*fb_div < pll->min_feedback_div)
770 *fb_div = pll->min_feedback_div;
773 static u32 avivo_get_post_div(struct radeon_pll *pll,
776 u32 vco, post_div, tmp;
778 if (pll->flags & RADEON_PLL_USE_POST_DIV)
779 return pll->post_div;
781 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
782 if (pll->flags & RADEON_PLL_IS_LCD)
783 vco = pll->lcd_pll_out_min;
785 vco = pll->pll_out_min;
787 if (pll->flags & RADEON_PLL_IS_LCD)
788 vco = pll->lcd_pll_out_max;
790 vco = pll->pll_out_max;
793 post_div = vco / target_clock;
794 tmp = vco % target_clock;
796 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
804 if (post_div > pll->max_post_div)
805 post_div = pll->max_post_div;
806 else if (post_div < pll->min_post_div)
807 post_div = pll->min_post_div;
812 #define MAX_TOLERANCE 10
814 void radeon_compute_pll_avivo(struct radeon_pll *pll,
822 u32 target_clock = freq / 10;
823 u32 post_div = avivo_get_post_div(pll, target_clock);
824 u32 ref_div = pll->min_ref_div;
825 u32 fb_div = 0, frac_fb_div = 0, tmp;
827 if (pll->flags & RADEON_PLL_USE_REF_DIV)
828 ref_div = pll->reference_div;
830 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
831 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
832 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
833 if (frac_fb_div >= 5) {
835 frac_fb_div = frac_fb_div / 10;
838 if (frac_fb_div >= 10) {
843 while (ref_div <= pll->max_ref_div) {
844 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
845 &fb_div, &frac_fb_div);
846 if (frac_fb_div >= (pll->reference_freq / 2))
849 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
850 tmp = (tmp * 10000) / target_clock;
852 if (tmp > (10000 + MAX_TOLERANCE))
854 else if (tmp >= (10000 - MAX_TOLERANCE))
861 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
862 (ref_div * post_div * 10);
864 *frac_fb_div_p = frac_fb_div;
865 *ref_div_p = ref_div;
866 *post_div_p = post_div;
867 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
868 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
872 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
882 void radeon_compute_pll_legacy(struct radeon_pll *pll,
884 uint32_t *dot_clock_p,
886 uint32_t *frac_fb_div_p,
888 uint32_t *post_div_p)
890 uint32_t min_ref_div = pll->min_ref_div;
891 uint32_t max_ref_div = pll->max_ref_div;
892 uint32_t min_post_div = pll->min_post_div;
893 uint32_t max_post_div = pll->max_post_div;
894 uint32_t min_fractional_feed_div = 0;
895 uint32_t max_fractional_feed_div = 0;
896 uint32_t best_vco = pll->best_vco;
897 uint32_t best_post_div = 1;
898 uint32_t best_ref_div = 1;
899 uint32_t best_feedback_div = 1;
900 uint32_t best_frac_feedback_div = 0;
901 uint32_t best_freq = -1;
902 uint32_t best_error = 0xffffffff;
903 uint32_t best_vco_diff = 1;
905 u32 pll_out_min, pll_out_max;
907 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
910 if (pll->flags & RADEON_PLL_IS_LCD) {
911 pll_out_min = pll->lcd_pll_out_min;
912 pll_out_max = pll->lcd_pll_out_max;
914 pll_out_min = pll->pll_out_min;
915 pll_out_max = pll->pll_out_max;
918 if (pll_out_min > 64800)
921 if (pll->flags & RADEON_PLL_USE_REF_DIV)
922 min_ref_div = max_ref_div = pll->reference_div;
924 while (min_ref_div < max_ref_div-1) {
925 uint32_t mid = (min_ref_div + max_ref_div) / 2;
926 uint32_t pll_in = pll->reference_freq / mid;
927 if (pll_in < pll->pll_in_min)
929 else if (pll_in > pll->pll_in_max)
936 if (pll->flags & RADEON_PLL_USE_POST_DIV)
937 min_post_div = max_post_div = pll->post_div;
939 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
940 min_fractional_feed_div = pll->min_frac_feedback_div;
941 max_fractional_feed_div = pll->max_frac_feedback_div;
944 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
947 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
950 /* legacy radeons only have a few post_divs */
951 if (pll->flags & RADEON_PLL_LEGACY) {
952 if ((post_div == 5) ||
963 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
964 uint32_t feedback_div, current_freq = 0, error, vco_diff;
965 uint32_t pll_in = pll->reference_freq / ref_div;
966 uint32_t min_feed_div = pll->min_feedback_div;
967 uint32_t max_feed_div = pll->max_feedback_div + 1;
969 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
972 while (min_feed_div < max_feed_div) {
974 uint32_t min_frac_feed_div = min_fractional_feed_div;
975 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
976 uint32_t frac_feedback_div;
979 feedback_div = (min_feed_div + max_feed_div) / 2;
981 tmp = (uint64_t)pll->reference_freq * feedback_div;
982 vco = radeon_div(tmp, ref_div);
984 if (vco < pll_out_min) {
985 min_feed_div = feedback_div + 1;
987 } else if (vco > pll_out_max) {
988 max_feed_div = feedback_div;
992 while (min_frac_feed_div < max_frac_feed_div) {
993 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
994 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
995 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
996 current_freq = radeon_div(tmp, ref_div * post_div);
998 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
999 if (freq < current_freq)
1002 error = freq - current_freq;
1004 error = abs(current_freq - freq);
1005 vco_diff = abs(vco - best_vco);
1007 if ((best_vco == 0 && error < best_error) ||
1009 ((best_error > 100 && error < best_error - 100) ||
1010 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1011 best_post_div = post_div;
1012 best_ref_div = ref_div;
1013 best_feedback_div = feedback_div;
1014 best_frac_feedback_div = frac_feedback_div;
1015 best_freq = current_freq;
1017 best_vco_diff = vco_diff;
1018 } else if (current_freq == freq) {
1019 if (best_freq == -1) {
1020 best_post_div = post_div;
1021 best_ref_div = ref_div;
1022 best_feedback_div = feedback_div;
1023 best_frac_feedback_div = frac_feedback_div;
1024 best_freq = current_freq;
1026 best_vco_diff = vco_diff;
1027 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1028 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1029 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1030 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1031 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1032 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1033 best_post_div = post_div;
1034 best_ref_div = ref_div;
1035 best_feedback_div = feedback_div;
1036 best_frac_feedback_div = frac_feedback_div;
1037 best_freq = current_freq;
1039 best_vco_diff = vco_diff;
1042 if (current_freq < freq)
1043 min_frac_feed_div = frac_feedback_div + 1;
1045 max_frac_feed_div = frac_feedback_div;
1047 if (current_freq < freq)
1048 min_feed_div = feedback_div + 1;
1050 max_feed_div = feedback_div;
1055 *dot_clock_p = best_freq / 10000;
1056 *fb_div_p = best_feedback_div;
1057 *frac_fb_div_p = best_frac_feedback_div;
1058 *ref_div_p = best_ref_div;
1059 *post_div_p = best_post_div;
1060 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1062 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1063 best_ref_div, best_post_div);
1067 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1069 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1071 if (radeon_fb->obj) {
1072 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1074 drm_framebuffer_cleanup(fb);
1078 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1079 struct drm_file *file_priv,
1080 unsigned int *handle)
1082 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1084 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1087 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1088 .destroy = radeon_user_framebuffer_destroy,
1089 .create_handle = radeon_user_framebuffer_create_handle,
1093 radeon_framebuffer_init(struct drm_device *dev,
1094 struct radeon_framebuffer *rfb,
1095 struct drm_mode_fb_cmd2 *mode_cmd,
1096 struct drm_gem_object *obj)
1100 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1105 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1109 static struct drm_framebuffer *
1110 radeon_user_framebuffer_create(struct drm_device *dev,
1111 struct drm_file *file_priv,
1112 struct drm_mode_fb_cmd2 *mode_cmd)
1114 struct drm_gem_object *obj;
1115 struct radeon_framebuffer *radeon_fb;
1118 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1120 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1121 "can't create framebuffer\n", mode_cmd->handles[0]);
1122 return ERR_PTR(-ENOENT);
1125 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1126 if (radeon_fb == NULL)
1127 return ERR_PTR(-ENOMEM);
1129 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1132 drm_gem_object_unreference_unlocked(obj);
1136 return &radeon_fb->base;
1139 static void radeon_output_poll_changed(struct drm_device *dev)
1141 struct radeon_device *rdev = dev->dev_private;
1142 radeon_fb_output_poll_changed(rdev);
1145 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1146 .fb_create = radeon_user_framebuffer_create,
1147 .output_poll_changed = radeon_output_poll_changed
1150 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1155 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1156 { { TV_STD_NTSC, "ntsc" },
1157 { TV_STD_PAL, "pal" },
1158 { TV_STD_PAL_M, "pal-m" },
1159 { TV_STD_PAL_60, "pal-60" },
1160 { TV_STD_NTSC_J, "ntsc-j" },
1161 { TV_STD_SCART_PAL, "scart-pal" },
1162 { TV_STD_PAL_CN, "pal-cn" },
1163 { TV_STD_SECAM, "secam" },
1166 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1167 { { UNDERSCAN_OFF, "off" },
1168 { UNDERSCAN_ON, "on" },
1169 { UNDERSCAN_AUTO, "auto" },
1172 static int radeon_modeset_create_props(struct radeon_device *rdev)
1176 if (rdev->is_atom_bios) {
1177 rdev->mode_info.coherent_mode_property =
1178 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1179 if (!rdev->mode_info.coherent_mode_property)
1183 if (!ASIC_IS_AVIVO(rdev)) {
1184 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1185 rdev->mode_info.tmds_pll_property =
1186 drm_property_create_enum(rdev->ddev, 0,
1188 radeon_tmds_pll_enum_list, sz);
1191 rdev->mode_info.load_detect_property =
1192 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1193 if (!rdev->mode_info.load_detect_property)
1196 drm_mode_create_scaling_mode_property(rdev->ddev);
1198 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1199 rdev->mode_info.tv_std_property =
1200 drm_property_create_enum(rdev->ddev, 0,
1202 radeon_tv_std_enum_list, sz);
1204 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1205 rdev->mode_info.underscan_property =
1206 drm_property_create_enum(rdev->ddev, 0,
1208 radeon_underscan_enum_list, sz);
1210 rdev->mode_info.underscan_hborder_property =
1211 drm_property_create_range(rdev->ddev, 0,
1212 "underscan hborder", 0, 128);
1213 if (!rdev->mode_info.underscan_hborder_property)
1216 rdev->mode_info.underscan_vborder_property =
1217 drm_property_create_range(rdev->ddev, 0,
1218 "underscan vborder", 0, 128);
1219 if (!rdev->mode_info.underscan_vborder_property)
1225 void radeon_update_display_priority(struct radeon_device *rdev)
1227 /* adjustment options for the display watermarks */
1228 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1229 /* set display priority to high for r3xx, rv515 chips
1230 * this avoids flickering due to underflow to the
1231 * display controllers during heavy acceleration.
1232 * Don't force high on rs4xx igp chips as it seems to
1233 * affect the sound card. See kernel bug 15982.
1235 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1236 !(rdev->flags & RADEON_IS_IGP))
1237 rdev->disp_priority = 2;
1239 rdev->disp_priority = 0;
1241 rdev->disp_priority = radeon_disp_priority;
1245 int radeon_modeset_init(struct radeon_device *rdev)
1250 drm_mode_config_init(rdev->ddev);
1251 rdev->mode_info.mode_config_initialized = true;
1253 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1255 if (ASIC_IS_DCE5(rdev)) {
1256 rdev->ddev->mode_config.max_width = 16384;
1257 rdev->ddev->mode_config.max_height = 16384;
1258 } else if (ASIC_IS_AVIVO(rdev)) {
1259 rdev->ddev->mode_config.max_width = 8192;
1260 rdev->ddev->mode_config.max_height = 8192;
1262 rdev->ddev->mode_config.max_width = 4096;
1263 rdev->ddev->mode_config.max_height = 4096;
1266 rdev->ddev->mode_config.preferred_depth = 24;
1267 rdev->ddev->mode_config.prefer_shadow = 1;
1269 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1271 ret = radeon_modeset_create_props(rdev);
1276 /* init i2c buses */
1277 radeon_i2c_init(rdev);
1279 /* check combios for a valid hardcoded EDID - Sun servers */
1280 if (!rdev->is_atom_bios) {
1281 /* check for hardcoded EDID in BIOS */
1282 radeon_combios_check_hardcoded_edid(rdev);
1285 /* allocate crtcs */
1286 for (i = 0; i < rdev->num_crtc; i++) {
1287 radeon_crtc_init(rdev->ddev, i);
1290 /* okay we should have all the bios connectors */
1291 ret = radeon_setup_enc_conn(rdev->ddev);
1296 /* init dig PHYs, disp eng pll */
1297 if (rdev->is_atom_bios) {
1298 radeon_atom_encoder_init(rdev);
1299 radeon_atom_disp_eng_pll_init(rdev);
1302 /* initialize hpd */
1303 radeon_hpd_init(rdev);
1305 /* Initialize power management */
1306 radeon_pm_init(rdev);
1308 radeon_fbdev_init(rdev);
1309 drm_kms_helper_poll_init(rdev->ddev);
1314 void radeon_modeset_fini(struct radeon_device *rdev)
1316 radeon_fbdev_fini(rdev);
1317 kfree(rdev->mode_info.bios_hardcoded_edid);
1318 radeon_pm_fini(rdev);
1320 if (rdev->mode_info.mode_config_initialized) {
1321 drm_kms_helper_poll_fini(rdev->ddev);
1322 radeon_hpd_fini(rdev);
1323 drm_mode_config_cleanup(rdev->ddev);
1324 rdev->mode_info.mode_config_initialized = false;
1326 /* free i2c buses */
1327 radeon_i2c_fini(rdev);
1330 static bool is_hdtv_mode(struct drm_display_mode *mode)
1332 /* try and guess if this is a tv or a monitor */
1333 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1334 (mode->vdisplay == 576) || /* 576p */
1335 (mode->vdisplay == 720) || /* 720p */
1336 (mode->vdisplay == 1080)) /* 1080p */
1342 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1343 struct drm_display_mode *mode,
1344 struct drm_display_mode *adjusted_mode)
1346 struct drm_device *dev = crtc->dev;
1347 struct radeon_device *rdev = dev->dev_private;
1348 struct drm_encoder *encoder;
1349 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1350 struct radeon_encoder *radeon_encoder;
1351 struct drm_connector *connector;
1352 struct radeon_connector *radeon_connector;
1354 u32 src_v = 1, dst_v = 1;
1355 u32 src_h = 1, dst_h = 1;
1357 radeon_crtc->h_border = 0;
1358 radeon_crtc->v_border = 0;
1360 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1361 if (encoder->crtc != crtc)
1363 radeon_encoder = to_radeon_encoder(encoder);
1364 connector = radeon_get_connector_for_encoder(encoder);
1365 radeon_connector = to_radeon_connector(connector);
1369 if (radeon_encoder->rmx_type == RMX_OFF)
1370 radeon_crtc->rmx_type = RMX_OFF;
1371 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1372 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1373 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1375 radeon_crtc->rmx_type = RMX_OFF;
1376 /* copy native mode */
1377 memcpy(&radeon_crtc->native_mode,
1378 &radeon_encoder->native_mode,
1379 sizeof(struct drm_display_mode));
1380 src_v = crtc->mode.vdisplay;
1381 dst_v = radeon_crtc->native_mode.vdisplay;
1382 src_h = crtc->mode.hdisplay;
1383 dst_h = radeon_crtc->native_mode.hdisplay;
1385 /* fix up for overscan on hdmi */
1386 if (ASIC_IS_AVIVO(rdev) &&
1387 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1388 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1389 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1390 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1391 is_hdtv_mode(mode)))) {
1392 if (radeon_encoder->underscan_hborder != 0)
1393 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1395 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1396 if (radeon_encoder->underscan_vborder != 0)
1397 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1399 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1400 radeon_crtc->rmx_type = RMX_FULL;
1401 src_v = crtc->mode.vdisplay;
1402 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1403 src_h = crtc->mode.hdisplay;
1404 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1408 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1409 /* WARNING: Right now this can't happen but
1410 * in the future we need to check that scaling
1411 * are consistent across different encoder
1412 * (ie all encoder can work with the same
1415 DRM_ERROR("Scaling not consistent across encoder.\n");
1420 if (radeon_crtc->rmx_type != RMX_OFF) {
1422 a.full = dfixed_const(src_v);
1423 b.full = dfixed_const(dst_v);
1424 radeon_crtc->vsc.full = dfixed_div(a, b);
1425 a.full = dfixed_const(src_h);
1426 b.full = dfixed_const(dst_h);
1427 radeon_crtc->hsc.full = dfixed_div(a, b);
1429 radeon_crtc->vsc.full = dfixed_const(1);
1430 radeon_crtc->hsc.full = dfixed_const(1);
1436 * Retrieve current video scanout position of crtc on a given gpu.
1438 * \param dev Device to query.
1439 * \param crtc Crtc to query.
1440 * \param *vpos Location where vertical scanout position should be stored.
1441 * \param *hpos Location where horizontal scanout position should go.
1443 * Returns vpos as a positive number while in active scanout area.
1444 * Returns vpos as a negative number inside vblank, counting the number
1445 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1446 * until start of active scanout / end of vblank."
1448 * \return Flags, or'ed together as follows:
1450 * DRM_SCANOUTPOS_VALID = Query successful.
1451 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1452 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1453 * this flag means that returned position may be offset by a constant but
1454 * unknown small number of scanlines wrt. real scanout position.
1457 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1459 u32 stat_crtc = 0, vbl = 0, position = 0;
1460 int vbl_start, vbl_end, vtotal, ret = 0;
1463 struct radeon_device *rdev = dev->dev_private;
1465 if (ASIC_IS_DCE4(rdev)) {
1467 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1468 EVERGREEN_CRTC0_REGISTER_OFFSET);
1469 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1470 EVERGREEN_CRTC0_REGISTER_OFFSET);
1471 ret |= DRM_SCANOUTPOS_VALID;
1474 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1475 EVERGREEN_CRTC1_REGISTER_OFFSET);
1476 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1477 EVERGREEN_CRTC1_REGISTER_OFFSET);
1478 ret |= DRM_SCANOUTPOS_VALID;
1481 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1482 EVERGREEN_CRTC2_REGISTER_OFFSET);
1483 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1484 EVERGREEN_CRTC2_REGISTER_OFFSET);
1485 ret |= DRM_SCANOUTPOS_VALID;
1488 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1489 EVERGREEN_CRTC3_REGISTER_OFFSET);
1490 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1491 EVERGREEN_CRTC3_REGISTER_OFFSET);
1492 ret |= DRM_SCANOUTPOS_VALID;
1495 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1496 EVERGREEN_CRTC4_REGISTER_OFFSET);
1497 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1498 EVERGREEN_CRTC4_REGISTER_OFFSET);
1499 ret |= DRM_SCANOUTPOS_VALID;
1502 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1503 EVERGREEN_CRTC5_REGISTER_OFFSET);
1504 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1505 EVERGREEN_CRTC5_REGISTER_OFFSET);
1506 ret |= DRM_SCANOUTPOS_VALID;
1508 } else if (ASIC_IS_AVIVO(rdev)) {
1510 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1511 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1512 ret |= DRM_SCANOUTPOS_VALID;
1515 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1516 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1517 ret |= DRM_SCANOUTPOS_VALID;
1520 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1522 /* Assume vbl_end == 0, get vbl_start from
1525 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1526 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1527 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1528 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1529 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1530 if (!(stat_crtc & 1))
1533 ret |= DRM_SCANOUTPOS_VALID;
1536 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1537 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1538 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1539 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1540 if (!(stat_crtc & 1))
1543 ret |= DRM_SCANOUTPOS_VALID;
1547 /* Decode into vertical and horizontal scanout position. */
1548 *vpos = position & 0x1fff;
1549 *hpos = (position >> 16) & 0x1fff;
1551 /* Valid vblank area boundaries from gpu retrieved? */
1554 ret |= DRM_SCANOUTPOS_ACCURATE;
1555 vbl_start = vbl & 0x1fff;
1556 vbl_end = (vbl >> 16) & 0x1fff;
1559 /* No: Fake something reasonable which gives at least ok results. */
1560 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1564 /* Test scanout position against vblank region. */
1565 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1568 /* Check if inside vblank area and apply corrective offsets:
1569 * vpos will then be >=0 in video scanout area, but negative
1570 * within vblank area, counting down the number of lines until
1574 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1575 if (in_vbl && (*vpos >= vbl_start)) {
1576 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1577 *vpos = *vpos - vtotal;
1580 /* Correct for shifted end of vbl at vbl_end. */
1581 *vpos = *vpos - vbl_end;
1585 ret |= DRM_SCANOUTPOS_INVBL;