2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 static struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
240 if (!rdev->is_atom_bios)
243 connector = radeon_get_connector_for_encoder(encoder);
247 radeon_connector = to_radeon_connector(connector);
249 if (!radeon_connector->con_priv)
252 dig_connector = radeon_connector->con_priv;
254 return dig_connector;
257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode)
261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
262 struct drm_device *dev = encoder->dev;
263 struct radeon_device *rdev = dev->dev_private;
265 /* adjust pm to upcoming mode change */
266 radeon_pm_compute_clocks(rdev);
268 /* set the active encoder to connector routing */
269 radeon_encoder_set_active_device(encoder);
270 drm_mode_set_crtcinfo(adjusted_mode, 0);
273 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
274 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
275 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
277 /* get the native mode for LVDS */
278 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
279 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
280 int mode_id = adjusted_mode->base.id;
281 *adjusted_mode = *native_mode;
282 if (!ASIC_IS_AVIVO(rdev)) {
283 adjusted_mode->hdisplay = mode->hdisplay;
284 adjusted_mode->vdisplay = mode->vdisplay;
285 adjusted_mode->crtc_hdisplay = mode->hdisplay;
286 adjusted_mode->crtc_vdisplay = mode->vdisplay;
288 adjusted_mode->base.id = mode_id;
291 /* get the native mode for TV */
292 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
293 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
295 if (tv_dac->tv_std == TV_STD_NTSC ||
296 tv_dac->tv_std == TV_STD_NTSC_J ||
297 tv_dac->tv_std == TV_STD_PAL_M)
298 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
300 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
304 if (ASIC_IS_DCE3(rdev) &&
305 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
306 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
307 radeon_dp_set_link_config(connector, mode);
314 atombios_dac_setup(struct drm_encoder *encoder, int action)
316 struct drm_device *dev = encoder->dev;
317 struct radeon_device *rdev = dev->dev_private;
318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
319 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
320 int index = 0, num = 0;
321 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
322 enum radeon_tv_std tv_std = TV_STD_NTSC;
324 if (dac_info->tv_std)
325 tv_std = dac_info->tv_std;
327 memset(&args, 0, sizeof(args));
329 switch (radeon_encoder->encoder_id) {
330 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
332 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
335 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
337 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
342 args.ucAction = action;
344 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
345 args.ucDacStandard = ATOM_DAC1_PS2;
346 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_CV;
352 case TV_STD_SCART_PAL:
355 args.ucDacStandard = ATOM_DAC1_PAL;
361 args.ucDacStandard = ATOM_DAC1_NTSC;
365 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
372 atombios_tv_setup(struct drm_encoder *encoder, int action)
374 struct drm_device *dev = encoder->dev;
375 struct radeon_device *rdev = dev->dev_private;
376 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
377 TV_ENCODER_CONTROL_PS_ALLOCATION args;
379 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
380 enum radeon_tv_std tv_std = TV_STD_NTSC;
382 if (dac_info->tv_std)
383 tv_std = dac_info->tv_std;
385 memset(&args, 0, sizeof(args));
387 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
389 args.sTVEncoder.ucAction = action;
391 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
392 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
396 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
399 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
402 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
405 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
408 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
410 case TV_STD_SCART_PAL:
411 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
414 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
417 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
420 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
425 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
440 memset(&args, 0, sizeof(args));
442 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
444 args.sXTmdsEncoder.ucEnable = action;
446 if (radeon_encoder->pixel_clock > 165000)
447 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
449 /*if (pScrn->rgbBits == 8)*/
450 args.sXTmdsEncoder.ucMisc |= (1 << 1);
452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
459 struct drm_device *dev = encoder->dev;
460 struct radeon_device *rdev = dev->dev_private;
461 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
462 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
465 memset(&args, 0, sizeof(args));
467 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
469 args.sDVOEncoder.ucAction = action;
470 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 if (radeon_encoder->pixel_clock > 165000)
473 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
475 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
479 union lvds_encoder_control {
480 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
481 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
485 atombios_digital_setup(struct drm_encoder *encoder, int action)
487 struct drm_device *dev = encoder->dev;
488 struct radeon_device *rdev = dev->dev_private;
489 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
490 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
491 struct radeon_connector_atom_dig *dig_connector =
492 radeon_get_atom_connector_priv_from_encoder(encoder);
493 union lvds_encoder_control args;
495 int hdmi_detected = 0;
498 if (!dig || !dig_connector)
501 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
504 memset(&args, 0, sizeof(args));
506 switch (radeon_encoder->encoder_id) {
507 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
508 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
510 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
512 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
514 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
515 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
516 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
518 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
522 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
531 args.v1.ucAction = action;
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
534 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
536 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
537 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
539 args.v1.ucMisc |= (1 << 1);
541 if (dig_connector->linkb)
542 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
543 if (radeon_encoder->pixel_clock > 165000)
544 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
545 /*if (pScrn->rgbBits == 8) */
546 args.v1.ucMisc |= (1 << 1);
552 args.v2.ucAction = action;
554 if (dig->coherent_mode)
555 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
558 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
559 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
560 args.v2.ucTruncate = 0;
561 args.v2.ucSpatial = 0;
562 args.v2.ucTemporal = 0;
564 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
565 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
566 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
567 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
568 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
569 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
570 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
572 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
573 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
574 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
575 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
576 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
577 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
580 if (dig_connector->linkb)
581 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
582 if (radeon_encoder->pixel_clock > 165000)
583 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
587 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
592 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
596 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
600 atombios_get_encoder_mode(struct drm_encoder *encoder)
602 struct drm_connector *connector;
603 struct radeon_connector *radeon_connector;
604 struct radeon_connector_atom_dig *dig_connector;
606 connector = radeon_get_connector_for_encoder(encoder);
610 radeon_connector = to_radeon_connector(connector);
612 switch (connector->connector_type) {
613 case DRM_MODE_CONNECTOR_DVII:
614 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
615 if (drm_detect_hdmi_monitor(radeon_connector->edid))
616 return ATOM_ENCODER_MODE_HDMI;
617 else if (radeon_connector->use_digital)
618 return ATOM_ENCODER_MODE_DVI;
620 return ATOM_ENCODER_MODE_CRT;
622 case DRM_MODE_CONNECTOR_DVID:
623 case DRM_MODE_CONNECTOR_HDMIA:
625 if (drm_detect_hdmi_monitor(radeon_connector->edid))
626 return ATOM_ENCODER_MODE_HDMI;
628 return ATOM_ENCODER_MODE_DVI;
630 case DRM_MODE_CONNECTOR_LVDS:
631 return ATOM_ENCODER_MODE_LVDS;
633 case DRM_MODE_CONNECTOR_DisplayPort:
634 case DRM_MODE_CONNECTOR_eDP:
635 dig_connector = radeon_connector->con_priv;
636 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
637 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
638 return ATOM_ENCODER_MODE_DP;
639 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
640 return ATOM_ENCODER_MODE_HDMI;
642 return ATOM_ENCODER_MODE_DVI;
644 case DRM_MODE_CONNECTOR_DVIA:
645 case DRM_MODE_CONNECTOR_VGA:
646 return ATOM_ENCODER_MODE_CRT;
648 case DRM_MODE_CONNECTOR_Composite:
649 case DRM_MODE_CONNECTOR_SVIDEO:
650 case DRM_MODE_CONNECTOR_9PinDIN:
652 return ATOM_ENCODER_MODE_TV;
653 /*return ATOM_ENCODER_MODE_CV;*/
659 * DIG Encoder/Transmitter Setup
662 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
663 * Supports up to 3 digital outputs
664 * - 2 DIG encoder blocks.
665 * DIG1 can drive UNIPHY link A or link B
666 * DIG2 can drive UNIPHY link B or LVTMA
669 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
670 * Supports up to 5 digital outputs
671 * - 2 DIG encoder blocks.
672 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
675 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
676 * Supports up to 6 digital outputs
677 * - 6 DIG encoder blocks.
678 * - DIG to PHY mapping is hardcoded
679 * DIG1 drives UNIPHY0 link A, A+B
680 * DIG2 drives UNIPHY0 link B
681 * DIG3 drives UNIPHY1 link A, A+B
682 * DIG4 drives UNIPHY1 link B
683 * DIG5 drives UNIPHY2 link A, A+B
684 * DIG6 drives UNIPHY2 link B
687 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
689 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
690 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
691 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
692 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
695 union dig_encoder_control {
696 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
697 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
698 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
702 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
704 struct drm_device *dev = encoder->dev;
705 struct radeon_device *rdev = dev->dev_private;
706 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
707 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
708 struct radeon_connector_atom_dig *dig_connector =
709 radeon_get_atom_connector_priv_from_encoder(encoder);
710 union dig_encoder_control args;
714 if (!dig || !dig_connector)
717 memset(&args, 0, sizeof(args));
719 if (ASIC_IS_DCE4(rdev))
720 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
722 if (dig->dig_encoder)
723 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
725 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
728 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
731 args.v1.ucAction = action;
732 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
733 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
735 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
736 if (dig_connector->dp_clock == 270000)
737 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
738 args.v1.ucLaneNum = dig_connector->dp_lane_count;
739 } else if (radeon_encoder->pixel_clock > 165000)
740 args.v1.ucLaneNum = 8;
742 args.v1.ucLaneNum = 4;
744 if (ASIC_IS_DCE4(rdev)) {
745 args.v3.acConfig.ucDigSel = dig->dig_encoder;
746 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
748 switch (radeon_encoder->encoder_id) {
749 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
750 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
752 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
753 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
754 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
757 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
760 if (dig_connector->linkb)
761 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
763 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
766 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
770 union dig_transmitter_control {
771 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
772 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
773 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
777 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
779 struct drm_device *dev = encoder->dev;
780 struct radeon_device *rdev = dev->dev_private;
781 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
782 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
783 struct radeon_connector_atom_dig *dig_connector =
784 radeon_get_atom_connector_priv_from_encoder(encoder);
785 struct drm_connector *connector;
786 struct radeon_connector *radeon_connector;
787 union dig_transmitter_control args;
793 if (!dig || !dig_connector)
796 connector = radeon_get_connector_for_encoder(encoder);
797 radeon_connector = to_radeon_connector(connector);
799 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
802 memset(&args, 0, sizeof(args));
804 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
805 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
807 switch (radeon_encoder->encoder_id) {
808 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
809 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
812 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
817 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
820 args.v1.ucAction = action;
821 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
822 args.v1.usInitInfo = radeon_connector->connector_object_id;
823 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
824 args.v1.asMode.ucLaneSel = lane_num;
825 args.v1.asMode.ucLaneSet = lane_set;
828 args.v1.usPixelClock =
829 cpu_to_le16(dig_connector->dp_clock / 10);
830 else if (radeon_encoder->pixel_clock > 165000)
831 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
833 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
835 if (ASIC_IS_DCE4(rdev)) {
837 args.v3.ucLaneNum = dig_connector->dp_lane_count;
838 else if (radeon_encoder->pixel_clock > 165000)
839 args.v3.ucLaneNum = 8;
841 args.v3.ucLaneNum = 4;
843 if (dig_connector->linkb) {
844 args.v3.acConfig.ucLinkSel = 1;
845 args.v3.acConfig.ucEncoderSel = 1;
848 /* Select the PLL for the PHY
849 * DP PHY should be clocked from external src if there is
853 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
854 pll_id = radeon_crtc->pll_id;
856 if (is_dp && rdev->clock.dp_extclk)
857 args.v3.acConfig.ucRefClkSource = 2; /* external src */
859 args.v3.acConfig.ucRefClkSource = pll_id;
861 switch (radeon_encoder->encoder_id) {
862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
863 args.v3.acConfig.ucTransmitterSel = 0;
865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
866 args.v3.acConfig.ucTransmitterSel = 1;
868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
869 args.v3.acConfig.ucTransmitterSel = 2;
874 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
875 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
876 if (dig->coherent_mode)
877 args.v3.acConfig.fCoherentMode = 1;
879 } else if (ASIC_IS_DCE32(rdev)) {
880 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
881 if (dig_connector->linkb)
882 args.v2.acConfig.ucLinkSel = 1;
884 switch (radeon_encoder->encoder_id) {
885 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
886 args.v2.acConfig.ucTransmitterSel = 0;
888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
889 args.v2.acConfig.ucTransmitterSel = 1;
891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
892 args.v2.acConfig.ucTransmitterSel = 2;
897 args.v2.acConfig.fCoherentMode = 1;
898 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
899 if (dig->coherent_mode)
900 args.v2.acConfig.fCoherentMode = 1;
903 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
905 if (dig->dig_encoder)
906 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
908 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
910 if ((rdev->flags & RADEON_IS_IGP) &&
911 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
912 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
913 if (dig_connector->igp_lane_info & 0x1)
914 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
915 else if (dig_connector->igp_lane_info & 0x2)
916 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
917 else if (dig_connector->igp_lane_info & 0x4)
918 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
919 else if (dig_connector->igp_lane_info & 0x8)
920 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
922 if (dig_connector->igp_lane_info & 0x3)
923 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
924 else if (dig_connector->igp_lane_info & 0xc)
925 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
929 if (dig_connector->linkb)
930 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
932 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
935 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
936 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
937 if (dig->coherent_mode)
938 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
939 if (radeon_encoder->pixel_clock > 165000)
940 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
944 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
948 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
950 struct drm_device *dev = encoder->dev;
951 struct radeon_device *rdev = dev->dev_private;
952 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
953 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
954 ENABLE_YUV_PS_ALLOCATION args;
955 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
958 memset(&args, 0, sizeof(args));
960 if (rdev->family >= CHIP_R600)
961 reg = R600_BIOS_3_SCRATCH;
963 reg = RADEON_BIOS_3_SCRATCH;
965 /* XXX: fix up scratch reg handling */
967 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
968 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
969 (radeon_crtc->crtc_id << 18)));
970 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
971 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
976 args.ucEnable = ATOM_ENABLE;
977 args.ucCRTC = radeon_crtc->crtc_id;
979 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
985 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
987 struct drm_device *dev = encoder->dev;
988 struct radeon_device *rdev = dev->dev_private;
989 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
990 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
994 memset(&args, 0, sizeof(args));
996 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
997 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
998 radeon_encoder->active_device);
999 switch (radeon_encoder->encoder_id) {
1000 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1001 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1002 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1005 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1007 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1010 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1011 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1012 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1013 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1015 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1016 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1018 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1019 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1020 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1022 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1024 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1025 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1026 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1027 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1028 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1029 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1031 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1033 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1034 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1035 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1036 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1037 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1038 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1040 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1046 case DRM_MODE_DPMS_ON:
1047 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1048 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1050 dp_link_train(encoder, connector);
1051 if (ASIC_IS_DCE4(rdev))
1052 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1054 if (!ASIC_IS_DCE4(rdev))
1055 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1057 case DRM_MODE_DPMS_STANDBY:
1058 case DRM_MODE_DPMS_SUSPEND:
1059 case DRM_MODE_DPMS_OFF:
1060 if (!ASIC_IS_DCE4(rdev))
1061 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1062 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1063 if (ASIC_IS_DCE4(rdev))
1064 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1070 case DRM_MODE_DPMS_ON:
1071 args.ucAction = ATOM_ENABLE;
1073 case DRM_MODE_DPMS_STANDBY:
1074 case DRM_MODE_DPMS_SUSPEND:
1075 case DRM_MODE_DPMS_OFF:
1076 args.ucAction = ATOM_DISABLE;
1079 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1081 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1083 /* adjust pm to dpms change */
1084 radeon_pm_compute_clocks(rdev);
1087 union crtc_source_param {
1088 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1089 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1093 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1095 struct drm_device *dev = encoder->dev;
1096 struct radeon_device *rdev = dev->dev_private;
1097 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1098 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1099 union crtc_source_param args;
1100 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1102 struct radeon_encoder_atom_dig *dig;
1104 memset(&args, 0, sizeof(args));
1106 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1114 if (ASIC_IS_AVIVO(rdev))
1115 args.v1.ucCRTC = radeon_crtc->crtc_id;
1117 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1118 args.v1.ucCRTC = radeon_crtc->crtc_id;
1120 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1123 switch (radeon_encoder->encoder_id) {
1124 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1126 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1128 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1129 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1130 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1131 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1133 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1135 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1136 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1138 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1140 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1141 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1142 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1143 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1144 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1145 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1147 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1149 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1150 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1151 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1152 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1153 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1154 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1156 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1161 args.v2.ucCRTC = radeon_crtc->crtc_id;
1162 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1163 switch (radeon_encoder->encoder_id) {
1164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1168 dig = radeon_encoder->enc_priv;
1169 switch (dig->dig_encoder) {
1171 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1174 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1177 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1180 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1183 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1186 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1190 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1191 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1193 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1194 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1195 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1196 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1197 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1199 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1201 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1202 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1203 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1204 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1205 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1207 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1214 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1218 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1220 /* update scratch regs with new routing */
1221 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1225 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1226 struct drm_display_mode *mode)
1228 struct drm_device *dev = encoder->dev;
1229 struct radeon_device *rdev = dev->dev_private;
1230 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1231 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1233 /* Funky macbooks */
1234 if ((dev->pdev->device == 0x71C5) &&
1235 (dev->pdev->subsystem_vendor == 0x106b) &&
1236 (dev->pdev->subsystem_device == 0x0080)) {
1237 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1238 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1240 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1241 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1243 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1247 /* set scaler clears this on some chips */
1248 /* XXX check DCE4 */
1249 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1250 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1251 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1252 AVIVO_D1MODE_INTERLEAVE_EN);
1256 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1258 struct drm_device *dev = encoder->dev;
1259 struct radeon_device *rdev = dev->dev_private;
1260 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1262 struct drm_encoder *test_encoder;
1263 struct radeon_encoder_atom_dig *dig;
1264 uint32_t dig_enc_in_use = 0;
1266 if (ASIC_IS_DCE4(rdev)) {
1267 struct radeon_connector_atom_dig *dig_connector =
1268 radeon_get_atom_connector_priv_from_encoder(encoder);
1270 switch (radeon_encoder->encoder_id) {
1271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1272 if (dig_connector->linkb)
1277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1278 if (dig_connector->linkb)
1283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1284 if (dig_connector->linkb)
1292 /* on DCE32 and encoder can driver any block so just crtc id */
1293 if (ASIC_IS_DCE32(rdev)) {
1294 return radeon_crtc->crtc_id;
1297 /* on DCE3 - LVTMA can only be driven by DIGB */
1298 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1299 struct radeon_encoder *radeon_test_encoder;
1301 if (encoder == test_encoder)
1304 if (!radeon_encoder_is_digital(test_encoder))
1307 radeon_test_encoder = to_radeon_encoder(test_encoder);
1308 dig = radeon_test_encoder->enc_priv;
1310 if (dig->dig_encoder >= 0)
1311 dig_enc_in_use |= (1 << dig->dig_encoder);
1314 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1315 if (dig_enc_in_use & 0x2)
1316 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1319 if (!(dig_enc_in_use & 1))
1325 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1326 struct drm_display_mode *mode,
1327 struct drm_display_mode *adjusted_mode)
1329 struct drm_device *dev = encoder->dev;
1330 struct radeon_device *rdev = dev->dev_private;
1331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1333 radeon_encoder->pixel_clock = adjusted_mode->clock;
1335 if (ASIC_IS_AVIVO(rdev)) {
1336 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1337 atombios_yuv_setup(encoder, true);
1339 atombios_yuv_setup(encoder, false);
1342 switch (radeon_encoder->encoder_id) {
1343 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1344 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1345 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1346 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1347 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1349 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1350 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1352 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1353 if (ASIC_IS_DCE4(rdev)) {
1354 /* disable the transmitter */
1355 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1356 /* setup and enable the encoder */
1357 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1359 /* init and enable the transmitter */
1360 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1361 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1363 /* disable the encoder and transmitter */
1364 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1365 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1367 /* setup and enable the encoder and transmitter */
1368 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1369 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1370 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1371 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1374 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1375 atombios_ddia_setup(encoder, ATOM_ENABLE);
1377 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1379 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1381 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1382 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1383 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1385 atombios_dac_setup(encoder, ATOM_ENABLE);
1386 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1387 atombios_tv_setup(encoder, ATOM_ENABLE);
1390 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1392 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1393 r600_hdmi_enable(encoder);
1394 r600_hdmi_setmode(encoder, adjusted_mode);
1399 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1401 struct drm_device *dev = encoder->dev;
1402 struct radeon_device *rdev = dev->dev_private;
1403 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1404 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1406 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1407 ATOM_DEVICE_CV_SUPPORT |
1408 ATOM_DEVICE_CRT_SUPPORT)) {
1409 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1410 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1413 memset(&args, 0, sizeof(args));
1415 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1418 args.sDacload.ucMisc = 0;
1420 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1421 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1422 args.sDacload.ucDacType = ATOM_DAC_A;
1424 args.sDacload.ucDacType = ATOM_DAC_B;
1426 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1427 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1428 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1429 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1430 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1431 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1433 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1434 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1435 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1437 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1440 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1447 static enum drm_connector_status
1448 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1450 struct drm_device *dev = encoder->dev;
1451 struct radeon_device *rdev = dev->dev_private;
1452 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1453 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1454 uint32_t bios_0_scratch;
1456 if (!atombios_dac_load_detect(encoder, connector)) {
1457 DRM_DEBUG("detect returned false \n");
1458 return connector_status_unknown;
1461 if (rdev->family >= CHIP_R600)
1462 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1464 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1466 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1467 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1468 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1469 return connector_status_connected;
1471 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1472 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1473 return connector_status_connected;
1475 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1476 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1477 return connector_status_connected;
1479 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1480 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1481 return connector_status_connected; /* CTV */
1482 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1483 return connector_status_connected; /* STV */
1485 return connector_status_disconnected;
1488 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1490 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1492 if (radeon_encoder->active_device &
1493 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1494 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1496 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1499 radeon_atom_output_lock(encoder, true);
1500 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1502 /* this is needed for the pll/ss setup to work correctly in some cases */
1503 atombios_set_encoder_crtc_source(encoder);
1506 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1508 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1509 radeon_atom_output_lock(encoder, false);
1512 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1514 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1515 struct radeon_encoder_atom_dig *dig;
1516 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1518 if (radeon_encoder_is_digital(encoder)) {
1519 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1520 r600_hdmi_disable(encoder);
1521 dig = radeon_encoder->enc_priv;
1522 dig->dig_encoder = -1;
1524 radeon_encoder->active_device = 0;
1527 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1528 .dpms = radeon_atom_encoder_dpms,
1529 .mode_fixup = radeon_atom_mode_fixup,
1530 .prepare = radeon_atom_encoder_prepare,
1531 .mode_set = radeon_atom_encoder_mode_set,
1532 .commit = radeon_atom_encoder_commit,
1533 .disable = radeon_atom_encoder_disable,
1534 /* no detect for TMDS/LVDS yet */
1537 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1538 .dpms = radeon_atom_encoder_dpms,
1539 .mode_fixup = radeon_atom_mode_fixup,
1540 .prepare = radeon_atom_encoder_prepare,
1541 .mode_set = radeon_atom_encoder_mode_set,
1542 .commit = radeon_atom_encoder_commit,
1543 .detect = radeon_atom_dac_detect,
1546 void radeon_enc_destroy(struct drm_encoder *encoder)
1548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1549 kfree(radeon_encoder->enc_priv);
1550 drm_encoder_cleanup(encoder);
1551 kfree(radeon_encoder);
1554 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1555 .destroy = radeon_enc_destroy,
1558 struct radeon_encoder_atom_dac *
1559 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1561 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1566 dac->tv_std = TV_STD_NTSC;
1570 struct radeon_encoder_atom_dig *
1571 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1573 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1578 /* coherent mode by default */
1579 dig->coherent_mode = true;
1580 dig->dig_encoder = -1;
1586 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1588 struct radeon_device *rdev = dev->dev_private;
1589 struct drm_encoder *encoder;
1590 struct radeon_encoder *radeon_encoder;
1592 /* see if we already added it */
1593 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1594 radeon_encoder = to_radeon_encoder(encoder);
1595 if (radeon_encoder->encoder_id == encoder_id) {
1596 radeon_encoder->devices |= supported_device;
1603 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1604 if (!radeon_encoder)
1607 encoder = &radeon_encoder->base;
1608 switch (rdev->num_crtc) {
1610 encoder->possible_crtcs = 0x1;
1614 encoder->possible_crtcs = 0x3;
1617 encoder->possible_crtcs = 0x3f;
1621 radeon_encoder->enc_priv = NULL;
1623 radeon_encoder->encoder_id = encoder_id;
1624 radeon_encoder->devices = supported_device;
1625 radeon_encoder->rmx_type = RMX_OFF;
1627 switch (radeon_encoder->encoder_id) {
1628 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1629 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1631 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1632 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1633 radeon_encoder->rmx_type = RMX_FULL;
1634 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1635 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1637 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1638 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1640 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1642 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1643 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1644 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1646 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1649 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1650 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1651 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1653 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1655 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1656 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1658 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1659 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1660 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1661 radeon_encoder->rmx_type = RMX_FULL;
1662 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1663 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1666 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1668 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);