2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
160 radeon_link_encoder_connector(struct drm_device *dev)
162 struct drm_connector *connector;
163 struct radeon_connector *radeon_connector;
164 struct drm_encoder *encoder;
165 struct radeon_encoder *radeon_encoder;
167 /* walk the list and link encoders to connectors */
168 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
169 radeon_connector = to_radeon_connector(connector);
170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
171 radeon_encoder = to_radeon_encoder(encoder);
172 if (radeon_encoder->devices & radeon_connector->devices)
173 drm_mode_connector_attach_encoder(connector, encoder);
178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
180 struct drm_device *dev = encoder->dev;
181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
182 struct drm_connector *connector;
184 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
185 if (connector->encoder == encoder) {
186 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
187 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
188 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
189 radeon_encoder->active_device, radeon_encoder->devices,
190 radeon_connector->devices, encoder->encoder_type);
195 static struct drm_connector *
196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
198 struct drm_device *dev = encoder->dev;
199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
200 struct drm_connector *connector;
201 struct radeon_connector *radeon_connector;
203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
204 radeon_connector = to_radeon_connector(connector);
205 if (radeon_encoder->devices & radeon_connector->devices)
211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
212 struct drm_display_mode *mode,
213 struct drm_display_mode *adjusted_mode)
215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
216 struct drm_device *dev = encoder->dev;
217 struct radeon_device *rdev = dev->dev_private;
219 /* set the active encoder to connector routing */
220 radeon_encoder_set_active_device(encoder);
221 drm_mode_set_crtcinfo(adjusted_mode, 0);
224 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
225 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
226 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
228 /* get the native mode for LVDS */
229 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
230 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
231 int mode_id = adjusted_mode->base.id;
232 *adjusted_mode = *native_mode;
233 if (!ASIC_IS_AVIVO(rdev)) {
234 adjusted_mode->hdisplay = mode->hdisplay;
235 adjusted_mode->vdisplay = mode->vdisplay;
237 adjusted_mode->base.id = mode_id;
240 /* get the native mode for TV */
241 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
242 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
244 if (tv_dac->tv_std == TV_STD_NTSC ||
245 tv_dac->tv_std == TV_STD_NTSC_J ||
246 tv_dac->tv_std == TV_STD_PAL_M)
247 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
249 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
253 if (ASIC_IS_DCE3(rdev) &&
254 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
255 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
256 radeon_dp_set_link_config(connector, mode);
263 atombios_dac_setup(struct drm_encoder *encoder, int action)
265 struct drm_device *dev = encoder->dev;
266 struct radeon_device *rdev = dev->dev_private;
267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
268 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
269 int index = 0, num = 0;
270 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
271 enum radeon_tv_std tv_std = TV_STD_NTSC;
273 if (dac_info->tv_std)
274 tv_std = dac_info->tv_std;
276 memset(&args, 0, sizeof(args));
278 switch (radeon_encoder->encoder_id) {
279 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
281 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
284 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
286 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
291 args.ucAction = action;
293 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
294 args.ucDacStandard = ATOM_DAC1_PS2;
295 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
296 args.ucDacStandard = ATOM_DAC1_CV;
301 case TV_STD_SCART_PAL:
304 args.ucDacStandard = ATOM_DAC1_PAL;
310 args.ucDacStandard = ATOM_DAC1_NTSC;
314 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
321 atombios_tv_setup(struct drm_encoder *encoder, int action)
323 struct drm_device *dev = encoder->dev;
324 struct radeon_device *rdev = dev->dev_private;
325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
326 TV_ENCODER_CONTROL_PS_ALLOCATION args;
328 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
329 enum radeon_tv_std tv_std = TV_STD_NTSC;
331 if (dac_info->tv_std)
332 tv_std = dac_info->tv_std;
334 memset(&args, 0, sizeof(args));
336 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
338 args.sTVEncoder.ucAction = action;
340 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
341 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
345 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
348 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
351 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
354 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
357 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
359 case TV_STD_SCART_PAL:
360 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
363 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
366 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
369 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
374 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
376 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
381 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
383 struct drm_device *dev = encoder->dev;
384 struct radeon_device *rdev = dev->dev_private;
385 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
386 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
389 memset(&args, 0, sizeof(args));
391 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
393 args.sXTmdsEncoder.ucEnable = action;
395 if (radeon_encoder->pixel_clock > 165000)
396 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
398 /*if (pScrn->rgbBits == 8)*/
399 args.sXTmdsEncoder.ucMisc |= (1 << 1);
401 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406 atombios_ddia_setup(struct drm_encoder *encoder, int action)
408 struct drm_device *dev = encoder->dev;
409 struct radeon_device *rdev = dev->dev_private;
410 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
411 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
414 memset(&args, 0, sizeof(args));
416 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
418 args.sDVOEncoder.ucAction = action;
419 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
421 if (radeon_encoder->pixel_clock > 165000)
422 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
424 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428 union lvds_encoder_control {
429 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
430 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
434 atombios_digital_setup(struct drm_encoder *encoder, int action)
436 struct drm_device *dev = encoder->dev;
437 struct radeon_device *rdev = dev->dev_private;
438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
439 union lvds_encoder_control args;
442 struct radeon_encoder_atom_dig *dig;
443 struct drm_connector *connector;
444 struct radeon_connector *radeon_connector;
445 struct radeon_connector_atom_dig *dig_connector;
447 connector = radeon_get_connector_for_encoder(encoder);
451 radeon_connector = to_radeon_connector(connector);
453 if (!radeon_encoder->enc_priv)
456 dig = radeon_encoder->enc_priv;
458 if (!radeon_connector->con_priv)
461 dig_connector = radeon_connector->con_priv;
463 memset(&args, 0, sizeof(args));
465 switch (radeon_encoder->encoder_id) {
466 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
467 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
469 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
470 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
471 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
473 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
474 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
475 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
477 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
481 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
489 args.v1.ucAction = action;
490 if (drm_detect_hdmi_monitor(radeon_connector->edid))
491 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
492 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
493 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
494 if (dig->lvds_misc & (1 << 0))
495 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
496 if (dig->lvds_misc & (1 << 1))
497 args.v1.ucMisc |= (1 << 1);
499 if (dig_connector->linkb)
500 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
501 if (radeon_encoder->pixel_clock > 165000)
502 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
503 /*if (pScrn->rgbBits == 8) */
504 args.v1.ucMisc |= (1 << 1);
510 args.v2.ucAction = action;
512 if (dig->coherent_mode)
513 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
515 if (drm_detect_hdmi_monitor(radeon_connector->edid))
516 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
517 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
518 args.v2.ucTruncate = 0;
519 args.v2.ucSpatial = 0;
520 args.v2.ucTemporal = 0;
522 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
523 if (dig->lvds_misc & (1 << 0))
524 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525 if (dig->lvds_misc & (1 << 5)) {
526 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
527 if (dig->lvds_misc & (1 << 1))
528 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
530 if (dig->lvds_misc & (1 << 6)) {
531 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
532 if (dig->lvds_misc & (1 << 1))
533 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
534 if (((dig->lvds_misc >> 2) & 0x3) == 2)
535 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
538 if (dig_connector->linkb)
539 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
540 if (radeon_encoder->pixel_clock > 165000)
541 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
545 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
550 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
554 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
559 atombios_get_encoder_mode(struct drm_encoder *encoder)
561 struct drm_connector *connector;
562 struct radeon_connector *radeon_connector;
563 struct radeon_connector_atom_dig *radeon_dig_connector;
565 connector = radeon_get_connector_for_encoder(encoder);
569 radeon_connector = to_radeon_connector(connector);
571 switch (connector->connector_type) {
572 case DRM_MODE_CONNECTOR_DVII:
573 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
574 if (drm_detect_hdmi_monitor(radeon_connector->edid))
575 return ATOM_ENCODER_MODE_HDMI;
576 else if (radeon_connector->use_digital)
577 return ATOM_ENCODER_MODE_DVI;
579 return ATOM_ENCODER_MODE_CRT;
581 case DRM_MODE_CONNECTOR_DVID:
582 case DRM_MODE_CONNECTOR_HDMIA:
584 if (drm_detect_hdmi_monitor(radeon_connector->edid))
585 return ATOM_ENCODER_MODE_HDMI;
587 return ATOM_ENCODER_MODE_DVI;
589 case DRM_MODE_CONNECTOR_LVDS:
590 return ATOM_ENCODER_MODE_LVDS;
592 case DRM_MODE_CONNECTOR_DisplayPort:
593 radeon_dig_connector = radeon_connector->con_priv;
594 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
595 return ATOM_ENCODER_MODE_DP;
596 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
597 return ATOM_ENCODER_MODE_HDMI;
599 return ATOM_ENCODER_MODE_DVI;
601 case CONNECTOR_DVI_A:
603 return ATOM_ENCODER_MODE_CRT;
609 return ATOM_ENCODER_MODE_TV;
610 /*return ATOM_ENCODER_MODE_CV;*/
616 * DIG Encoder/Transmitter Setup
619 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
620 * Supports up to 3 digital outputs
621 * - 2 DIG encoder blocks.
622 * DIG1 can drive UNIPHY link A or link B
623 * DIG2 can drive UNIPHY link B or LVTMA
626 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
627 * Supports up to 5 digital outputs
628 * - 2 DIG encoder blocks.
629 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
632 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
634 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
635 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
636 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
637 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
640 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
642 struct drm_device *dev = encoder->dev;
643 struct radeon_device *rdev = dev->dev_private;
644 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
645 DIG_ENCODER_CONTROL_PS_ALLOCATION args;
646 int index = 0, num = 0;
648 struct radeon_encoder_atom_dig *dig;
649 struct drm_connector *connector;
650 struct radeon_connector *radeon_connector;
651 struct radeon_connector_atom_dig *dig_connector;
653 connector = radeon_get_connector_for_encoder(encoder);
657 radeon_connector = to_radeon_connector(connector);
659 if (!radeon_connector->con_priv)
662 dig_connector = radeon_connector->con_priv;
664 if (!radeon_encoder->enc_priv)
667 dig = radeon_encoder->enc_priv;
669 memset(&args, 0, sizeof(args));
671 if (ASIC_IS_DCE32(rdev)) {
673 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
675 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
676 num = dig->dig_block + 1;
678 switch (radeon_encoder->encoder_id) {
679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
680 /* XXX doesn't really matter which dig encoder we pick as long as it's
683 if (dig_connector->linkb)
684 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
686 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
689 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
690 /* Only dig2 encoder can drive LVTMA */
691 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
697 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
699 args.ucAction = action;
700 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
702 if (ASIC_IS_DCE32(rdev)) {
703 switch (radeon_encoder->encoder_id) {
704 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
705 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
707 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
708 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
710 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
711 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
715 switch (radeon_encoder->encoder_id) {
716 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
717 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
719 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
720 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
725 args.ucEncoderMode = atombios_get_encoder_mode(encoder);
727 if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
728 if (dig_connector->dp_clock == 270000)
729 args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
730 args.ucLaneNum = dig_connector->dp_lane_count;
731 } else if (radeon_encoder->pixel_clock > 165000)
736 if (dig_connector->linkb)
737 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
739 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
741 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
745 union dig_transmitter_control {
746 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
747 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
751 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
753 struct drm_device *dev = encoder->dev;
754 struct radeon_device *rdev = dev->dev_private;
755 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
756 union dig_transmitter_control args;
757 int index = 0, num = 0;
759 struct radeon_encoder_atom_dig *dig;
760 struct drm_connector *connector;
761 struct radeon_connector *radeon_connector;
762 struct radeon_connector_atom_dig *dig_connector;
765 connector = radeon_get_connector_for_encoder(encoder);
769 radeon_connector = to_radeon_connector(connector);
771 if (!radeon_encoder->enc_priv)
774 dig = radeon_encoder->enc_priv;
776 if (!radeon_connector->con_priv)
779 dig_connector = radeon_connector->con_priv;
781 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
784 memset(&args, 0, sizeof(args));
786 if (ASIC_IS_DCE32(rdev))
787 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
789 switch (radeon_encoder->encoder_id) {
790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
791 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
794 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
799 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
801 args.v1.ucAction = action;
802 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
803 args.v1.usInitInfo = radeon_connector->connector_object_id;
804 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
805 args.v1.asMode.ucLaneSel = lane_num;
806 args.v1.asMode.ucLaneSet = lane_set;
809 args.v1.usPixelClock =
810 cpu_to_le16(dig_connector->dp_clock / 10);
811 else if (radeon_encoder->pixel_clock > 165000)
812 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
814 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
816 if (ASIC_IS_DCE32(rdev)) {
818 args.v2.acConfig.ucEncoderSel = 1;
819 if (dig_connector->linkb)
820 args.v2.acConfig.ucLinkSel = 1;
822 switch (radeon_encoder->encoder_id) {
823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
824 args.v2.acConfig.ucTransmitterSel = 0;
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
828 args.v2.acConfig.ucTransmitterSel = 1;
831 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
832 args.v2.acConfig.ucTransmitterSel = 2;
838 args.v2.acConfig.fCoherentMode = 1;
839 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
840 if (dig->coherent_mode)
841 args.v2.acConfig.fCoherentMode = 1;
844 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
846 switch (radeon_encoder->encoder_id) {
847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
848 /* XXX doesn't really matter which dig encoder we pick as long as it's
851 if (dig_connector->linkb)
852 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
854 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
855 if (rdev->flags & RADEON_IS_IGP) {
856 if (radeon_encoder->pixel_clock > 165000) {
857 if (dig_connector->igp_lane_info & 0x3)
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
859 else if (dig_connector->igp_lane_info & 0xc)
860 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
862 if (dig_connector->igp_lane_info & 0x1)
863 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
864 else if (dig_connector->igp_lane_info & 0x2)
865 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
866 else if (dig_connector->igp_lane_info & 0x4)
867 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
868 else if (dig_connector->igp_lane_info & 0x8)
869 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
873 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
874 /* Only dig2 encoder can drive LVTMA */
875 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
879 if (radeon_encoder->pixel_clock > 165000)
880 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
882 if (dig_connector->linkb)
883 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
885 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
888 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
889 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
890 if (dig->coherent_mode)
891 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
895 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
900 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
902 struct drm_device *dev = encoder->dev;
903 struct radeon_device *rdev = dev->dev_private;
904 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
905 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
906 ENABLE_YUV_PS_ALLOCATION args;
907 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
910 memset(&args, 0, sizeof(args));
912 if (rdev->family >= CHIP_R600)
913 reg = R600_BIOS_3_SCRATCH;
915 reg = RADEON_BIOS_3_SCRATCH;
917 /* XXX: fix up scratch reg handling */
919 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
920 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
921 (radeon_crtc->crtc_id << 18)));
922 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
923 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
928 args.ucEnable = ATOM_ENABLE;
929 args.ucCRTC = radeon_crtc->crtc_id;
931 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
937 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
939 struct drm_device *dev = encoder->dev;
940 struct radeon_device *rdev = dev->dev_private;
941 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
942 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
946 memset(&args, 0, sizeof(args));
948 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
949 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
950 radeon_encoder->active_device);
951 switch (radeon_encoder->encoder_id) {
952 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
953 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
954 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
956 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
957 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
958 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
959 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
962 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
963 case ENCODER_OBJECT_ID_INTERNAL_DDI:
964 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
965 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
967 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
968 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
970 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
971 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
972 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
974 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
976 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
977 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
978 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
979 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
980 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
981 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
983 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
985 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
986 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
987 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
988 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
989 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
990 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
992 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
998 case DRM_MODE_DPMS_ON:
999 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1001 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1002 dp_link_train(encoder, connector);
1005 case DRM_MODE_DPMS_STANDBY:
1006 case DRM_MODE_DPMS_SUSPEND:
1007 case DRM_MODE_DPMS_OFF:
1008 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1013 case DRM_MODE_DPMS_ON:
1014 args.ucAction = ATOM_ENABLE;
1016 case DRM_MODE_DPMS_STANDBY:
1017 case DRM_MODE_DPMS_SUSPEND:
1018 case DRM_MODE_DPMS_OFF:
1019 args.ucAction = ATOM_DISABLE;
1022 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1024 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1027 union crtc_sourc_param {
1028 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1029 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1033 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1035 struct drm_device *dev = encoder->dev;
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1038 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1039 union crtc_sourc_param args;
1040 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1043 memset(&args, 0, sizeof(args));
1045 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1052 if (ASIC_IS_AVIVO(rdev))
1053 args.v1.ucCRTC = radeon_crtc->crtc_id;
1055 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1056 args.v1.ucCRTC = radeon_crtc->crtc_id;
1058 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1061 switch (radeon_encoder->encoder_id) {
1062 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1063 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1064 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1066 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1067 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1068 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1069 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1071 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1073 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1074 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1075 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1076 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1078 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1079 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1080 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1081 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1082 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1083 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1085 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1087 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1088 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1089 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1090 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1091 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1092 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1094 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1099 args.v2.ucCRTC = radeon_crtc->crtc_id;
1100 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1101 switch (radeon_encoder->encoder_id) {
1102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1105 if (ASIC_IS_DCE32(rdev)) {
1106 if (radeon_crtc->crtc_id)
1107 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1109 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1111 struct drm_connector *connector;
1112 struct radeon_connector *radeon_connector;
1113 struct radeon_connector_atom_dig *dig_connector;
1115 connector = radeon_get_connector_for_encoder(encoder);
1118 radeon_connector = to_radeon_connector(connector);
1119 if (!radeon_connector->con_priv)
1121 dig_connector = radeon_connector->con_priv;
1123 /* XXX doesn't really matter which dig encoder we pick as long as it's
1124 * not already in use
1126 if (dig_connector->linkb)
1127 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1129 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1132 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1133 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1136 /* Only dig2 encoder can drive LVTMA */
1137 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1139 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1140 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1141 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1142 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1143 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1145 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1147 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1148 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1149 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1150 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1151 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1153 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1160 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1164 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1169 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1170 struct drm_display_mode *mode)
1172 struct drm_device *dev = encoder->dev;
1173 struct radeon_device *rdev = dev->dev_private;
1174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1175 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1177 /* Funky macbooks */
1178 if ((dev->pdev->device == 0x71C5) &&
1179 (dev->pdev->subsystem_vendor == 0x106b) &&
1180 (dev->pdev->subsystem_device == 0x0080)) {
1181 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1182 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1184 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1185 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1187 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1191 /* set scaler clears this on some chips */
1192 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1193 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1194 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1195 AVIVO_D1MODE_INTERLEAVE_EN);
1200 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1201 struct drm_display_mode *mode,
1202 struct drm_display_mode *adjusted_mode)
1204 struct drm_device *dev = encoder->dev;
1205 struct radeon_device *rdev = dev->dev_private;
1206 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1207 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1209 if (radeon_encoder->active_device &
1210 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1211 if (radeon_encoder->enc_priv) {
1212 struct radeon_encoder_atom_dig *dig;
1214 dig = radeon_encoder->enc_priv;
1215 dig->dig_block = radeon_crtc->crtc_id;
1218 radeon_encoder->pixel_clock = adjusted_mode->clock;
1220 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1221 atombios_set_encoder_crtc_source(encoder);
1223 if (ASIC_IS_AVIVO(rdev)) {
1224 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1225 atombios_yuv_setup(encoder, true);
1227 atombios_yuv_setup(encoder, false);
1230 switch (radeon_encoder->encoder_id) {
1231 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1232 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1233 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1234 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1235 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1237 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1240 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1241 /* disable the encoder and transmitter */
1242 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1243 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1245 /* setup and enable the encoder and transmitter */
1246 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1247 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1248 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1249 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1251 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1252 atombios_ddia_setup(encoder, ATOM_ENABLE);
1254 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1255 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1256 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1258 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1259 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1260 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1261 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1262 atombios_dac_setup(encoder, ATOM_ENABLE);
1263 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1264 atombios_tv_setup(encoder, ATOM_ENABLE);
1267 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1271 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1273 struct drm_device *dev = encoder->dev;
1274 struct radeon_device *rdev = dev->dev_private;
1275 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1276 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1278 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1279 ATOM_DEVICE_CV_SUPPORT |
1280 ATOM_DEVICE_CRT_SUPPORT)) {
1281 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1282 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1285 memset(&args, 0, sizeof(args));
1287 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1289 args.sDacload.ucMisc = 0;
1291 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1292 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1293 args.sDacload.ucDacType = ATOM_DAC_A;
1295 args.sDacload.ucDacType = ATOM_DAC_B;
1297 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1298 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1299 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1300 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1301 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1302 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1304 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1305 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1306 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1308 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1318 static enum drm_connector_status
1319 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1321 struct drm_device *dev = encoder->dev;
1322 struct radeon_device *rdev = dev->dev_private;
1323 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1324 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1325 uint32_t bios_0_scratch;
1327 if (!atombios_dac_load_detect(encoder, connector)) {
1328 DRM_DEBUG("detect returned false \n");
1329 return connector_status_unknown;
1332 if (rdev->family >= CHIP_R600)
1333 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1335 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1337 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1338 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1339 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1340 return connector_status_connected;
1342 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1343 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1344 return connector_status_connected;
1346 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1347 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1348 return connector_status_connected;
1350 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1351 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1352 return connector_status_connected; /* CTV */
1353 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1354 return connector_status_connected; /* STV */
1356 return connector_status_disconnected;
1359 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1361 radeon_atom_output_lock(encoder, true);
1362 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1365 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1367 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1368 radeon_atom_output_lock(encoder, false);
1371 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1373 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1374 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1375 radeon_encoder->active_device = 0;
1378 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1379 .dpms = radeon_atom_encoder_dpms,
1380 .mode_fixup = radeon_atom_mode_fixup,
1381 .prepare = radeon_atom_encoder_prepare,
1382 .mode_set = radeon_atom_encoder_mode_set,
1383 .commit = radeon_atom_encoder_commit,
1384 .disable = radeon_atom_encoder_disable,
1385 /* no detect for TMDS/LVDS yet */
1388 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1389 .dpms = radeon_atom_encoder_dpms,
1390 .mode_fixup = radeon_atom_mode_fixup,
1391 .prepare = radeon_atom_encoder_prepare,
1392 .mode_set = radeon_atom_encoder_mode_set,
1393 .commit = radeon_atom_encoder_commit,
1394 .detect = radeon_atom_dac_detect,
1397 void radeon_enc_destroy(struct drm_encoder *encoder)
1399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1400 kfree(radeon_encoder->enc_priv);
1401 drm_encoder_cleanup(encoder);
1402 kfree(radeon_encoder);
1405 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1406 .destroy = radeon_enc_destroy,
1409 struct radeon_encoder_atom_dac *
1410 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1412 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1417 dac->tv_std = TV_STD_NTSC;
1421 struct radeon_encoder_atom_dig *
1422 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1424 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1429 /* coherent mode by default */
1430 dig->coherent_mode = true;
1436 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1438 struct radeon_device *rdev = dev->dev_private;
1439 struct drm_encoder *encoder;
1440 struct radeon_encoder *radeon_encoder;
1442 /* see if we already added it */
1443 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1444 radeon_encoder = to_radeon_encoder(encoder);
1445 if (radeon_encoder->encoder_id == encoder_id) {
1446 radeon_encoder->devices |= supported_device;
1453 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1454 if (!radeon_encoder)
1457 encoder = &radeon_encoder->base;
1458 if (rdev->flags & RADEON_SINGLE_CRTC)
1459 encoder->possible_crtcs = 0x1;
1461 encoder->possible_crtcs = 0x3;
1463 radeon_encoder->enc_priv = NULL;
1465 radeon_encoder->encoder_id = encoder_id;
1466 radeon_encoder->devices = supported_device;
1467 radeon_encoder->rmx_type = RMX_OFF;
1469 switch (radeon_encoder->encoder_id) {
1470 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1471 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1472 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1473 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1474 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1475 radeon_encoder->rmx_type = RMX_FULL;
1476 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1477 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1479 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1480 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1482 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1484 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1485 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1486 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1488 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1489 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1490 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1491 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1492 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1493 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1495 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1496 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1497 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1498 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1500 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1501 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1502 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1503 radeon_encoder->rmx_type = RMX_FULL;
1504 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1505 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1507 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1508 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1510 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);