2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
39 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
41 struct radeon_device *rdev = dev->dev_private;
44 switch (supported_device) {
45 case ATOM_DEVICE_CRT1_SUPPORT:
46 case ATOM_DEVICE_TV1_SUPPORT:
47 case ATOM_DEVICE_TV2_SUPPORT:
48 case ATOM_DEVICE_CRT2_SUPPORT:
49 case ATOM_DEVICE_CV_SUPPORT:
52 if ((rdev->family == CHIP_RS300) ||
53 (rdev->family == CHIP_RS400) ||
54 (rdev->family == CHIP_RS480))
55 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
56 else if (ASIC_IS_AVIVO(rdev))
57 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
59 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
62 if (ASIC_IS_AVIVO(rdev))
63 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
65 /*if (rdev->family == CHIP_R200)
66 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
68 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
71 case 3: /* external dac */
72 if (ASIC_IS_AVIVO(rdev))
73 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
75 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
79 case ATOM_DEVICE_LCD1_SUPPORT:
80 if (ASIC_IS_AVIVO(rdev))
81 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
83 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
85 case ATOM_DEVICE_DFP1_SUPPORT:
86 if ((rdev->family == CHIP_RS300) ||
87 (rdev->family == CHIP_RS400) ||
88 (rdev->family == CHIP_RS480))
89 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
90 else if (ASIC_IS_AVIVO(rdev))
91 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
93 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
95 case ATOM_DEVICE_LCD2_SUPPORT:
96 case ATOM_DEVICE_DFP2_SUPPORT:
97 if ((rdev->family == CHIP_RS600) ||
98 (rdev->family == CHIP_RS690) ||
99 (rdev->family == CHIP_RS740))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
106 case ATOM_DEVICE_DFP3_SUPPORT:
107 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
115 radeon_link_encoder_connector(struct drm_device *dev)
117 struct drm_connector *connector;
118 struct radeon_connector *radeon_connector;
119 struct drm_encoder *encoder;
120 struct radeon_encoder *radeon_encoder;
122 /* walk the list and link encoders to connectors */
123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
124 radeon_connector = to_radeon_connector(connector);
125 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
126 radeon_encoder = to_radeon_encoder(encoder);
127 if (radeon_encoder->devices & radeon_connector->devices)
128 drm_mode_connector_attach_encoder(connector, encoder);
133 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
135 struct drm_device *dev = encoder->dev;
136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
137 struct drm_connector *connector;
139 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
140 if (connector->encoder == encoder) {
141 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
142 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
143 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
144 radeon_encoder->active_device, radeon_encoder->devices,
145 radeon_connector->devices, encoder->encoder_type);
150 static struct drm_connector *
151 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
153 struct drm_device *dev = encoder->dev;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct drm_connector *connector;
156 struct radeon_connector *radeon_connector;
158 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
159 radeon_connector = to_radeon_connector(connector);
160 if (radeon_encoder->devices & radeon_connector->devices)
166 /* used for both atom and legacy */
167 void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
168 struct drm_display_mode *mode,
169 struct drm_display_mode *adjusted_mode)
171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
172 struct drm_device *dev = encoder->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
176 if (mode->hdisplay < native_mode->hdisplay ||
177 mode->vdisplay < native_mode->vdisplay) {
178 int mode_id = adjusted_mode->base.id;
179 *adjusted_mode = *native_mode;
180 if (!ASIC_IS_AVIVO(rdev)) {
181 adjusted_mode->hdisplay = mode->hdisplay;
182 adjusted_mode->vdisplay = mode->vdisplay;
184 adjusted_mode->base.id = mode_id;
189 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
190 struct drm_display_mode *mode,
191 struct drm_display_mode *adjusted_mode)
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct drm_device *dev = encoder->dev;
195 struct radeon_device *rdev = dev->dev_private;
197 /* set the active encoder to connector routing */
198 radeon_encoder_set_active_device(encoder);
199 drm_mode_set_crtcinfo(adjusted_mode, 0);
201 if (radeon_encoder->rmx_type != RMX_OFF)
202 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
205 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
206 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
207 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
209 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
210 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
212 if (tv_dac->tv_std == TV_STD_NTSC ||
213 tv_dac->tv_std == TV_STD_NTSC_J ||
214 tv_dac->tv_std == TV_STD_PAL_M)
215 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
217 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
225 atombios_dac_setup(struct drm_encoder *encoder, int action)
227 struct drm_device *dev = encoder->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
230 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
231 int index = 0, num = 0;
232 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
233 enum radeon_tv_std tv_std = TV_STD_NTSC;
235 if (dac_info->tv_std)
236 tv_std = dac_info->tv_std;
238 memset(&args, 0, sizeof(args));
240 switch (radeon_encoder->encoder_id) {
241 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
242 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
243 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
246 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
247 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
248 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
253 args.ucAction = action;
255 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
256 args.ucDacStandard = ATOM_DAC1_PS2;
257 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
258 args.ucDacStandard = ATOM_DAC1_CV;
263 case TV_STD_SCART_PAL:
266 args.ucDacStandard = ATOM_DAC1_PAL;
272 args.ucDacStandard = ATOM_DAC1_NTSC;
276 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
278 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
283 atombios_tv_setup(struct drm_encoder *encoder, int action)
285 struct drm_device *dev = encoder->dev;
286 struct radeon_device *rdev = dev->dev_private;
287 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
288 TV_ENCODER_CONTROL_PS_ALLOCATION args;
290 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
291 enum radeon_tv_std tv_std = TV_STD_NTSC;
293 if (dac_info->tv_std)
294 tv_std = dac_info->tv_std;
296 memset(&args, 0, sizeof(args));
298 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
300 args.sTVEncoder.ucAction = action;
302 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
303 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
307 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
310 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
313 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
316 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
319 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
321 case TV_STD_SCART_PAL:
322 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
325 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
328 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
331 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
336 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
338 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
343 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
345 struct drm_device *dev = encoder->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
348 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
351 memset(&args, 0, sizeof(args));
353 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
355 args.sXTmdsEncoder.ucEnable = action;
357 if (radeon_encoder->pixel_clock > 165000)
358 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
360 /*if (pScrn->rgbBits == 8)*/
361 args.sXTmdsEncoder.ucMisc |= (1 << 1);
363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
368 atombios_ddia_setup(struct drm_encoder *encoder, int action)
370 struct drm_device *dev = encoder->dev;
371 struct radeon_device *rdev = dev->dev_private;
372 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
373 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
376 memset(&args, 0, sizeof(args));
378 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
380 args.sDVOEncoder.ucAction = action;
381 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
383 if (radeon_encoder->pixel_clock > 165000)
384 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
386 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
390 union lvds_encoder_control {
391 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
392 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
396 atombios_digital_setup(struct drm_encoder *encoder, int action)
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 union lvds_encoder_control args;
404 struct radeon_encoder_atom_dig *dig;
405 struct drm_connector *connector;
406 struct radeon_connector *radeon_connector;
407 struct radeon_connector_atom_dig *dig_connector;
409 connector = radeon_get_connector_for_encoder(encoder);
413 radeon_connector = to_radeon_connector(connector);
415 if (!radeon_encoder->enc_priv)
418 dig = radeon_encoder->enc_priv;
420 if (!radeon_connector->con_priv)
423 dig_connector = radeon_connector->con_priv;
425 memset(&args, 0, sizeof(args));
427 switch (radeon_encoder->encoder_id) {
428 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
429 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
431 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
432 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
433 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
435 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
436 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
437 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
439 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
443 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
451 args.v1.ucAction = action;
452 if (drm_detect_hdmi_monitor(radeon_connector->edid))
453 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
454 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
455 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
456 if (dig->lvds_misc & (1 << 0))
457 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
458 if (dig->lvds_misc & (1 << 1))
459 args.v1.ucMisc |= (1 << 1);
461 if (dig_connector->linkb)
462 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
463 if (radeon_encoder->pixel_clock > 165000)
464 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
465 /*if (pScrn->rgbBits == 8) */
466 args.v1.ucMisc |= (1 << 1);
472 args.v2.ucAction = action;
474 if (dig->coherent_mode)
475 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
477 if (drm_detect_hdmi_monitor(radeon_connector->edid))
478 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
479 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
480 args.v2.ucTruncate = 0;
481 args.v2.ucSpatial = 0;
482 args.v2.ucTemporal = 0;
484 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
485 if (dig->lvds_misc & (1 << 0))
486 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
487 if (dig->lvds_misc & (1 << 5)) {
488 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
489 if (dig->lvds_misc & (1 << 1))
490 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
492 if (dig->lvds_misc & (1 << 6)) {
493 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
494 if (dig->lvds_misc & (1 << 1))
495 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
496 if (((dig->lvds_misc >> 2) & 0x3) == 2)
497 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
500 if (dig_connector->linkb)
501 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
502 if (radeon_encoder->pixel_clock > 165000)
503 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
507 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
512 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
516 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
521 atombios_get_encoder_mode(struct drm_encoder *encoder)
523 struct drm_connector *connector;
524 struct radeon_connector *radeon_connector;
526 connector = radeon_get_connector_for_encoder(encoder);
530 radeon_connector = to_radeon_connector(connector);
532 switch (connector->connector_type) {
533 case DRM_MODE_CONNECTOR_DVII:
534 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
535 if (drm_detect_hdmi_monitor(radeon_connector->edid))
536 return ATOM_ENCODER_MODE_HDMI;
537 else if (radeon_connector->use_digital)
538 return ATOM_ENCODER_MODE_DVI;
540 return ATOM_ENCODER_MODE_CRT;
542 case DRM_MODE_CONNECTOR_DVID:
543 case DRM_MODE_CONNECTOR_HDMIA:
545 if (drm_detect_hdmi_monitor(radeon_connector->edid))
546 return ATOM_ENCODER_MODE_HDMI;
548 return ATOM_ENCODER_MODE_DVI;
550 case DRM_MODE_CONNECTOR_LVDS:
551 return ATOM_ENCODER_MODE_LVDS;
553 case DRM_MODE_CONNECTOR_DisplayPort:
554 /*if (radeon_output->MonType == MT_DP)
555 return ATOM_ENCODER_MODE_DP;
557 if (drm_detect_hdmi_monitor(radeon_connector->edid))
558 return ATOM_ENCODER_MODE_HDMI;
560 return ATOM_ENCODER_MODE_DVI;
562 case CONNECTOR_DVI_A:
564 return ATOM_ENCODER_MODE_CRT;
570 return ATOM_ENCODER_MODE_TV;
571 /*return ATOM_ENCODER_MODE_CV;*/
577 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
579 struct drm_device *dev = encoder->dev;
580 struct radeon_device *rdev = dev->dev_private;
581 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
582 DIG_ENCODER_CONTROL_PS_ALLOCATION args;
583 int index = 0, num = 0;
585 struct radeon_encoder_atom_dig *dig;
586 struct drm_connector *connector;
587 struct radeon_connector *radeon_connector;
588 struct radeon_connector_atom_dig *dig_connector;
590 connector = radeon_get_connector_for_encoder(encoder);
594 radeon_connector = to_radeon_connector(connector);
596 if (!radeon_connector->con_priv)
599 dig_connector = radeon_connector->con_priv;
601 if (!radeon_encoder->enc_priv)
604 dig = radeon_encoder->enc_priv;
606 memset(&args, 0, sizeof(args));
608 if (ASIC_IS_DCE32(rdev)) {
610 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
612 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
613 num = dig->dig_block + 1;
615 switch (radeon_encoder->encoder_id) {
616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
617 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
620 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
621 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
627 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
629 args.ucAction = action;
630 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
632 if (ASIC_IS_DCE32(rdev)) {
633 switch (radeon_encoder->encoder_id) {
634 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
635 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
637 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
638 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
640 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
641 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
645 switch (radeon_encoder->encoder_id) {
646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
647 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
649 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
650 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
655 if (radeon_encoder->pixel_clock > 165000) {
656 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
659 if (dig_connector->linkb)
660 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
662 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
666 args.ucEncoderMode = atombios_get_encoder_mode(encoder);
668 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
672 union dig_transmitter_control {
673 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
674 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
678 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
680 struct drm_device *dev = encoder->dev;
681 struct radeon_device *rdev = dev->dev_private;
682 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
683 union dig_transmitter_control args;
684 int index = 0, num = 0;
686 struct radeon_encoder_atom_dig *dig;
687 struct drm_connector *connector;
688 struct radeon_connector *radeon_connector;
689 struct radeon_connector_atom_dig *dig_connector;
691 connector = radeon_get_connector_for_encoder(encoder);
695 radeon_connector = to_radeon_connector(connector);
697 if (!radeon_encoder->enc_priv)
700 dig = radeon_encoder->enc_priv;
702 if (!radeon_connector->con_priv)
705 dig_connector = radeon_connector->con_priv;
707 memset(&args, 0, sizeof(args));
709 if (ASIC_IS_DCE32(rdev))
710 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
712 switch (radeon_encoder->encoder_id) {
713 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
714 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
716 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
717 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
722 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
724 args.v1.ucAction = action;
725 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
726 args.v1.usInitInfo = radeon_connector->connector_object_id;
728 if (radeon_encoder->pixel_clock > 165000)
729 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
731 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
733 if (ASIC_IS_DCE32(rdev)) {
734 if (radeon_encoder->pixel_clock > 165000)
735 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
737 args.v2.acConfig.ucEncoderSel = 1;
739 switch (radeon_encoder->encoder_id) {
740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
741 args.v2.acConfig.ucTransmitterSel = 0;
744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
745 args.v2.acConfig.ucTransmitterSel = 1;
748 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
749 args.v2.acConfig.ucTransmitterSel = 2;
754 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
755 if (dig->coherent_mode)
756 args.v2.acConfig.fCoherentMode = 1;
759 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
761 switch (radeon_encoder->encoder_id) {
762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
763 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
764 if (rdev->flags & RADEON_IS_IGP) {
765 if (radeon_encoder->pixel_clock > 165000) {
766 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
767 ATOM_TRANSMITTER_CONFIG_LINKA_B);
768 if (dig_connector->igp_lane_info & 0x3)
769 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
770 else if (dig_connector->igp_lane_info & 0xc)
771 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
773 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
774 if (dig_connector->igp_lane_info & 0x1)
775 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
776 else if (dig_connector->igp_lane_info & 0x2)
777 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
778 else if (dig_connector->igp_lane_info & 0x4)
779 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
780 else if (dig_connector->igp_lane_info & 0x8)
781 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
784 if (radeon_encoder->pixel_clock > 165000)
785 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
786 ATOM_TRANSMITTER_CONFIG_LINKA_B |
787 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
789 if (dig_connector->linkb)
790 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
792 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
796 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
797 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
798 if (radeon_encoder->pixel_clock > 165000)
799 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
800 ATOM_TRANSMITTER_CONFIG_LINKA_B |
801 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
803 if (dig_connector->linkb)
804 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
806 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
811 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
812 if (dig->coherent_mode)
813 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
817 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
822 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
824 struct drm_device *dev = encoder->dev;
825 struct radeon_device *rdev = dev->dev_private;
826 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
827 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
828 ENABLE_YUV_PS_ALLOCATION args;
829 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
832 memset(&args, 0, sizeof(args));
834 if (rdev->family >= CHIP_R600)
835 reg = R600_BIOS_3_SCRATCH;
837 reg = RADEON_BIOS_3_SCRATCH;
839 /* XXX: fix up scratch reg handling */
841 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
842 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
843 (radeon_crtc->crtc_id << 18)));
844 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
845 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
850 args.ucEnable = ATOM_ENABLE;
851 args.ucCRTC = radeon_crtc->crtc_id;
853 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
859 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
861 struct drm_device *dev = encoder->dev;
862 struct radeon_device *rdev = dev->dev_private;
863 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
864 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
868 memset(&args, 0, sizeof(args));
870 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
871 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
872 radeon_encoder->active_device);
873 switch (radeon_encoder->encoder_id) {
874 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
876 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
881 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
884 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
885 case ENCODER_OBJECT_ID_INTERNAL_DDI:
886 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
887 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
889 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
890 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
892 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
893 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
894 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
896 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
898 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
899 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
900 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
901 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
902 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
903 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
905 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
907 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
910 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
912 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
914 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
920 case DRM_MODE_DPMS_ON:
921 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
923 case DRM_MODE_DPMS_STANDBY:
924 case DRM_MODE_DPMS_SUSPEND:
925 case DRM_MODE_DPMS_OFF:
926 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
931 case DRM_MODE_DPMS_ON:
932 args.ucAction = ATOM_ENABLE;
934 case DRM_MODE_DPMS_STANDBY:
935 case DRM_MODE_DPMS_SUSPEND:
936 case DRM_MODE_DPMS_OFF:
937 args.ucAction = ATOM_DISABLE;
940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
942 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
945 union crtc_sourc_param {
946 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
947 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
951 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
953 struct drm_device *dev = encoder->dev;
954 struct radeon_device *rdev = dev->dev_private;
955 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
956 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
957 union crtc_sourc_param args;
958 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
961 memset(&args, 0, sizeof(args));
963 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
970 if (ASIC_IS_AVIVO(rdev))
971 args.v1.ucCRTC = radeon_crtc->crtc_id;
973 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
974 args.v1.ucCRTC = radeon_crtc->crtc_id;
976 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
979 switch (radeon_encoder->encoder_id) {
980 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
981 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
982 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
984 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
985 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
986 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
987 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
989 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
991 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
992 case ENCODER_OBJECT_ID_INTERNAL_DDI:
993 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
994 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
996 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
997 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
998 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
999 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1000 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1001 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1003 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1005 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1006 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1007 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1008 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1009 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1010 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1012 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1017 args.v2.ucCRTC = radeon_crtc->crtc_id;
1018 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1019 switch (radeon_encoder->encoder_id) {
1020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1021 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1023 if (ASIC_IS_DCE32(rdev)) {
1024 if (radeon_crtc->crtc_id)
1025 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1027 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1029 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1031 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1032 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1034 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1035 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1038 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1039 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1040 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1041 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1043 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1046 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1047 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1048 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1049 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1051 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1058 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1062 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1067 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1068 struct drm_display_mode *mode)
1070 struct drm_device *dev = encoder->dev;
1071 struct radeon_device *rdev = dev->dev_private;
1072 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1073 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1075 /* Funky macbooks */
1076 if ((dev->pdev->device == 0x71C5) &&
1077 (dev->pdev->subsystem_vendor == 0x106b) &&
1078 (dev->pdev->subsystem_device == 0x0080)) {
1079 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1080 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1082 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1083 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1085 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1089 /* set scaler clears this on some chips */
1090 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1091 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1092 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1093 AVIVO_D1MODE_INTERLEAVE_EN);
1098 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1099 struct drm_display_mode *mode,
1100 struct drm_display_mode *adjusted_mode)
1102 struct drm_device *dev = encoder->dev;
1103 struct radeon_device *rdev = dev->dev_private;
1104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1107 if (radeon_encoder->enc_priv) {
1108 struct radeon_encoder_atom_dig *dig;
1110 dig = radeon_encoder->enc_priv;
1111 dig->dig_block = radeon_crtc->crtc_id;
1113 radeon_encoder->pixel_clock = adjusted_mode->clock;
1115 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1116 atombios_set_encoder_crtc_source(encoder);
1118 if (ASIC_IS_AVIVO(rdev)) {
1119 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1120 atombios_yuv_setup(encoder, true);
1122 atombios_yuv_setup(encoder, false);
1125 switch (radeon_encoder->encoder_id) {
1126 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1128 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1129 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1130 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1136 /* disable the encoder and transmitter */
1137 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
1138 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1140 /* setup and enable the encoder and transmitter */
1141 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1142 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT);
1143 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1144 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1146 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1147 atombios_ddia_setup(encoder, ATOM_ENABLE);
1149 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1150 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1151 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1153 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1154 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1155 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1157 atombios_dac_setup(encoder, ATOM_ENABLE);
1158 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1159 atombios_tv_setup(encoder, ATOM_ENABLE);
1162 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1166 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1168 struct drm_device *dev = encoder->dev;
1169 struct radeon_device *rdev = dev->dev_private;
1170 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1171 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1173 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1174 ATOM_DEVICE_CV_SUPPORT |
1175 ATOM_DEVICE_CRT_SUPPORT)) {
1176 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1177 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1180 memset(&args, 0, sizeof(args));
1182 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1184 args.sDacload.ucMisc = 0;
1186 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1187 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1188 args.sDacload.ucDacType = ATOM_DAC_A;
1190 args.sDacload.ucDacType = ATOM_DAC_B;
1192 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1193 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1194 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1195 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1196 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1197 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1199 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1200 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1201 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1203 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1206 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1213 static enum drm_connector_status
1214 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1216 struct drm_device *dev = encoder->dev;
1217 struct radeon_device *rdev = dev->dev_private;
1218 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1219 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1220 uint32_t bios_0_scratch;
1222 if (!atombios_dac_load_detect(encoder, connector)) {
1223 DRM_DEBUG("detect returned false \n");
1224 return connector_status_unknown;
1227 if (rdev->family >= CHIP_R600)
1228 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1230 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1232 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1233 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1234 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1235 return connector_status_connected;
1237 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1238 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1239 return connector_status_connected;
1241 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1242 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1243 return connector_status_connected;
1245 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1246 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1247 return connector_status_connected; /* CTV */
1248 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1249 return connector_status_connected; /* STV */
1251 return connector_status_disconnected;
1254 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1256 radeon_atom_output_lock(encoder, true);
1257 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1260 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1262 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1263 radeon_atom_output_lock(encoder, false);
1266 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1268 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1269 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1270 radeon_encoder->active_device = 0;
1273 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1274 .dpms = radeon_atom_encoder_dpms,
1275 .mode_fixup = radeon_atom_mode_fixup,
1276 .prepare = radeon_atom_encoder_prepare,
1277 .mode_set = radeon_atom_encoder_mode_set,
1278 .commit = radeon_atom_encoder_commit,
1279 .disable = radeon_atom_encoder_disable,
1280 /* no detect for TMDS/LVDS yet */
1283 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1284 .dpms = radeon_atom_encoder_dpms,
1285 .mode_fixup = radeon_atom_mode_fixup,
1286 .prepare = radeon_atom_encoder_prepare,
1287 .mode_set = radeon_atom_encoder_mode_set,
1288 .commit = radeon_atom_encoder_commit,
1289 .detect = radeon_atom_dac_detect,
1292 void radeon_enc_destroy(struct drm_encoder *encoder)
1294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1295 kfree(radeon_encoder->enc_priv);
1296 drm_encoder_cleanup(encoder);
1297 kfree(radeon_encoder);
1300 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1301 .destroy = radeon_enc_destroy,
1304 struct radeon_encoder_atom_dac *
1305 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1307 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1312 dac->tv_std = TV_STD_NTSC;
1316 struct radeon_encoder_atom_dig *
1317 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1319 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1324 /* coherent mode by default */
1325 dig->coherent_mode = true;
1331 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1333 struct radeon_device *rdev = dev->dev_private;
1334 struct drm_encoder *encoder;
1335 struct radeon_encoder *radeon_encoder;
1337 /* see if we already added it */
1338 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1339 radeon_encoder = to_radeon_encoder(encoder);
1340 if (radeon_encoder->encoder_id == encoder_id) {
1341 radeon_encoder->devices |= supported_device;
1348 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1349 if (!radeon_encoder)
1352 encoder = &radeon_encoder->base;
1353 if (rdev->flags & RADEON_SINGLE_CRTC)
1354 encoder->possible_crtcs = 0x1;
1356 encoder->possible_crtcs = 0x3;
1357 encoder->possible_clones = 0;
1359 radeon_encoder->enc_priv = NULL;
1361 radeon_encoder->encoder_id = encoder_id;
1362 radeon_encoder->devices = supported_device;
1363 radeon_encoder->rmx_type = RMX_OFF;
1365 switch (radeon_encoder->encoder_id) {
1366 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1367 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1369 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1370 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1371 radeon_encoder->rmx_type = RMX_FULL;
1372 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1373 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1375 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1376 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1378 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1380 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1381 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1382 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1384 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1385 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1386 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1387 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1388 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1389 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1391 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1392 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1393 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1395 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1396 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1398 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1399 radeon_encoder->rmx_type = RMX_FULL;
1400 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1401 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1403 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1404 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1406 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);