2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
181 radeon_link_encoder_connector(struct drm_device *dev)
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
239 if (radeon_encoder->is_ext_encoder)
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
253 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
254 struct drm_display_mode *adjusted_mode)
256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
257 struct drm_device *dev = encoder->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
260 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
261 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
262 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
263 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
264 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
265 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
267 adjusted_mode->clock = native_mode->clock;
268 adjusted_mode->flags = native_mode->flags;
270 if (ASIC_IS_AVIVO(rdev)) {
271 adjusted_mode->hdisplay = native_mode->hdisplay;
272 adjusted_mode->vdisplay = native_mode->vdisplay;
275 adjusted_mode->htotal = native_mode->hdisplay + hblank;
276 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
277 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
279 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
280 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
281 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
283 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
285 if (ASIC_IS_AVIVO(rdev)) {
286 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
287 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
290 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
291 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
292 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
294 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
295 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
296 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
301 struct drm_display_mode *mode,
302 struct drm_display_mode *adjusted_mode)
304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305 struct drm_device *dev = encoder->dev;
306 struct radeon_device *rdev = dev->dev_private;
308 /* set the active encoder to connector routing */
309 radeon_encoder_set_active_device(encoder);
310 drm_mode_set_crtcinfo(adjusted_mode, 0);
313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
314 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
315 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
317 /* get the native mode for LVDS */
318 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
319 radeon_panel_mode_fixup(encoder, adjusted_mode);
321 /* get the native mode for TV */
322 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
323 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
325 if (tv_dac->tv_std == TV_STD_NTSC ||
326 tv_dac->tv_std == TV_STD_NTSC_J ||
327 tv_dac->tv_std == TV_STD_PAL_M)
328 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
330 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
334 if (ASIC_IS_DCE3(rdev) &&
335 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337 radeon_dp_set_link_config(connector, mode);
344 atombios_dac_setup(struct drm_encoder *encoder, int action)
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
353 memset(&args, 0, sizeof(args));
355 switch (radeon_encoder->encoder_id) {
356 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
360 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
366 args.ucAction = action;
368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
369 args.ucDacStandard = ATOM_DAC1_PS2;
370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
371 args.ucDacStandard = ATOM_DAC1_CV;
373 switch (dac_info->tv_std) {
376 case TV_STD_SCART_PAL:
379 args.ucDacStandard = ATOM_DAC1_PAL;
385 args.ucDacStandard = ATOM_DAC1_NTSC;
389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
396 atombios_tv_setup(struct drm_encoder *encoder, int action)
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args;
403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
405 memset(&args, 0, sizeof(args));
407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
409 args.sTVEncoder.ucAction = action;
411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
414 switch (dac_info->tv_std) {
416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
430 case TV_STD_SCART_PAL:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
451 union dvo_encoder_control {
452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
458 atombios_dvo_setup(struct drm_encoder *encoder, int action)
460 struct drm_device *dev = encoder->dev;
461 struct radeon_device *rdev = dev->dev_private;
462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
463 union dvo_encoder_control args;
464 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
466 memset(&args, 0, sizeof(args));
468 if (ASIC_IS_DCE3(rdev)) {
470 args.dvo_v3.ucAction = action;
471 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 args.dvo_v3.ucDVOConfig = 0; /* XXX */
473 } else if (ASIC_IS_DCE2(rdev)) {
474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475 args.dvo.sDVOEncoder.ucAction = action;
476 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
477 /* DFP1, CRT1, TV1 depending on the type of port */
478 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
480 if (radeon_encoder->pixel_clock > 165000)
481 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
484 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
486 if (radeon_encoder->pixel_clock > 165000)
487 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
489 /*if (pScrn->rgbBits == 8)*/
490 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
496 union lvds_encoder_control {
497 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
498 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
502 atombios_digital_setup(struct drm_encoder *encoder, int action)
504 struct drm_device *dev = encoder->dev;
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
508 union lvds_encoder_control args;
510 int hdmi_detected = 0;
516 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
519 memset(&args, 0, sizeof(args));
521 switch (radeon_encoder->encoder_id) {
522 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
523 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
527 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
530 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
531 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
533 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
537 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
546 args.v1.ucAction = action;
548 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
549 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
551 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
552 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
553 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
554 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
557 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
558 if (radeon_encoder->pixel_clock > 165000)
559 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
560 /*if (pScrn->rgbBits == 8) */
561 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
567 args.v2.ucAction = action;
569 if (dig->coherent_mode)
570 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
573 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
574 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
575 args.v2.ucTruncate = 0;
576 args.v2.ucSpatial = 0;
577 args.v2.ucTemporal = 0;
579 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
580 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
581 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
582 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
583 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
584 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
585 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
587 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
588 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
591 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
592 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
596 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
597 if (radeon_encoder->pixel_clock > 165000)
598 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
602 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
607 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
611 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
615 atombios_get_encoder_mode(struct drm_encoder *encoder)
617 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
618 struct drm_device *dev = encoder->dev;
619 struct radeon_device *rdev = dev->dev_private;
620 struct drm_connector *connector;
621 struct radeon_connector *radeon_connector;
622 struct radeon_connector_atom_dig *dig_connector;
624 connector = radeon_get_connector_for_encoder(encoder);
626 switch (radeon_encoder->encoder_id) {
627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
632 return ATOM_ENCODER_MODE_DVI;
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
636 return ATOM_ENCODER_MODE_CRT;
639 radeon_connector = to_radeon_connector(connector);
641 switch (connector->connector_type) {
642 case DRM_MODE_CONNECTOR_DVII:
643 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
644 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
646 if (ASIC_IS_DCE4(rdev))
647 return ATOM_ENCODER_MODE_DVI;
649 return ATOM_ENCODER_MODE_HDMI;
650 } else if (radeon_connector->use_digital)
651 return ATOM_ENCODER_MODE_DVI;
653 return ATOM_ENCODER_MODE_CRT;
655 case DRM_MODE_CONNECTOR_DVID:
656 case DRM_MODE_CONNECTOR_HDMIA:
658 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
660 if (ASIC_IS_DCE4(rdev))
661 return ATOM_ENCODER_MODE_DVI;
663 return ATOM_ENCODER_MODE_HDMI;
665 return ATOM_ENCODER_MODE_DVI;
667 case DRM_MODE_CONNECTOR_LVDS:
668 return ATOM_ENCODER_MODE_LVDS;
670 case DRM_MODE_CONNECTOR_DisplayPort:
671 case DRM_MODE_CONNECTOR_eDP:
672 dig_connector = radeon_connector->con_priv;
673 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
674 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
675 return ATOM_ENCODER_MODE_DP;
676 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
678 if (ASIC_IS_DCE4(rdev))
679 return ATOM_ENCODER_MODE_DVI;
681 return ATOM_ENCODER_MODE_HDMI;
683 return ATOM_ENCODER_MODE_DVI;
685 case DRM_MODE_CONNECTOR_DVIA:
686 case DRM_MODE_CONNECTOR_VGA:
687 return ATOM_ENCODER_MODE_CRT;
689 case DRM_MODE_CONNECTOR_Composite:
690 case DRM_MODE_CONNECTOR_SVIDEO:
691 case DRM_MODE_CONNECTOR_9PinDIN:
693 return ATOM_ENCODER_MODE_TV;
694 /*return ATOM_ENCODER_MODE_CV;*/
700 * DIG Encoder/Transmitter Setup
703 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
704 * Supports up to 3 digital outputs
705 * - 2 DIG encoder blocks.
706 * DIG1 can drive UNIPHY link A or link B
707 * DIG2 can drive UNIPHY link B or LVTMA
710 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
711 * Supports up to 5 digital outputs
712 * - 2 DIG encoder blocks.
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks.
719 * - DIG to PHY mapping is hardcoded
720 * DIG1 drives UNIPHY0 link A, A+B
721 * DIG2 drives UNIPHY0 link B
722 * DIG3 drives UNIPHY1 link A, A+B
723 * DIG4 drives UNIPHY1 link B
724 * DIG5 drives UNIPHY2 link A, A+B
725 * DIG6 drives UNIPHY2 link B
728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
729 * Supports up to 6 digital outputs
730 * - 2 DIG encoder blocks.
731 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
734 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
736 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
737 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
738 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
739 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
742 union dig_encoder_control {
743 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
744 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
745 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
746 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
750 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
752 struct drm_device *dev = encoder->dev;
753 struct radeon_device *rdev = dev->dev_private;
754 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
755 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
756 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
757 union dig_encoder_control args;
761 int dp_lane_count = 0;
762 int hpd_id = RADEON_HPD_NONE;
765 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
766 struct radeon_connector_atom_dig *dig_connector =
767 radeon_connector->con_priv;
769 dp_clock = dig_connector->dp_clock;
770 dp_lane_count = dig_connector->dp_lane_count;
771 hpd_id = radeon_connector->hpd.hpd;
774 /* no dig encoder assigned */
775 if (dig->dig_encoder == -1)
778 memset(&args, 0, sizeof(args));
780 if (ASIC_IS_DCE4(rdev))
781 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
783 if (dig->dig_encoder)
784 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
786 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
789 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
792 args.v1.ucAction = action;
793 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
794 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
796 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
797 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
798 args.v1.ucLaneNum = dp_lane_count;
799 else if (radeon_encoder->pixel_clock > 165000)
800 args.v1.ucLaneNum = 8;
802 args.v1.ucLaneNum = 4;
804 if (ASIC_IS_DCE5(rdev)) {
805 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
806 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
807 if (dp_clock == 270000)
808 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
809 else if (dp_clock == 540000)
810 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
812 args.v4.acConfig.ucDigSel = dig->dig_encoder;
813 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
814 if (hpd_id == RADEON_HPD_NONE)
815 args.v4.ucHPD_ID = 0;
817 args.v4.ucHPD_ID = hpd_id + 1;
818 } else if (ASIC_IS_DCE4(rdev)) {
819 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
820 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
821 args.v3.acConfig.ucDigSel = dig->dig_encoder;
822 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
824 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
825 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
826 switch (radeon_encoder->encoder_id) {
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
828 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
830 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
832 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
834 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
835 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
839 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
841 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
844 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
848 union dig_transmitter_control {
849 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
850 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
851 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
852 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
856 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
858 struct drm_device *dev = encoder->dev;
859 struct radeon_device *rdev = dev->dev_private;
860 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
861 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
862 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
863 union dig_transmitter_control args;
869 int dp_lane_count = 0;
870 int connector_object_id = 0;
871 int igp_lane_info = 0;
874 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
875 struct radeon_connector_atom_dig *dig_connector =
876 radeon_connector->con_priv;
878 dp_clock = dig_connector->dp_clock;
879 dp_lane_count = dig_connector->dp_lane_count;
880 connector_object_id =
881 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
882 igp_lane_info = dig_connector->igp_lane_info;
885 /* no dig encoder assigned */
886 if (dig->dig_encoder == -1)
889 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
892 memset(&args, 0, sizeof(args));
894 switch (radeon_encoder->encoder_id) {
895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
896 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
901 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
903 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
904 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
908 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
911 args.v1.ucAction = action;
912 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
913 args.v1.usInitInfo = connector_object_id;
914 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
915 args.v1.asMode.ucLaneSel = lane_num;
916 args.v1.asMode.ucLaneSet = lane_set;
919 args.v1.usPixelClock =
920 cpu_to_le16(dp_clock / 10);
921 else if (radeon_encoder->pixel_clock > 165000)
922 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
924 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
926 if (ASIC_IS_DCE4(rdev)) {
928 args.v3.ucLaneNum = dp_lane_count;
929 else if (radeon_encoder->pixel_clock > 165000)
930 args.v3.ucLaneNum = 8;
932 args.v3.ucLaneNum = 4;
935 args.v3.acConfig.ucLinkSel = 1;
936 args.v3.acConfig.ucEncoderSel = 1;
939 /* Select the PLL for the PHY
940 * DP PHY should be clocked from external src if there is
944 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
945 pll_id = radeon_crtc->pll_id;
948 if (ASIC_IS_DCE5(rdev)) {
949 if (is_dp && rdev->clock.dp_extclk)
950 args.v4.acConfig.ucRefClkSource = 3; /* external src */
952 args.v4.acConfig.ucRefClkSource = pll_id;
954 if (is_dp && rdev->clock.dp_extclk)
955 args.v3.acConfig.ucRefClkSource = 2; /* external src */
957 args.v3.acConfig.ucRefClkSource = pll_id;
960 switch (radeon_encoder->encoder_id) {
961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
962 args.v3.acConfig.ucTransmitterSel = 0;
964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
965 args.v3.acConfig.ucTransmitterSel = 1;
967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
968 args.v3.acConfig.ucTransmitterSel = 2;
973 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
974 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
975 if (dig->coherent_mode)
976 args.v3.acConfig.fCoherentMode = 1;
977 if (radeon_encoder->pixel_clock > 165000)
978 args.v3.acConfig.fDualLinkConnector = 1;
980 } else if (ASIC_IS_DCE32(rdev)) {
981 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
983 args.v2.acConfig.ucLinkSel = 1;
985 switch (radeon_encoder->encoder_id) {
986 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
987 args.v2.acConfig.ucTransmitterSel = 0;
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
990 args.v2.acConfig.ucTransmitterSel = 1;
992 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
993 args.v2.acConfig.ucTransmitterSel = 2;
998 args.v2.acConfig.fCoherentMode = 1;
999 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1000 if (dig->coherent_mode)
1001 args.v2.acConfig.fCoherentMode = 1;
1002 if (radeon_encoder->pixel_clock > 165000)
1003 args.v2.acConfig.fDualLinkConnector = 1;
1006 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1008 if (dig->dig_encoder)
1009 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1011 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1013 if ((rdev->flags & RADEON_IS_IGP) &&
1014 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1015 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1016 if (igp_lane_info & 0x1)
1017 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1018 else if (igp_lane_info & 0x2)
1019 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1020 else if (igp_lane_info & 0x4)
1021 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1022 else if (igp_lane_info & 0x8)
1023 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1025 if (igp_lane_info & 0x3)
1026 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1027 else if (igp_lane_info & 0xc)
1028 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1033 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1035 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1038 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1039 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1040 if (dig->coherent_mode)
1041 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1042 if (radeon_encoder->pixel_clock > 165000)
1043 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1051 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1053 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1054 struct drm_device *dev = radeon_connector->base.dev;
1055 struct radeon_device *rdev = dev->dev_private;
1056 union dig_transmitter_control args;
1057 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1060 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1063 if (!ASIC_IS_DCE4(rdev))
1066 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1067 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1070 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1073 memset(&args, 0, sizeof(args));
1075 args.v1.ucAction = action;
1077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1080 union external_encoder_control {
1081 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1082 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1086 atombios_external_encoder_setup(struct drm_encoder *encoder,
1087 struct drm_encoder *ext_encoder,
1090 struct drm_device *dev = encoder->dev;
1091 struct radeon_device *rdev = dev->dev_private;
1092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1093 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1094 union external_encoder_control args;
1095 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1096 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1099 int dp_lane_count = 0;
1100 int connector_object_id = 0;
1101 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1104 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1105 struct radeon_connector_atom_dig *dig_connector =
1106 radeon_connector->con_priv;
1108 dp_clock = dig_connector->dp_clock;
1109 dp_lane_count = dig_connector->dp_lane_count;
1110 connector_object_id =
1111 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1114 memset(&args, 0, sizeof(args));
1116 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1121 /* no params on frev 1 */
1127 args.v1.sDigEncoder.ucAction = action;
1128 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1129 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1131 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1132 if (dp_clock == 270000)
1133 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1134 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1135 } else if (radeon_encoder->pixel_clock > 165000)
1136 args.v1.sDigEncoder.ucLaneNum = 8;
1138 args.v1.sDigEncoder.ucLaneNum = 4;
1141 args.v3.sExtEncoder.ucAction = action;
1142 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1143 args.v3.sExtEncoder.usConnectorId = connector_object_id;
1145 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1146 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1148 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1149 if (dp_clock == 270000)
1150 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1151 else if (dp_clock == 540000)
1152 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1153 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1154 } else if (radeon_encoder->pixel_clock > 165000)
1155 args.v3.sExtEncoder.ucLaneNum = 8;
1157 args.v3.sExtEncoder.ucLaneNum = 4;
1159 case GRAPH_OBJECT_ENUM_ID1:
1160 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1162 case GRAPH_OBJECT_ENUM_ID2:
1163 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1165 case GRAPH_OBJECT_ENUM_ID3:
1166 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1169 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1172 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1177 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1180 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1184 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1186 struct drm_device *dev = encoder->dev;
1187 struct radeon_device *rdev = dev->dev_private;
1188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1189 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1190 ENABLE_YUV_PS_ALLOCATION args;
1191 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1194 memset(&args, 0, sizeof(args));
1196 if (rdev->family >= CHIP_R600)
1197 reg = R600_BIOS_3_SCRATCH;
1199 reg = RADEON_BIOS_3_SCRATCH;
1201 /* XXX: fix up scratch reg handling */
1203 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1204 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1205 (radeon_crtc->crtc_id << 18)));
1206 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1207 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1212 args.ucEnable = ATOM_ENABLE;
1213 args.ucCRTC = radeon_crtc->crtc_id;
1215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1221 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1223 struct drm_device *dev = encoder->dev;
1224 struct radeon_device *rdev = dev->dev_private;
1225 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1226 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1227 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1229 bool is_dig = false;
1231 memset(&args, 0, sizeof(args));
1233 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1234 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1235 radeon_encoder->active_device);
1236 switch (radeon_encoder->encoder_id) {
1237 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1238 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1239 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1242 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1244 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1247 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1248 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1249 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1251 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1252 if (ASIC_IS_DCE3(rdev))
1255 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1257 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1258 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1260 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1261 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1262 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1264 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1266 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1267 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1268 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1269 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1270 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1271 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1273 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1275 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1276 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1277 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1278 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1279 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1280 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1282 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1288 case DRM_MODE_DPMS_ON:
1289 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1290 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1291 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1294 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1295 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1296 struct radeon_connector_atom_dig *radeon_dig_connector =
1297 radeon_connector->con_priv;
1298 atombios_set_edp_panel_power(connector,
1299 ATOM_TRANSMITTER_ACTION_POWER_ON);
1300 radeon_dig_connector->edp_on = true;
1302 dp_link_train(encoder, connector);
1303 if (ASIC_IS_DCE4(rdev))
1304 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1306 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1307 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1309 case DRM_MODE_DPMS_STANDBY:
1310 case DRM_MODE_DPMS_SUSPEND:
1311 case DRM_MODE_DPMS_OFF:
1312 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1313 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1316 if (ASIC_IS_DCE4(rdev))
1317 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1319 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1320 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1321 struct radeon_connector_atom_dig *radeon_dig_connector =
1322 radeon_connector->con_priv;
1323 atombios_set_edp_panel_power(connector,
1324 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1325 radeon_dig_connector->edp_on = false;
1328 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1329 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1334 case DRM_MODE_DPMS_ON:
1335 args.ucAction = ATOM_ENABLE;
1336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1337 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1338 args.ucAction = ATOM_LCD_BLON;
1339 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1342 case DRM_MODE_DPMS_STANDBY:
1343 case DRM_MODE_DPMS_SUSPEND:
1344 case DRM_MODE_DPMS_OFF:
1345 args.ucAction = ATOM_DISABLE;
1346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1347 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1348 args.ucAction = ATOM_LCD_BLOFF;
1349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1359 case DRM_MODE_DPMS_ON:
1361 if (ASIC_IS_DCE41(rdev))
1362 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1364 action = ATOM_ENABLE;
1366 case DRM_MODE_DPMS_STANDBY:
1367 case DRM_MODE_DPMS_SUSPEND:
1368 case DRM_MODE_DPMS_OFF:
1369 if (ASIC_IS_DCE41(rdev))
1370 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1372 action = ATOM_DISABLE;
1375 atombios_external_encoder_setup(encoder, ext_encoder, action);
1378 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1382 union crtc_source_param {
1383 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1384 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1388 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1390 struct drm_device *dev = encoder->dev;
1391 struct radeon_device *rdev = dev->dev_private;
1392 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1393 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1394 union crtc_source_param args;
1395 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1397 struct radeon_encoder_atom_dig *dig;
1399 memset(&args, 0, sizeof(args));
1401 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1409 if (ASIC_IS_AVIVO(rdev))
1410 args.v1.ucCRTC = radeon_crtc->crtc_id;
1412 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1413 args.v1.ucCRTC = radeon_crtc->crtc_id;
1415 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1418 switch (radeon_encoder->encoder_id) {
1419 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1421 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1423 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1424 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1425 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1426 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1428 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1430 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1431 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1432 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1433 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1435 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1437 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1438 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1439 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1440 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1442 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1444 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1446 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1447 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1448 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1449 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1451 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1456 args.v2.ucCRTC = radeon_crtc->crtc_id;
1457 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1458 switch (radeon_encoder->encoder_id) {
1459 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1460 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1461 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1462 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1463 dig = radeon_encoder->enc_priv;
1464 switch (dig->dig_encoder) {
1466 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1469 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1472 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1475 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1478 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1481 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1485 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1486 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1488 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1489 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1490 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1491 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1492 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1494 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1496 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1497 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1498 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1499 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1500 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1502 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1509 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1513 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515 /* update scratch regs with new routing */
1516 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1520 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1521 struct drm_display_mode *mode)
1523 struct drm_device *dev = encoder->dev;
1524 struct radeon_device *rdev = dev->dev_private;
1525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1526 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1528 /* Funky macbooks */
1529 if ((dev->pdev->device == 0x71C5) &&
1530 (dev->pdev->subsystem_vendor == 0x106b) &&
1531 (dev->pdev->subsystem_device == 0x0080)) {
1532 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1533 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1535 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1536 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1538 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1542 /* set scaler clears this on some chips */
1543 /* XXX check DCE4 */
1544 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1545 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1546 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1547 AVIVO_D1MODE_INTERLEAVE_EN);
1551 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1553 struct drm_device *dev = encoder->dev;
1554 struct radeon_device *rdev = dev->dev_private;
1555 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1556 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1557 struct drm_encoder *test_encoder;
1558 struct radeon_encoder_atom_dig *dig;
1559 uint32_t dig_enc_in_use = 0;
1562 if (ASIC_IS_DCE4(rdev)) {
1563 dig = radeon_encoder->enc_priv;
1564 if (ASIC_IS_DCE41(rdev)) {
1570 switch (radeon_encoder->encoder_id) {
1571 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1577 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1583 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1593 /* on DCE32 and encoder can driver any block so just crtc id */
1594 if (ASIC_IS_DCE32(rdev)) {
1595 return radeon_crtc->crtc_id;
1598 /* on DCE3 - LVTMA can only be driven by DIGB */
1599 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1600 struct radeon_encoder *radeon_test_encoder;
1602 if (encoder == test_encoder)
1605 if (!radeon_encoder_is_digital(test_encoder))
1608 radeon_test_encoder = to_radeon_encoder(test_encoder);
1609 dig = radeon_test_encoder->enc_priv;
1611 if (dig->dig_encoder >= 0)
1612 dig_enc_in_use |= (1 << dig->dig_encoder);
1615 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1616 if (dig_enc_in_use & 0x2)
1617 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1620 if (!(dig_enc_in_use & 1))
1626 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1627 struct drm_display_mode *mode,
1628 struct drm_display_mode *adjusted_mode)
1630 struct drm_device *dev = encoder->dev;
1631 struct radeon_device *rdev = dev->dev_private;
1632 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1633 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1635 radeon_encoder->pixel_clock = adjusted_mode->clock;
1637 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1638 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1639 atombios_yuv_setup(encoder, true);
1641 atombios_yuv_setup(encoder, false);
1644 switch (radeon_encoder->encoder_id) {
1645 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1646 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1647 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1648 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1649 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1651 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1653 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1655 if (ASIC_IS_DCE4(rdev)) {
1656 /* disable the transmitter */
1657 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1658 /* setup and enable the encoder */
1659 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1661 /* init and enable the transmitter */
1662 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1663 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1665 /* disable the encoder and transmitter */
1666 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1667 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1669 /* setup and enable the encoder and transmitter */
1670 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1671 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1673 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1676 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1677 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1678 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1679 atombios_dvo_setup(encoder, ATOM_ENABLE);
1681 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1683 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1684 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1685 atombios_dac_setup(encoder, ATOM_ENABLE);
1686 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1687 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1688 atombios_tv_setup(encoder, ATOM_ENABLE);
1690 atombios_tv_setup(encoder, ATOM_DISABLE);
1696 if (ASIC_IS_DCE41(rdev)) {
1697 atombios_external_encoder_setup(encoder, ext_encoder,
1698 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1699 atombios_external_encoder_setup(encoder, ext_encoder,
1700 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1702 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1705 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1707 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1708 r600_hdmi_enable(encoder);
1709 r600_hdmi_setmode(encoder, adjusted_mode);
1714 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1716 struct drm_device *dev = encoder->dev;
1717 struct radeon_device *rdev = dev->dev_private;
1718 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1719 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1721 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1722 ATOM_DEVICE_CV_SUPPORT |
1723 ATOM_DEVICE_CRT_SUPPORT)) {
1724 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1725 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1728 memset(&args, 0, sizeof(args));
1730 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1733 args.sDacload.ucMisc = 0;
1735 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1736 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1737 args.sDacload.ucDacType = ATOM_DAC_A;
1739 args.sDacload.ucDacType = ATOM_DAC_B;
1741 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1742 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1743 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1744 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1745 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1746 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1748 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1749 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1750 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1752 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1755 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1762 static enum drm_connector_status
1763 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1765 struct drm_device *dev = encoder->dev;
1766 struct radeon_device *rdev = dev->dev_private;
1767 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1768 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1769 uint32_t bios_0_scratch;
1771 if (!atombios_dac_load_detect(encoder, connector)) {
1772 DRM_DEBUG_KMS("detect returned false \n");
1773 return connector_status_unknown;
1776 if (rdev->family >= CHIP_R600)
1777 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1779 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1781 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1782 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1783 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1784 return connector_status_connected;
1786 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1787 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1788 return connector_status_connected;
1790 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1791 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1792 return connector_status_connected;
1794 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1795 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1796 return connector_status_connected; /* CTV */
1797 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1798 return connector_status_connected; /* STV */
1800 return connector_status_disconnected;
1803 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1806 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1808 if (radeon_encoder->active_device &
1809 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1810 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1812 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1815 radeon_atom_output_lock(encoder, true);
1816 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1818 /* select the clock/data port if it uses a router */
1820 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1821 if (radeon_connector->router.cd_valid)
1822 radeon_router_select_cd_port(radeon_connector);
1825 /* this is needed for the pll/ss setup to work correctly in some cases */
1826 atombios_set_encoder_crtc_source(encoder);
1829 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1831 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1832 radeon_atom_output_lock(encoder, false);
1835 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1837 struct drm_device *dev = encoder->dev;
1838 struct radeon_device *rdev = dev->dev_private;
1839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1840 struct radeon_encoder_atom_dig *dig;
1842 /* check for pre-DCE3 cards with shared encoders;
1843 * can't really use the links individually, so don't disable
1844 * the encoder if it's in use by another connector
1846 if (!ASIC_IS_DCE3(rdev)) {
1847 struct drm_encoder *other_encoder;
1848 struct radeon_encoder *other_radeon_encoder;
1850 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1851 other_radeon_encoder = to_radeon_encoder(other_encoder);
1852 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1853 drm_helper_encoder_in_use(other_encoder))
1858 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1860 switch (radeon_encoder->encoder_id) {
1861 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1862 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1863 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1864 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1865 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1869 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1871 if (ASIC_IS_DCE4(rdev))
1872 /* disable the transmitter */
1873 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1875 /* disable the encoder and transmitter */
1876 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1877 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1880 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1881 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1882 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1883 atombios_dvo_setup(encoder, ATOM_DISABLE);
1885 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1886 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1887 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1889 atombios_dac_setup(encoder, ATOM_DISABLE);
1890 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1891 atombios_tv_setup(encoder, ATOM_DISABLE);
1896 if (radeon_encoder_is_digital(encoder)) {
1897 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1898 r600_hdmi_disable(encoder);
1899 dig = radeon_encoder->enc_priv;
1900 dig->dig_encoder = -1;
1902 radeon_encoder->active_device = 0;
1905 /* these are handled by the primary encoders */
1906 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1911 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1917 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1918 struct drm_display_mode *mode,
1919 struct drm_display_mode *adjusted_mode)
1924 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1930 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
1935 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
1936 struct drm_display_mode *mode,
1937 struct drm_display_mode *adjusted_mode)
1942 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
1943 .dpms = radeon_atom_ext_dpms,
1944 .mode_fixup = radeon_atom_ext_mode_fixup,
1945 .prepare = radeon_atom_ext_prepare,
1946 .mode_set = radeon_atom_ext_mode_set,
1947 .commit = radeon_atom_ext_commit,
1948 .disable = radeon_atom_ext_disable,
1949 /* no detect for TMDS/LVDS yet */
1952 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1953 .dpms = radeon_atom_encoder_dpms,
1954 .mode_fixup = radeon_atom_mode_fixup,
1955 .prepare = radeon_atom_encoder_prepare,
1956 .mode_set = radeon_atom_encoder_mode_set,
1957 .commit = radeon_atom_encoder_commit,
1958 .disable = radeon_atom_encoder_disable,
1959 /* no detect for TMDS/LVDS yet */
1962 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1963 .dpms = radeon_atom_encoder_dpms,
1964 .mode_fixup = radeon_atom_mode_fixup,
1965 .prepare = radeon_atom_encoder_prepare,
1966 .mode_set = radeon_atom_encoder_mode_set,
1967 .commit = radeon_atom_encoder_commit,
1968 .detect = radeon_atom_dac_detect,
1971 void radeon_enc_destroy(struct drm_encoder *encoder)
1973 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1974 kfree(radeon_encoder->enc_priv);
1975 drm_encoder_cleanup(encoder);
1976 kfree(radeon_encoder);
1979 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1980 .destroy = radeon_enc_destroy,
1983 struct radeon_encoder_atom_dac *
1984 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1986 struct drm_device *dev = radeon_encoder->base.dev;
1987 struct radeon_device *rdev = dev->dev_private;
1988 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1993 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1997 struct radeon_encoder_atom_dig *
1998 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2000 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2001 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2006 /* coherent mode by default */
2007 dig->coherent_mode = true;
2008 dig->dig_encoder = -1;
2010 if (encoder_enum == 2)
2019 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
2021 struct radeon_device *rdev = dev->dev_private;
2022 struct drm_encoder *encoder;
2023 struct radeon_encoder *radeon_encoder;
2025 /* see if we already added it */
2026 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2027 radeon_encoder = to_radeon_encoder(encoder);
2028 if (radeon_encoder->encoder_enum == encoder_enum) {
2029 radeon_encoder->devices |= supported_device;
2036 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2037 if (!radeon_encoder)
2040 encoder = &radeon_encoder->base;
2041 switch (rdev->num_crtc) {
2043 encoder->possible_crtcs = 0x1;
2047 encoder->possible_crtcs = 0x3;
2050 encoder->possible_crtcs = 0x3f;
2054 radeon_encoder->enc_priv = NULL;
2056 radeon_encoder->encoder_enum = encoder_enum;
2057 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2058 radeon_encoder->devices = supported_device;
2059 radeon_encoder->rmx_type = RMX_OFF;
2060 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2061 radeon_encoder->is_ext_encoder = false;
2063 switch (radeon_encoder->encoder_id) {
2064 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2065 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2067 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2068 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2069 radeon_encoder->rmx_type = RMX_FULL;
2070 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2071 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2073 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2074 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2075 if (ASIC_IS_AVIVO(rdev))
2076 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2078 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2080 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2081 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2082 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2083 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2085 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2086 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2087 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2088 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2089 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2090 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2092 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2093 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2094 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2095 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2096 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2097 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2098 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2099 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2100 radeon_encoder->rmx_type = RMX_FULL;
2101 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2102 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2103 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2104 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2105 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2107 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2108 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2109 if (ASIC_IS_AVIVO(rdev))
2110 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2112 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2114 case ENCODER_OBJECT_ID_SI170B:
2115 case ENCODER_OBJECT_ID_CH7303:
2116 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2117 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2118 case ENCODER_OBJECT_ID_TITFP513:
2119 case ENCODER_OBJECT_ID_VT1623:
2120 case ENCODER_OBJECT_ID_HDMI_SI1930:
2121 case ENCODER_OBJECT_ID_TRAVIS:
2122 case ENCODER_OBJECT_ID_NUTMEG:
2123 /* these are handled by the primary encoders */
2124 radeon_encoder->is_ext_encoder = true;
2125 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2126 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2127 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2128 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2130 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2131 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);