2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
240 if (!rdev->is_atom_bios)
243 connector = radeon_get_connector_for_encoder(encoder);
247 radeon_connector = to_radeon_connector(connector);
249 if (!radeon_connector->con_priv)
252 dig_connector = radeon_connector->con_priv;
254 return dig_connector;
257 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode)
260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
261 struct drm_device *dev = encoder->dev;
262 struct radeon_device *rdev = dev->dev_private;
263 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
264 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
265 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
266 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
267 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
268 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
269 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
271 adjusted_mode->clock = native_mode->clock;
272 adjusted_mode->flags = native_mode->flags;
274 if (ASIC_IS_AVIVO(rdev)) {
275 adjusted_mode->hdisplay = native_mode->hdisplay;
276 adjusted_mode->vdisplay = native_mode->vdisplay;
279 adjusted_mode->htotal = native_mode->hdisplay + hblank;
280 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
281 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
283 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
284 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
285 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
287 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
291 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
294 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
295 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
296 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
298 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
299 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
300 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
304 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
305 struct drm_display_mode *mode,
306 struct drm_display_mode *adjusted_mode)
308 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
309 struct drm_device *dev = encoder->dev;
310 struct radeon_device *rdev = dev->dev_private;
312 /* set the active encoder to connector routing */
313 radeon_encoder_set_active_device(encoder);
314 drm_mode_set_crtcinfo(adjusted_mode, 0);
317 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
318 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
319 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
321 /* get the native mode for LVDS */
322 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
323 radeon_panel_mode_fixup(encoder, adjusted_mode);
325 /* get the native mode for TV */
326 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
327 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
329 if (tv_dac->tv_std == TV_STD_NTSC ||
330 tv_dac->tv_std == TV_STD_NTSC_J ||
331 tv_dac->tv_std == TV_STD_PAL_M)
332 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
334 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
338 if (ASIC_IS_DCE3(rdev) &&
339 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
340 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
341 radeon_dp_set_link_config(connector, mode);
348 atombios_dac_setup(struct drm_encoder *encoder, int action)
350 struct drm_device *dev = encoder->dev;
351 struct radeon_device *rdev = dev->dev_private;
352 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
353 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
355 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
357 memset(&args, 0, sizeof(args));
359 switch (radeon_encoder->encoder_id) {
360 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
362 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
364 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
365 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
366 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
370 args.ucAction = action;
372 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
373 args.ucDacStandard = ATOM_DAC1_PS2;
374 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
375 args.ucDacStandard = ATOM_DAC1_CV;
377 switch (dac_info->tv_std) {
380 case TV_STD_SCART_PAL:
383 args.ucDacStandard = ATOM_DAC1_PAL;
389 args.ucDacStandard = ATOM_DAC1_NTSC;
393 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
395 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
400 atombios_tv_setup(struct drm_encoder *encoder, int action)
402 struct drm_device *dev = encoder->dev;
403 struct radeon_device *rdev = dev->dev_private;
404 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
405 TV_ENCODER_CONTROL_PS_ALLOCATION args;
407 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
409 memset(&args, 0, sizeof(args));
411 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
413 args.sTVEncoder.ucAction = action;
415 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
416 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
418 switch (dac_info->tv_std) {
420 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
426 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
429 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
432 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
434 case TV_STD_SCART_PAL:
435 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
438 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
441 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
444 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
449 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
451 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
456 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
458 struct drm_device *dev = encoder->dev;
459 struct radeon_device *rdev = dev->dev_private;
460 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
461 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
464 memset(&args, 0, sizeof(args));
466 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
468 args.sXTmdsEncoder.ucEnable = action;
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
473 /*if (pScrn->rgbBits == 8)*/
474 args.sXTmdsEncoder.ucMisc |= (1 << 1);
476 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
481 atombios_ddia_setup(struct drm_encoder *encoder, int action)
483 struct drm_device *dev = encoder->dev;
484 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
489 memset(&args, 0, sizeof(args));
491 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
493 args.sDVOEncoder.ucAction = action;
494 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
496 if (radeon_encoder->pixel_clock > 165000)
497 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
499 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
503 union lvds_encoder_control {
504 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
505 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
509 atombios_digital_setup(struct drm_encoder *encoder, int action)
511 struct drm_device *dev = encoder->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
514 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
515 struct radeon_connector_atom_dig *dig_connector =
516 radeon_get_atom_connector_priv_from_encoder(encoder);
517 union lvds_encoder_control args;
519 int hdmi_detected = 0;
522 if (!dig || !dig_connector)
525 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
528 memset(&args, 0, sizeof(args));
530 switch (radeon_encoder->encoder_id) {
531 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
532 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
534 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
536 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
538 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
539 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
540 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
542 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
546 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
555 args.v1.ucAction = action;
557 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
558 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
559 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
560 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
561 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
562 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
563 args.v1.ucMisc |= (1 << 1);
566 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
567 if (radeon_encoder->pixel_clock > 165000)
568 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
569 /*if (pScrn->rgbBits == 8) */
570 args.v1.ucMisc |= (1 << 1);
576 args.v2.ucAction = action;
578 if (dig->coherent_mode)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
582 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
583 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
584 args.v2.ucTruncate = 0;
585 args.v2.ucSpatial = 0;
586 args.v2.ucTemporal = 0;
588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
589 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
590 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
591 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
592 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
593 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
594 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
596 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
597 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
598 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
599 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
600 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
601 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
605 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
606 if (radeon_encoder->pixel_clock > 165000)
607 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
616 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
624 atombios_get_encoder_mode(struct drm_encoder *encoder)
626 struct drm_connector *connector;
627 struct radeon_connector *radeon_connector;
628 struct radeon_connector_atom_dig *dig_connector;
630 connector = radeon_get_connector_for_encoder(encoder);
634 radeon_connector = to_radeon_connector(connector);
636 switch (connector->connector_type) {
637 case DRM_MODE_CONNECTOR_DVII:
638 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
639 if (drm_detect_hdmi_monitor(radeon_connector->edid))
640 return ATOM_ENCODER_MODE_HDMI;
641 else if (radeon_connector->use_digital)
642 return ATOM_ENCODER_MODE_DVI;
644 return ATOM_ENCODER_MODE_CRT;
646 case DRM_MODE_CONNECTOR_DVID:
647 case DRM_MODE_CONNECTOR_HDMIA:
649 if (drm_detect_hdmi_monitor(radeon_connector->edid))
650 return ATOM_ENCODER_MODE_HDMI;
652 return ATOM_ENCODER_MODE_DVI;
654 case DRM_MODE_CONNECTOR_LVDS:
655 return ATOM_ENCODER_MODE_LVDS;
657 case DRM_MODE_CONNECTOR_DisplayPort:
658 case DRM_MODE_CONNECTOR_eDP:
659 dig_connector = radeon_connector->con_priv;
660 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
661 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
662 return ATOM_ENCODER_MODE_DP;
663 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
664 return ATOM_ENCODER_MODE_HDMI;
666 return ATOM_ENCODER_MODE_DVI;
668 case DRM_MODE_CONNECTOR_DVIA:
669 case DRM_MODE_CONNECTOR_VGA:
670 return ATOM_ENCODER_MODE_CRT;
672 case DRM_MODE_CONNECTOR_Composite:
673 case DRM_MODE_CONNECTOR_SVIDEO:
674 case DRM_MODE_CONNECTOR_9PinDIN:
676 return ATOM_ENCODER_MODE_TV;
677 /*return ATOM_ENCODER_MODE_CV;*/
683 * DIG Encoder/Transmitter Setup
686 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
687 * Supports up to 3 digital outputs
688 * - 2 DIG encoder blocks.
689 * DIG1 can drive UNIPHY link A or link B
690 * DIG2 can drive UNIPHY link B or LVTMA
693 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
694 * Supports up to 5 digital outputs
695 * - 2 DIG encoder blocks.
696 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
699 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
700 * Supports up to 6 digital outputs
701 * - 6 DIG encoder blocks.
702 * - DIG to PHY mapping is hardcoded
703 * DIG1 drives UNIPHY0 link A, A+B
704 * DIG2 drives UNIPHY0 link B
705 * DIG3 drives UNIPHY1 link A, A+B
706 * DIG4 drives UNIPHY1 link B
707 * DIG5 drives UNIPHY2 link A, A+B
708 * DIG6 drives UNIPHY2 link B
711 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
713 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
714 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
715 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
716 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
719 union dig_encoder_control {
720 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
721 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
722 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
726 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
728 struct drm_device *dev = encoder->dev;
729 struct radeon_device *rdev = dev->dev_private;
730 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
731 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
732 struct radeon_connector_atom_dig *dig_connector =
733 radeon_get_atom_connector_priv_from_encoder(encoder);
734 union dig_encoder_control args;
738 if (!dig || !dig_connector)
741 memset(&args, 0, sizeof(args));
743 if (ASIC_IS_DCE4(rdev))
744 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
746 if (dig->dig_encoder)
747 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
749 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
752 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
755 args.v1.ucAction = action;
756 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
757 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
759 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
760 if (dig_connector->dp_clock == 270000)
761 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
762 args.v1.ucLaneNum = dig_connector->dp_lane_count;
763 } else if (radeon_encoder->pixel_clock > 165000)
764 args.v1.ucLaneNum = 8;
766 args.v1.ucLaneNum = 4;
768 if (ASIC_IS_DCE4(rdev)) {
769 args.v3.acConfig.ucDigSel = dig->dig_encoder;
770 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
772 switch (radeon_encoder->encoder_id) {
773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
774 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
776 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
777 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
778 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
781 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
785 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
787 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
790 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
794 union dig_transmitter_control {
795 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
796 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
797 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
801 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
803 struct drm_device *dev = encoder->dev;
804 struct radeon_device *rdev = dev->dev_private;
805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
806 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
807 struct radeon_connector_atom_dig *dig_connector =
808 radeon_get_atom_connector_priv_from_encoder(encoder);
809 struct drm_connector *connector;
810 struct radeon_connector *radeon_connector;
811 union dig_transmitter_control args;
817 if (!dig || !dig_connector)
820 connector = radeon_get_connector_for_encoder(encoder);
821 radeon_connector = to_radeon_connector(connector);
823 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
826 memset(&args, 0, sizeof(args));
828 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
829 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
831 switch (radeon_encoder->encoder_id) {
832 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
833 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
836 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
844 args.v1.ucAction = action;
845 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
847 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
848 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
849 args.v1.asMode.ucLaneSel = lane_num;
850 args.v1.asMode.ucLaneSet = lane_set;
853 args.v1.usPixelClock =
854 cpu_to_le16(dig_connector->dp_clock / 10);
855 else if (radeon_encoder->pixel_clock > 165000)
856 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
858 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
860 if (ASIC_IS_DCE4(rdev)) {
862 args.v3.ucLaneNum = dig_connector->dp_lane_count;
863 else if (radeon_encoder->pixel_clock > 165000)
864 args.v3.ucLaneNum = 8;
866 args.v3.ucLaneNum = 4;
869 args.v3.acConfig.ucLinkSel = 1;
870 args.v3.acConfig.ucEncoderSel = 1;
873 /* Select the PLL for the PHY
874 * DP PHY should be clocked from external src if there is
878 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
879 pll_id = radeon_crtc->pll_id;
881 if (is_dp && rdev->clock.dp_extclk)
882 args.v3.acConfig.ucRefClkSource = 2; /* external src */
884 args.v3.acConfig.ucRefClkSource = pll_id;
886 switch (radeon_encoder->encoder_id) {
887 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
888 args.v3.acConfig.ucTransmitterSel = 0;
890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
891 args.v3.acConfig.ucTransmitterSel = 1;
893 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
894 args.v3.acConfig.ucTransmitterSel = 2;
899 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
900 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
901 if (dig->coherent_mode)
902 args.v3.acConfig.fCoherentMode = 1;
903 if (radeon_encoder->pixel_clock > 165000)
904 args.v3.acConfig.fDualLinkConnector = 1;
906 } else if (ASIC_IS_DCE32(rdev)) {
907 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
909 args.v2.acConfig.ucLinkSel = 1;
911 switch (radeon_encoder->encoder_id) {
912 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
913 args.v2.acConfig.ucTransmitterSel = 0;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
916 args.v2.acConfig.ucTransmitterSel = 1;
918 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
919 args.v2.acConfig.ucTransmitterSel = 2;
924 args.v2.acConfig.fCoherentMode = 1;
925 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
926 if (dig->coherent_mode)
927 args.v2.acConfig.fCoherentMode = 1;
928 if (radeon_encoder->pixel_clock > 165000)
929 args.v2.acConfig.fDualLinkConnector = 1;
932 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
934 if (dig->dig_encoder)
935 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
937 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
939 if ((rdev->flags & RADEON_IS_IGP) &&
940 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
941 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
942 if (dig_connector->igp_lane_info & 0x1)
943 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
944 else if (dig_connector->igp_lane_info & 0x2)
945 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
946 else if (dig_connector->igp_lane_info & 0x4)
947 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
948 else if (dig_connector->igp_lane_info & 0x8)
949 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
951 if (dig_connector->igp_lane_info & 0x3)
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
953 else if (dig_connector->igp_lane_info & 0xc)
954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
959 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
961 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
965 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
966 if (dig->coherent_mode)
967 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
968 if (radeon_encoder->pixel_clock > 165000)
969 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
973 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
977 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
979 struct drm_device *dev = encoder->dev;
980 struct radeon_device *rdev = dev->dev_private;
981 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
982 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
983 ENABLE_YUV_PS_ALLOCATION args;
984 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
987 memset(&args, 0, sizeof(args));
989 if (rdev->family >= CHIP_R600)
990 reg = R600_BIOS_3_SCRATCH;
992 reg = RADEON_BIOS_3_SCRATCH;
994 /* XXX: fix up scratch reg handling */
996 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
997 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
998 (radeon_crtc->crtc_id << 18)));
999 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1000 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1005 args.ucEnable = ATOM_ENABLE;
1006 args.ucCRTC = radeon_crtc->crtc_id;
1008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1014 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1016 struct drm_device *dev = encoder->dev;
1017 struct radeon_device *rdev = dev->dev_private;
1018 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1019 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1021 bool is_dig = false;
1023 memset(&args, 0, sizeof(args));
1025 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1026 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1027 radeon_encoder->active_device);
1028 switch (radeon_encoder->encoder_id) {
1029 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1030 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1031 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1036 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1039 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1040 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1041 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1042 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1044 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1045 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1047 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1048 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1049 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1051 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1053 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1055 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1056 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1057 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1058 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1060 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1062 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1063 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1064 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1065 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1066 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1067 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1069 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1075 case DRM_MODE_DPMS_ON:
1076 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1077 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1078 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1080 dp_link_train(encoder, connector);
1081 if (ASIC_IS_DCE4(rdev))
1082 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1085 case DRM_MODE_DPMS_STANDBY:
1086 case DRM_MODE_DPMS_SUSPEND:
1087 case DRM_MODE_DPMS_OFF:
1088 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1089 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1090 if (ASIC_IS_DCE4(rdev))
1091 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1097 case DRM_MODE_DPMS_ON:
1098 args.ucAction = ATOM_ENABLE;
1100 case DRM_MODE_DPMS_STANDBY:
1101 case DRM_MODE_DPMS_SUSPEND:
1102 case DRM_MODE_DPMS_OFF:
1103 args.ucAction = ATOM_DISABLE;
1106 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1108 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1112 union crtc_source_param {
1113 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1114 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1118 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1120 struct drm_device *dev = encoder->dev;
1121 struct radeon_device *rdev = dev->dev_private;
1122 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1124 union crtc_source_param args;
1125 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1127 struct radeon_encoder_atom_dig *dig;
1129 memset(&args, 0, sizeof(args));
1131 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1139 if (ASIC_IS_AVIVO(rdev))
1140 args.v1.ucCRTC = radeon_crtc->crtc_id;
1142 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1143 args.v1.ucCRTC = radeon_crtc->crtc_id;
1145 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1148 switch (radeon_encoder->encoder_id) {
1149 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1150 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1151 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1153 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1154 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1155 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1156 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1158 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1160 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1161 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1163 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1165 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1167 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1168 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1169 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1170 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1172 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1174 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1175 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1176 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1177 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1178 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1179 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1181 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1186 args.v2.ucCRTC = radeon_crtc->crtc_id;
1187 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1188 switch (radeon_encoder->encoder_id) {
1189 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1192 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1193 dig = radeon_encoder->enc_priv;
1194 switch (dig->dig_encoder) {
1196 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1199 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1202 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1205 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1208 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1211 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1215 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1216 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1218 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1219 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1220 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1221 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1222 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1224 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1226 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1227 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1228 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1229 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1230 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1232 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1239 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1243 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1245 /* update scratch regs with new routing */
1246 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1250 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1251 struct drm_display_mode *mode)
1253 struct drm_device *dev = encoder->dev;
1254 struct radeon_device *rdev = dev->dev_private;
1255 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1256 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1258 /* Funky macbooks */
1259 if ((dev->pdev->device == 0x71C5) &&
1260 (dev->pdev->subsystem_vendor == 0x106b) &&
1261 (dev->pdev->subsystem_device == 0x0080)) {
1262 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1263 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1265 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1266 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1268 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1272 /* set scaler clears this on some chips */
1273 /* XXX check DCE4 */
1274 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1275 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1276 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1277 AVIVO_D1MODE_INTERLEAVE_EN);
1281 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1283 struct drm_device *dev = encoder->dev;
1284 struct radeon_device *rdev = dev->dev_private;
1285 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1286 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1287 struct drm_encoder *test_encoder;
1288 struct radeon_encoder_atom_dig *dig;
1289 uint32_t dig_enc_in_use = 0;
1291 if (ASIC_IS_DCE4(rdev)) {
1292 dig = radeon_encoder->enc_priv;
1293 switch (radeon_encoder->encoder_id) {
1294 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1315 /* on DCE32 and encoder can driver any block so just crtc id */
1316 if (ASIC_IS_DCE32(rdev)) {
1317 return radeon_crtc->crtc_id;
1320 /* on DCE3 - LVTMA can only be driven by DIGB */
1321 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1322 struct radeon_encoder *radeon_test_encoder;
1324 if (encoder == test_encoder)
1327 if (!radeon_encoder_is_digital(test_encoder))
1330 radeon_test_encoder = to_radeon_encoder(test_encoder);
1331 dig = radeon_test_encoder->enc_priv;
1333 if (dig->dig_encoder >= 0)
1334 dig_enc_in_use |= (1 << dig->dig_encoder);
1337 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1338 if (dig_enc_in_use & 0x2)
1339 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1342 if (!(dig_enc_in_use & 1))
1348 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1349 struct drm_display_mode *mode,
1350 struct drm_display_mode *adjusted_mode)
1352 struct drm_device *dev = encoder->dev;
1353 struct radeon_device *rdev = dev->dev_private;
1354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1356 radeon_encoder->pixel_clock = adjusted_mode->clock;
1358 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1359 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1360 atombios_yuv_setup(encoder, true);
1362 atombios_yuv_setup(encoder, false);
1365 switch (radeon_encoder->encoder_id) {
1366 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1368 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1369 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1370 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1372 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1376 if (ASIC_IS_DCE4(rdev)) {
1377 /* disable the transmitter */
1378 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1379 /* setup and enable the encoder */
1380 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1382 /* init and enable the transmitter */
1383 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1384 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1386 /* disable the encoder and transmitter */
1387 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1388 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1390 /* setup and enable the encoder and transmitter */
1391 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1392 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1393 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1394 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1397 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1398 atombios_ddia_setup(encoder, ATOM_ENABLE);
1400 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1402 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1404 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1405 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1406 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1408 atombios_dac_setup(encoder, ATOM_ENABLE);
1409 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1410 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1411 atombios_tv_setup(encoder, ATOM_ENABLE);
1413 atombios_tv_setup(encoder, ATOM_DISABLE);
1417 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1419 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1420 r600_hdmi_enable(encoder);
1421 r600_hdmi_setmode(encoder, adjusted_mode);
1426 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1428 struct drm_device *dev = encoder->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1431 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1433 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1434 ATOM_DEVICE_CV_SUPPORT |
1435 ATOM_DEVICE_CRT_SUPPORT)) {
1436 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1437 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1440 memset(&args, 0, sizeof(args));
1442 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1445 args.sDacload.ucMisc = 0;
1447 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1448 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1449 args.sDacload.ucDacType = ATOM_DAC_A;
1451 args.sDacload.ucDacType = ATOM_DAC_B;
1453 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1454 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1455 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1456 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1457 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1458 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1460 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1461 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1462 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1464 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1467 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1474 static enum drm_connector_status
1475 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1477 struct drm_device *dev = encoder->dev;
1478 struct radeon_device *rdev = dev->dev_private;
1479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1480 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1481 uint32_t bios_0_scratch;
1483 if (!atombios_dac_load_detect(encoder, connector)) {
1484 DRM_DEBUG_KMS("detect returned false \n");
1485 return connector_status_unknown;
1488 if (rdev->family >= CHIP_R600)
1489 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1491 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1493 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1494 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1495 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1496 return connector_status_connected;
1498 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1499 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1500 return connector_status_connected;
1502 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1503 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1504 return connector_status_connected;
1506 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1507 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1508 return connector_status_connected; /* CTV */
1509 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1510 return connector_status_connected; /* STV */
1512 return connector_status_disconnected;
1515 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1517 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1519 if (radeon_encoder->active_device &
1520 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1521 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1523 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1526 radeon_atom_output_lock(encoder, true);
1527 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1529 /* this is needed for the pll/ss setup to work correctly in some cases */
1530 atombios_set_encoder_crtc_source(encoder);
1533 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1535 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1536 radeon_atom_output_lock(encoder, false);
1539 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1541 struct drm_device *dev = encoder->dev;
1542 struct radeon_device *rdev = dev->dev_private;
1543 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1544 struct radeon_encoder_atom_dig *dig;
1545 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1547 switch (radeon_encoder->encoder_id) {
1548 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1549 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1550 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1551 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1552 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1554 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1555 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1556 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1558 if (ASIC_IS_DCE4(rdev))
1559 /* disable the transmitter */
1560 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1562 /* disable the encoder and transmitter */
1563 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1564 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1567 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1568 atombios_ddia_setup(encoder, ATOM_DISABLE);
1570 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1571 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1572 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1574 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1575 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1576 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1578 atombios_dac_setup(encoder, ATOM_DISABLE);
1579 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1580 atombios_tv_setup(encoder, ATOM_DISABLE);
1584 if (radeon_encoder_is_digital(encoder)) {
1585 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1586 r600_hdmi_disable(encoder);
1587 dig = radeon_encoder->enc_priv;
1588 dig->dig_encoder = -1;
1590 radeon_encoder->active_device = 0;
1593 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1594 .dpms = radeon_atom_encoder_dpms,
1595 .mode_fixup = radeon_atom_mode_fixup,
1596 .prepare = radeon_atom_encoder_prepare,
1597 .mode_set = radeon_atom_encoder_mode_set,
1598 .commit = radeon_atom_encoder_commit,
1599 .disable = radeon_atom_encoder_disable,
1600 /* no detect for TMDS/LVDS yet */
1603 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1604 .dpms = radeon_atom_encoder_dpms,
1605 .mode_fixup = radeon_atom_mode_fixup,
1606 .prepare = radeon_atom_encoder_prepare,
1607 .mode_set = radeon_atom_encoder_mode_set,
1608 .commit = radeon_atom_encoder_commit,
1609 .detect = radeon_atom_dac_detect,
1612 void radeon_enc_destroy(struct drm_encoder *encoder)
1614 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1615 kfree(radeon_encoder->enc_priv);
1616 drm_encoder_cleanup(encoder);
1617 kfree(radeon_encoder);
1620 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1621 .destroy = radeon_enc_destroy,
1624 struct radeon_encoder_atom_dac *
1625 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1627 struct drm_device *dev = radeon_encoder->base.dev;
1628 struct radeon_device *rdev = dev->dev_private;
1629 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1634 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1638 struct radeon_encoder_atom_dig *
1639 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1641 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1642 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1647 /* coherent mode by default */
1648 dig->coherent_mode = true;
1649 dig->dig_encoder = -1;
1651 if (encoder_enum == 2)
1660 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1662 struct radeon_device *rdev = dev->dev_private;
1663 struct drm_encoder *encoder;
1664 struct radeon_encoder *radeon_encoder;
1666 /* see if we already added it */
1667 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1668 radeon_encoder = to_radeon_encoder(encoder);
1669 if (radeon_encoder->encoder_enum == encoder_enum) {
1670 radeon_encoder->devices |= supported_device;
1677 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1678 if (!radeon_encoder)
1681 encoder = &radeon_encoder->base;
1682 switch (rdev->num_crtc) {
1684 encoder->possible_crtcs = 0x1;
1688 encoder->possible_crtcs = 0x3;
1691 encoder->possible_crtcs = 0x3f;
1695 radeon_encoder->enc_priv = NULL;
1697 radeon_encoder->encoder_enum = encoder_enum;
1698 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1699 radeon_encoder->devices = supported_device;
1700 radeon_encoder->rmx_type = RMX_OFF;
1701 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1703 switch (radeon_encoder->encoder_id) {
1704 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1705 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1706 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1707 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1708 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1709 radeon_encoder->rmx_type = RMX_FULL;
1710 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1711 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1713 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1714 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1715 if (ASIC_IS_AVIVO(rdev))
1716 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1718 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1720 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1721 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1722 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1723 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1725 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1728 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1729 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1730 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1732 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1734 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1738 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1739 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1740 radeon_encoder->rmx_type = RMX_FULL;
1741 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1742 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1744 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1745 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1746 if (ASIC_IS_AVIVO(rdev))
1747 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1749 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);