2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode)
234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
235 struct drm_device *dev = encoder->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
238 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
239 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
240 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
241 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
242 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
243 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
245 adjusted_mode->clock = native_mode->clock;
246 adjusted_mode->flags = native_mode->flags;
248 if (ASIC_IS_AVIVO(rdev)) {
249 adjusted_mode->hdisplay = native_mode->hdisplay;
250 adjusted_mode->vdisplay = native_mode->vdisplay;
253 adjusted_mode->htotal = native_mode->hdisplay + hblank;
254 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
255 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
257 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
258 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
259 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
261 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
263 if (ASIC_IS_AVIVO(rdev)) {
264 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
265 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
268 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
269 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
270 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
272 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
273 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
274 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
278 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
286 /* set the active encoder to connector routing */
287 radeon_encoder_set_active_device(encoder);
288 drm_mode_set_crtcinfo(adjusted_mode, 0);
291 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
292 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
293 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
295 /* get the native mode for LVDS */
296 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
297 radeon_panel_mode_fixup(encoder, adjusted_mode);
299 /* get the native mode for TV */
300 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
301 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
303 if (tv_dac->tv_std == TV_STD_NTSC ||
304 tv_dac->tv_std == TV_STD_NTSC_J ||
305 tv_dac->tv_std == TV_STD_PAL_M)
306 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
308 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
312 if (ASIC_IS_DCE3(rdev) &&
313 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
315 radeon_dp_set_link_config(connector, mode);
322 atombios_dac_setup(struct drm_encoder *encoder, int action)
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
329 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
331 memset(&args, 0, sizeof(args));
333 switch (radeon_encoder->encoder_id) {
334 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
336 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
340 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
344 args.ucAction = action;
346 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_PS2;
348 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
349 args.ucDacStandard = ATOM_DAC1_CV;
351 switch (dac_info->tv_std) {
354 case TV_STD_SCART_PAL:
357 args.ucDacStandard = ATOM_DAC1_PAL;
363 args.ucDacStandard = ATOM_DAC1_NTSC;
367 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
374 atombios_tv_setup(struct drm_encoder *encoder, int action)
376 struct drm_device *dev = encoder->dev;
377 struct radeon_device *rdev = dev->dev_private;
378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
379 TV_ENCODER_CONTROL_PS_ALLOCATION args;
381 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
383 memset(&args, 0, sizeof(args));
385 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
387 args.sTVEncoder.ucAction = action;
389 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
390 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
392 switch (dac_info->tv_std) {
394 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
397 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
400 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
403 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
408 case TV_STD_SCART_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
412 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
425 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
430 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
438 memset(&args, 0, sizeof(args));
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
442 args.sXTmdsEncoder.ucEnable = action;
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
455 atombios_ddia_setup(struct drm_encoder *encoder, int action)
457 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
463 memset(&args, 0, sizeof(args));
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
467 args.sDVOEncoder.ucAction = action;
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
477 union lvds_encoder_control {
478 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
479 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
483 atombios_digital_setup(struct drm_encoder *encoder, int action)
485 struct drm_device *dev = encoder->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
489 union lvds_encoder_control args;
491 int hdmi_detected = 0;
497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
500 memset(&args, 0, sizeof(args));
502 switch (radeon_encoder->encoder_id) {
503 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
504 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
506 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
508 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
512 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
514 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
518 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
527 args.v1.ucAction = action;
529 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
530 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
532 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
535 args.v1.ucMisc |= (1 << 1);
538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1);
548 args.v2.ucAction = action;
550 if (dig->coherent_mode)
551 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
554 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
555 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
556 args.v2.ucTruncate = 0;
557 args.v2.ucSpatial = 0;
558 args.v2.ucTemporal = 0;
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
561 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
562 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
563 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
564 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
565 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
566 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
568 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
569 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
570 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
571 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
572 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
578 if (radeon_encoder->pixel_clock > 165000)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
583 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
588 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
596 atombios_get_encoder_mode(struct drm_encoder *encoder)
598 struct drm_device *dev = encoder->dev;
599 struct radeon_device *rdev = dev->dev_private;
600 struct drm_connector *connector;
601 struct radeon_connector *radeon_connector;
602 struct radeon_connector_atom_dig *dig_connector;
604 connector = radeon_get_connector_for_encoder(encoder);
608 radeon_connector = to_radeon_connector(connector);
610 switch (connector->connector_type) {
611 case DRM_MODE_CONNECTOR_DVII:
612 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
613 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
615 if (ASIC_IS_DCE4(rdev))
616 return ATOM_ENCODER_MODE_DVI;
618 return ATOM_ENCODER_MODE_HDMI;
619 } else if (radeon_connector->use_digital)
620 return ATOM_ENCODER_MODE_DVI;
622 return ATOM_ENCODER_MODE_CRT;
624 case DRM_MODE_CONNECTOR_DVID:
625 case DRM_MODE_CONNECTOR_HDMIA:
627 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
629 if (ASIC_IS_DCE4(rdev))
630 return ATOM_ENCODER_MODE_DVI;
632 return ATOM_ENCODER_MODE_HDMI;
634 return ATOM_ENCODER_MODE_DVI;
636 case DRM_MODE_CONNECTOR_LVDS:
637 return ATOM_ENCODER_MODE_LVDS;
639 case DRM_MODE_CONNECTOR_DisplayPort:
640 case DRM_MODE_CONNECTOR_eDP:
641 dig_connector = radeon_connector->con_priv;
642 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
643 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
644 return ATOM_ENCODER_MODE_DP;
645 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
647 if (ASIC_IS_DCE4(rdev))
648 return ATOM_ENCODER_MODE_DVI;
650 return ATOM_ENCODER_MODE_HDMI;
652 return ATOM_ENCODER_MODE_DVI;
654 case DRM_MODE_CONNECTOR_DVIA:
655 case DRM_MODE_CONNECTOR_VGA:
656 return ATOM_ENCODER_MODE_CRT;
658 case DRM_MODE_CONNECTOR_Composite:
659 case DRM_MODE_CONNECTOR_SVIDEO:
660 case DRM_MODE_CONNECTOR_9PinDIN:
662 return ATOM_ENCODER_MODE_TV;
663 /*return ATOM_ENCODER_MODE_CV;*/
669 * DIG Encoder/Transmitter Setup
672 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
673 * Supports up to 3 digital outputs
674 * - 2 DIG encoder blocks.
675 * DIG1 can drive UNIPHY link A or link B
676 * DIG2 can drive UNIPHY link B or LVTMA
679 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
680 * Supports up to 5 digital outputs
681 * - 2 DIG encoder blocks.
682 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
685 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
686 * Supports up to 6 digital outputs
687 * - 6 DIG encoder blocks.
688 * - DIG to PHY mapping is hardcoded
689 * DIG1 drives UNIPHY0 link A, A+B
690 * DIG2 drives UNIPHY0 link B
691 * DIG3 drives UNIPHY1 link A, A+B
692 * DIG4 drives UNIPHY1 link B
693 * DIG5 drives UNIPHY2 link A, A+B
694 * DIG6 drives UNIPHY2 link B
697 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
699 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
700 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
701 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
702 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
705 union dig_encoder_control {
706 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
707 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
708 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
712 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
714 struct drm_device *dev = encoder->dev;
715 struct radeon_device *rdev = dev->dev_private;
716 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
718 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
719 union dig_encoder_control args;
723 int dp_lane_count = 0;
726 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
727 struct radeon_connector_atom_dig *dig_connector =
728 radeon_connector->con_priv;
730 dp_clock = dig_connector->dp_clock;
731 dp_lane_count = dig_connector->dp_lane_count;
734 /* no dig encoder assigned */
735 if (dig->dig_encoder == -1)
738 memset(&args, 0, sizeof(args));
740 if (ASIC_IS_DCE4(rdev))
741 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
743 if (dig->dig_encoder)
744 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
746 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
749 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
752 args.v1.ucAction = action;
753 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
754 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
756 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
757 if (dp_clock == 270000)
758 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
759 args.v1.ucLaneNum = dp_lane_count;
760 } else if (radeon_encoder->pixel_clock > 165000)
761 args.v1.ucLaneNum = 8;
763 args.v1.ucLaneNum = 4;
765 if (ASIC_IS_DCE4(rdev)) {
766 args.v3.acConfig.ucDigSel = dig->dig_encoder;
767 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
769 switch (radeon_encoder->encoder_id) {
770 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
771 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
775 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
777 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
778 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
782 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
784 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
787 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
791 union dig_transmitter_control {
792 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
793 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
794 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
798 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
800 struct drm_device *dev = encoder->dev;
801 struct radeon_device *rdev = dev->dev_private;
802 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
803 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
804 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
805 union dig_transmitter_control args;
811 int dp_lane_count = 0;
812 int connector_object_id = 0;
813 int igp_lane_info = 0;
816 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
817 struct radeon_connector_atom_dig *dig_connector =
818 radeon_connector->con_priv;
820 dp_clock = dig_connector->dp_clock;
821 dp_lane_count = dig_connector->dp_lane_count;
822 connector_object_id =
823 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
824 igp_lane_info = dig_connector->igp_lane_info;
827 /* no dig encoder assigned */
828 if (dig->dig_encoder == -1)
831 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
834 memset(&args, 0, sizeof(args));
836 switch (radeon_encoder->encoder_id) {
837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
838 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
840 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
843 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
847 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
850 args.v1.ucAction = action;
851 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
852 args.v1.usInitInfo = connector_object_id;
853 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
854 args.v1.asMode.ucLaneSel = lane_num;
855 args.v1.asMode.ucLaneSet = lane_set;
858 args.v1.usPixelClock =
859 cpu_to_le16(dp_clock / 10);
860 else if (radeon_encoder->pixel_clock > 165000)
861 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
863 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
865 if (ASIC_IS_DCE4(rdev)) {
867 args.v3.ucLaneNum = dp_lane_count;
868 else if (radeon_encoder->pixel_clock > 165000)
869 args.v3.ucLaneNum = 8;
871 args.v3.ucLaneNum = 4;
874 args.v3.acConfig.ucLinkSel = 1;
875 args.v3.acConfig.ucEncoderSel = 1;
878 /* Select the PLL for the PHY
879 * DP PHY should be clocked from external src if there is
883 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
884 pll_id = radeon_crtc->pll_id;
886 if (is_dp && rdev->clock.dp_extclk)
887 args.v3.acConfig.ucRefClkSource = 2; /* external src */
889 args.v3.acConfig.ucRefClkSource = pll_id;
891 switch (radeon_encoder->encoder_id) {
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
893 args.v3.acConfig.ucTransmitterSel = 0;
895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
896 args.v3.acConfig.ucTransmitterSel = 1;
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
899 args.v3.acConfig.ucTransmitterSel = 2;
904 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
905 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
906 if (dig->coherent_mode)
907 args.v3.acConfig.fCoherentMode = 1;
908 if (radeon_encoder->pixel_clock > 165000)
909 args.v3.acConfig.fDualLinkConnector = 1;
911 } else if (ASIC_IS_DCE32(rdev)) {
912 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
914 args.v2.acConfig.ucLinkSel = 1;
916 switch (radeon_encoder->encoder_id) {
917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
918 args.v2.acConfig.ucTransmitterSel = 0;
920 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
921 args.v2.acConfig.ucTransmitterSel = 1;
923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
924 args.v2.acConfig.ucTransmitterSel = 2;
929 args.v2.acConfig.fCoherentMode = 1;
930 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
931 if (dig->coherent_mode)
932 args.v2.acConfig.fCoherentMode = 1;
933 if (radeon_encoder->pixel_clock > 165000)
934 args.v2.acConfig.fDualLinkConnector = 1;
937 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
939 if (dig->dig_encoder)
940 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
942 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
944 if ((rdev->flags & RADEON_IS_IGP) &&
945 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
946 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
947 if (igp_lane_info & 0x1)
948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
949 else if (igp_lane_info & 0x2)
950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
951 else if (igp_lane_info & 0x4)
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
953 else if (igp_lane_info & 0x8)
954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
956 if (igp_lane_info & 0x3)
957 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
958 else if (igp_lane_info & 0xc)
959 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
969 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
970 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
971 if (dig->coherent_mode)
972 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
973 if (radeon_encoder->pixel_clock > 165000)
974 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
978 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
982 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
984 struct drm_device *dev = encoder->dev;
985 struct radeon_device *rdev = dev->dev_private;
986 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
988 ENABLE_YUV_PS_ALLOCATION args;
989 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
992 memset(&args, 0, sizeof(args));
994 if (rdev->family >= CHIP_R600)
995 reg = R600_BIOS_3_SCRATCH;
997 reg = RADEON_BIOS_3_SCRATCH;
999 /* XXX: fix up scratch reg handling */
1001 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1002 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1003 (radeon_crtc->crtc_id << 18)));
1004 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1005 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1010 args.ucEnable = ATOM_ENABLE;
1011 args.ucCRTC = radeon_crtc->crtc_id;
1013 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1019 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1021 struct drm_device *dev = encoder->dev;
1022 struct radeon_device *rdev = dev->dev_private;
1023 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1024 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1026 bool is_dig = false;
1028 memset(&args, 0, sizeof(args));
1030 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1031 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1032 radeon_encoder->active_device);
1033 switch (radeon_encoder->encoder_id) {
1034 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1035 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1036 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1038 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1041 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1044 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1045 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1047 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1049 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1050 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1052 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1053 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1054 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1056 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1058 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1059 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1060 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1061 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1062 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1063 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1065 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1067 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1068 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1069 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1070 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1071 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1072 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1074 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1080 case DRM_MODE_DPMS_ON:
1081 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1082 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1083 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1085 dp_link_train(encoder, connector);
1086 if (ASIC_IS_DCE4(rdev))
1087 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1090 case DRM_MODE_DPMS_STANDBY:
1091 case DRM_MODE_DPMS_SUSPEND:
1092 case DRM_MODE_DPMS_OFF:
1093 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1094 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1095 if (ASIC_IS_DCE4(rdev))
1096 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1102 case DRM_MODE_DPMS_ON:
1103 args.ucAction = ATOM_ENABLE;
1105 case DRM_MODE_DPMS_STANDBY:
1106 case DRM_MODE_DPMS_SUSPEND:
1107 case DRM_MODE_DPMS_OFF:
1108 args.ucAction = ATOM_DISABLE;
1111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1113 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1117 union crtc_source_param {
1118 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1119 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1123 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1125 struct drm_device *dev = encoder->dev;
1126 struct radeon_device *rdev = dev->dev_private;
1127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1128 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1129 union crtc_source_param args;
1130 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1132 struct radeon_encoder_atom_dig *dig;
1134 memset(&args, 0, sizeof(args));
1136 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1144 if (ASIC_IS_AVIVO(rdev))
1145 args.v1.ucCRTC = radeon_crtc->crtc_id;
1147 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1148 args.v1.ucCRTC = radeon_crtc->crtc_id;
1150 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1153 switch (radeon_encoder->encoder_id) {
1154 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1156 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1158 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1159 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1160 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1161 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1163 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1165 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1166 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1168 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1170 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1172 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1173 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1174 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1175 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1177 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1179 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1180 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1181 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1182 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1183 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1184 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1186 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1191 args.v2.ucCRTC = radeon_crtc->crtc_id;
1192 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1193 switch (radeon_encoder->encoder_id) {
1194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1196 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1198 dig = radeon_encoder->enc_priv;
1199 switch (dig->dig_encoder) {
1201 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1204 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1207 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1210 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1213 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1216 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1220 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1221 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1223 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1224 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1225 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1226 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1227 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1229 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1231 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1232 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1233 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1234 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1235 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1237 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1244 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1248 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1250 /* update scratch regs with new routing */
1251 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1255 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1256 struct drm_display_mode *mode)
1258 struct drm_device *dev = encoder->dev;
1259 struct radeon_device *rdev = dev->dev_private;
1260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1261 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1263 /* Funky macbooks */
1264 if ((dev->pdev->device == 0x71C5) &&
1265 (dev->pdev->subsystem_vendor == 0x106b) &&
1266 (dev->pdev->subsystem_device == 0x0080)) {
1267 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1268 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1270 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1271 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1273 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1277 /* set scaler clears this on some chips */
1278 /* XXX check DCE4 */
1279 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1280 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1281 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1282 AVIVO_D1MODE_INTERLEAVE_EN);
1286 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1288 struct drm_device *dev = encoder->dev;
1289 struct radeon_device *rdev = dev->dev_private;
1290 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1292 struct drm_encoder *test_encoder;
1293 struct radeon_encoder_atom_dig *dig;
1294 uint32_t dig_enc_in_use = 0;
1296 if (ASIC_IS_DCE4(rdev)) {
1297 dig = radeon_encoder->enc_priv;
1298 switch (radeon_encoder->encoder_id) {
1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1320 /* on DCE32 and encoder can driver any block so just crtc id */
1321 if (ASIC_IS_DCE32(rdev)) {
1322 return radeon_crtc->crtc_id;
1325 /* on DCE3 - LVTMA can only be driven by DIGB */
1326 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1327 struct radeon_encoder *radeon_test_encoder;
1329 if (encoder == test_encoder)
1332 if (!radeon_encoder_is_digital(test_encoder))
1335 radeon_test_encoder = to_radeon_encoder(test_encoder);
1336 dig = radeon_test_encoder->enc_priv;
1338 if (dig->dig_encoder >= 0)
1339 dig_enc_in_use |= (1 << dig->dig_encoder);
1342 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1343 if (dig_enc_in_use & 0x2)
1344 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1347 if (!(dig_enc_in_use & 1))
1353 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1354 struct drm_display_mode *mode,
1355 struct drm_display_mode *adjusted_mode)
1357 struct drm_device *dev = encoder->dev;
1358 struct radeon_device *rdev = dev->dev_private;
1359 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1361 radeon_encoder->pixel_clock = adjusted_mode->clock;
1363 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1364 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1365 atombios_yuv_setup(encoder, true);
1367 atombios_yuv_setup(encoder, false);
1370 switch (radeon_encoder->encoder_id) {
1371 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1373 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1374 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1375 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1377 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1378 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1380 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1381 if (ASIC_IS_DCE4(rdev)) {
1382 /* disable the transmitter */
1383 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1384 /* setup and enable the encoder */
1385 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1387 /* init and enable the transmitter */
1388 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1389 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1391 /* disable the encoder and transmitter */
1392 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1393 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1395 /* setup and enable the encoder and transmitter */
1396 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1397 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1398 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1399 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1402 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1403 atombios_ddia_setup(encoder, ATOM_ENABLE);
1405 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1407 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1409 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1410 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1411 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1413 atombios_dac_setup(encoder, ATOM_ENABLE);
1414 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1415 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1416 atombios_tv_setup(encoder, ATOM_ENABLE);
1418 atombios_tv_setup(encoder, ATOM_DISABLE);
1422 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1424 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1425 r600_hdmi_enable(encoder);
1426 r600_hdmi_setmode(encoder, adjusted_mode);
1431 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1433 struct drm_device *dev = encoder->dev;
1434 struct radeon_device *rdev = dev->dev_private;
1435 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1436 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1438 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1439 ATOM_DEVICE_CV_SUPPORT |
1440 ATOM_DEVICE_CRT_SUPPORT)) {
1441 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1442 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1445 memset(&args, 0, sizeof(args));
1447 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1450 args.sDacload.ucMisc = 0;
1452 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1453 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1454 args.sDacload.ucDacType = ATOM_DAC_A;
1456 args.sDacload.ucDacType = ATOM_DAC_B;
1458 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1459 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1460 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1461 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1462 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1463 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1465 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1466 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1467 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1469 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1472 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1479 static enum drm_connector_status
1480 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1482 struct drm_device *dev = encoder->dev;
1483 struct radeon_device *rdev = dev->dev_private;
1484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1485 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1486 uint32_t bios_0_scratch;
1488 if (!atombios_dac_load_detect(encoder, connector)) {
1489 DRM_DEBUG_KMS("detect returned false \n");
1490 return connector_status_unknown;
1493 if (rdev->family >= CHIP_R600)
1494 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1496 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1498 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1499 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1500 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1501 return connector_status_connected;
1503 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1504 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1505 return connector_status_connected;
1507 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1508 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1509 return connector_status_connected;
1511 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1512 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1513 return connector_status_connected; /* CTV */
1514 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1515 return connector_status_connected; /* STV */
1517 return connector_status_disconnected;
1520 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1522 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1524 if (radeon_encoder->active_device &
1525 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1528 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1531 radeon_atom_output_lock(encoder, true);
1532 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1534 /* this is needed for the pll/ss setup to work correctly in some cases */
1535 atombios_set_encoder_crtc_source(encoder);
1538 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1540 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1541 radeon_atom_output_lock(encoder, false);
1544 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1546 struct drm_device *dev = encoder->dev;
1547 struct radeon_device *rdev = dev->dev_private;
1548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1549 struct radeon_encoder_atom_dig *dig;
1550 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1552 switch (radeon_encoder->encoder_id) {
1553 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1555 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1556 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1557 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1559 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1560 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1561 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1563 if (ASIC_IS_DCE4(rdev))
1564 /* disable the transmitter */
1565 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1567 /* disable the encoder and transmitter */
1568 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1569 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1572 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1573 atombios_ddia_setup(encoder, ATOM_DISABLE);
1575 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1577 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1579 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1580 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1581 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1583 atombios_dac_setup(encoder, ATOM_DISABLE);
1584 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1585 atombios_tv_setup(encoder, ATOM_DISABLE);
1589 if (radeon_encoder_is_digital(encoder)) {
1590 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1591 r600_hdmi_disable(encoder);
1592 dig = radeon_encoder->enc_priv;
1593 dig->dig_encoder = -1;
1595 radeon_encoder->active_device = 0;
1598 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1599 .dpms = radeon_atom_encoder_dpms,
1600 .mode_fixup = radeon_atom_mode_fixup,
1601 .prepare = radeon_atom_encoder_prepare,
1602 .mode_set = radeon_atom_encoder_mode_set,
1603 .commit = radeon_atom_encoder_commit,
1604 .disable = radeon_atom_encoder_disable,
1605 /* no detect for TMDS/LVDS yet */
1608 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1609 .dpms = radeon_atom_encoder_dpms,
1610 .mode_fixup = radeon_atom_mode_fixup,
1611 .prepare = radeon_atom_encoder_prepare,
1612 .mode_set = radeon_atom_encoder_mode_set,
1613 .commit = radeon_atom_encoder_commit,
1614 .detect = radeon_atom_dac_detect,
1617 void radeon_enc_destroy(struct drm_encoder *encoder)
1619 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1620 kfree(radeon_encoder->enc_priv);
1621 drm_encoder_cleanup(encoder);
1622 kfree(radeon_encoder);
1625 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1626 .destroy = radeon_enc_destroy,
1629 struct radeon_encoder_atom_dac *
1630 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1632 struct drm_device *dev = radeon_encoder->base.dev;
1633 struct radeon_device *rdev = dev->dev_private;
1634 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1639 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1643 struct radeon_encoder_atom_dig *
1644 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1646 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1647 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1652 /* coherent mode by default */
1653 dig->coherent_mode = true;
1654 dig->dig_encoder = -1;
1656 if (encoder_enum == 2)
1665 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1667 struct radeon_device *rdev = dev->dev_private;
1668 struct drm_encoder *encoder;
1669 struct radeon_encoder *radeon_encoder;
1671 /* see if we already added it */
1672 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1673 radeon_encoder = to_radeon_encoder(encoder);
1674 if (radeon_encoder->encoder_enum == encoder_enum) {
1675 radeon_encoder->devices |= supported_device;
1682 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1683 if (!radeon_encoder)
1686 encoder = &radeon_encoder->base;
1687 switch (rdev->num_crtc) {
1689 encoder->possible_crtcs = 0x1;
1693 encoder->possible_crtcs = 0x3;
1696 encoder->possible_crtcs = 0x3f;
1700 radeon_encoder->enc_priv = NULL;
1702 radeon_encoder->encoder_enum = encoder_enum;
1703 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1704 radeon_encoder->devices = supported_device;
1705 radeon_encoder->rmx_type = RMX_OFF;
1706 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1708 switch (radeon_encoder->encoder_id) {
1709 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1710 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1711 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1712 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1713 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1714 radeon_encoder->rmx_type = RMX_FULL;
1715 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1716 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1718 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1719 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1720 if (ASIC_IS_AVIVO(rdev))
1721 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1723 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1725 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1726 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1727 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1728 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1730 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1731 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1733 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1734 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1735 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1737 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1739 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1744 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1745 radeon_encoder->rmx_type = RMX_FULL;
1746 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1747 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1749 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1750 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1751 if (ASIC_IS_AVIVO(rdev))
1752 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1754 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);