2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <asm/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/list.h>
35 #include <linux/kref.h>
38 #include "radeon_reg.h"
41 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
43 unsigned long irq_flags;
45 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
47 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
50 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
51 if (!rdev->cp.ready) {
52 /* FIXME: cp is not running assume everythings is done right
55 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
57 radeon_fence_ring_emit(rdev, fence);
60 fence->timeout = jiffies + ((2000 * HZ) / 1000);
61 list_del(&fence->list);
62 list_add_tail(&fence->list, &rdev->fence_drv.emited);
63 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
67 static bool radeon_fence_poll_locked(struct radeon_device *rdev)
69 struct radeon_fence *fence;
70 struct list_head *i, *n;
80 seq = RREG32(rdev->fence_drv.scratch_reg);
81 rdev->fence_drv.last_seq = seq;
83 list_for_each(i, &rdev->fence_drv.emited) {
84 fence = list_entry(i, struct radeon_fence, list);
85 if (fence->seq == seq) {
90 /* all fence previous to this one are considered as signaled */
96 list_add_tail(i, &rdev->fence_drv.signaled);
97 fence = list_entry(i, struct radeon_fence, list);
98 fence->signaled = true;
100 } while (i != &rdev->fence_drv.emited);
106 static void radeon_fence_destroy(struct kref *kref)
108 unsigned long irq_flags;
109 struct radeon_fence *fence;
111 fence = container_of(kref, struct radeon_fence, kref);
112 write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
113 list_del(&fence->list);
114 fence->emited = false;
115 write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
119 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
121 unsigned long irq_flags;
123 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
124 if ((*fence) == NULL) {
127 kref_init(&((*fence)->kref));
128 (*fence)->rdev = rdev;
129 (*fence)->emited = false;
130 (*fence)->signaled = false;
132 INIT_LIST_HEAD(&(*fence)->list);
134 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
135 list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
136 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
141 bool radeon_fence_signaled(struct radeon_fence *fence)
143 struct radeon_device *rdev = fence->rdev;
144 unsigned long irq_flags;
145 bool signaled = false;
147 if (rdev->gpu_lockup) {
153 write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
154 signaled = fence->signaled;
155 /* if we are shuting down report all fence as signaled */
156 if (fence->rdev->shutdown) {
159 if (!fence->emited) {
160 WARN(1, "Querying an unemited fence : %p !\n", fence);
164 radeon_fence_poll_locked(fence->rdev);
165 signaled = fence->signaled;
167 write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
171 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
173 struct radeon_device *rdev;
174 unsigned long cur_jiffies;
175 unsigned long timeout;
176 bool expired = false;
180 WARN(1, "Querying an invalid fence : %p !\n", fence);
184 if (radeon_fence_signaled(fence)) {
189 cur_jiffies = jiffies;
191 if (time_after(fence->timeout, cur_jiffies)) {
192 timeout = fence->timeout - cur_jiffies;
196 radeon_irq_kms_sw_irq_get(rdev);
197 r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
198 radeon_fence_signaled(fence), timeout);
199 radeon_irq_kms_sw_irq_put(rdev);
203 radeon_irq_kms_sw_irq_get(rdev);
204 r = wait_event_timeout(rdev->fence_drv.queue,
205 radeon_fence_signaled(fence), timeout);
206 radeon_irq_kms_sw_irq_put(rdev);
208 if (unlikely(!radeon_fence_signaled(fence))) {
209 if (unlikely(r == 0)) {
212 if (unlikely(expired)) {
214 if (time_after(cur_jiffies, fence->timeout)) {
215 timeout = cur_jiffies - fence->timeout;
217 timeout = jiffies_to_msecs(timeout);
219 DRM_ERROR("fence(%p:0x%08X) %lums timeout "
220 "going to reset GPU\n",
221 fence, fence->seq, timeout);
222 radeon_gpu_reset(rdev);
223 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
228 if (unlikely(expired)) {
229 rdev->fence_drv.count_timeout++;
230 cur_jiffies = jiffies;
232 if (time_after(cur_jiffies, fence->timeout)) {
233 timeout = cur_jiffies - fence->timeout;
235 timeout = jiffies_to_msecs(timeout);
236 DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
237 fence, fence->seq, timeout);
238 DRM_ERROR("last signaled fence(0x%08X)\n",
239 rdev->fence_drv.last_seq);
244 int radeon_fence_wait_next(struct radeon_device *rdev)
246 unsigned long irq_flags;
247 struct radeon_fence *fence;
250 if (rdev->gpu_lockup) {
253 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
254 if (list_empty(&rdev->fence_drv.emited)) {
255 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
258 fence = list_entry(rdev->fence_drv.emited.next,
259 struct radeon_fence, list);
260 radeon_fence_ref(fence);
261 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
262 r = radeon_fence_wait(fence, false);
263 radeon_fence_unref(&fence);
267 int radeon_fence_wait_last(struct radeon_device *rdev)
269 unsigned long irq_flags;
270 struct radeon_fence *fence;
273 if (rdev->gpu_lockup) {
276 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
277 if (list_empty(&rdev->fence_drv.emited)) {
278 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
281 fence = list_entry(rdev->fence_drv.emited.prev,
282 struct radeon_fence, list);
283 radeon_fence_ref(fence);
284 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
285 r = radeon_fence_wait(fence, false);
286 radeon_fence_unref(&fence);
290 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
292 kref_get(&fence->kref);
296 void radeon_fence_unref(struct radeon_fence **fence)
298 struct radeon_fence *tmp = *fence;
302 kref_put(&tmp->kref, &radeon_fence_destroy);
306 void radeon_fence_process(struct radeon_device *rdev)
308 unsigned long irq_flags;
311 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
312 wake = radeon_fence_poll_locked(rdev);
313 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
315 wake_up_all(&rdev->fence_drv.queue);
319 int radeon_fence_driver_init(struct radeon_device *rdev)
321 unsigned long irq_flags;
324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
327 dev_err(rdev->dev, "fence failed to get scratch register\n");
328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
331 WREG32(rdev->fence_drv.scratch_reg, 0);
332 atomic_set(&rdev->fence_drv.seq, 0);
333 INIT_LIST_HEAD(&rdev->fence_drv.created);
334 INIT_LIST_HEAD(&rdev->fence_drv.emited);
335 INIT_LIST_HEAD(&rdev->fence_drv.signaled);
336 rdev->fence_drv.count_timeout = 0;
337 init_waitqueue_head(&rdev->fence_drv.queue);
338 rdev->fence_drv.initialized = true;
339 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
340 if (radeon_debugfs_fence_init(rdev)) {
341 dev_err(rdev->dev, "fence debugfs file creation failed\n");
346 void radeon_fence_driver_fini(struct radeon_device *rdev)
348 unsigned long irq_flags;
350 if (!rdev->fence_drv.initialized)
352 wake_up_all(&rdev->fence_drv.queue);
353 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
354 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
355 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
356 rdev->fence_drv.initialized = false;
363 #if defined(CONFIG_DEBUG_FS)
364 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
366 struct drm_info_node *node = (struct drm_info_node *)m->private;
367 struct drm_device *dev = node->minor->dev;
368 struct radeon_device *rdev = dev->dev_private;
369 struct radeon_fence *fence;
371 seq_printf(m, "Last signaled fence 0x%08X\n",
372 RREG32(rdev->fence_drv.scratch_reg));
373 if (!list_empty(&rdev->fence_drv.emited)) {
374 fence = list_entry(rdev->fence_drv.emited.prev,
375 struct radeon_fence, list);
376 seq_printf(m, "Last emited fence %p with 0x%08X\n",
382 static struct drm_info_list radeon_debugfs_fence_list[] = {
383 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
387 int radeon_debugfs_fence_init(struct radeon_device *rdev)
389 #if defined(CONFIG_DEBUG_FS)
390 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);