2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include <drm/drm_edid.h>
30 #include <drm/radeon_drm.h>
34 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
35 struct i2c_msg *msgs, int num);
36 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
42 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
47 struct i2c_msg msgs[] = {
62 /* on hw with routers, select right port */
63 if (radeon_connector->router.ddc_valid)
64 radeon_router_select_ddc_port(radeon_connector);
67 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
69 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
73 /* Couldn't find an accessible DDC on this connector */
75 /* Probe also for valid EDID header
76 * EDID header starts with:
77 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
78 * Only the first 6 bytes must be valid as
79 * drm_edid_block_valid() can fix the last 2 bytes */
80 if (drm_edid_header_is_valid(buf) < 6) {
81 /* Couldn't find an accessible EDID on this
90 static int pre_xfer(struct i2c_adapter *i2c_adap)
92 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
93 struct radeon_device *rdev = i2c->dev->dev_private;
94 struct radeon_i2c_bus_rec *rec = &i2c->rec;
97 /* RV410 appears to have a bug where the hw i2c in reset
98 * holds the i2c port in a bad state - switch hw i2c away before
99 * doing DDC - do this for all r200s/r300s/r400s for safety sake
101 if (rec->hw_capable) {
102 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
105 if (rdev->family >= CHIP_RV350)
106 reg = RADEON_GPIO_MONID;
107 else if ((rdev->family == CHIP_R300) ||
108 (rdev->family == CHIP_R350))
109 reg = RADEON_GPIO_DVI_DDC;
111 reg = RADEON_GPIO_CRT2_DDC;
113 mutex_lock(&rdev->dc_hw_i2c_mutex);
114 if (rec->a_clk_reg == reg) {
115 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
116 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
118 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
119 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
121 mutex_unlock(&rdev->dc_hw_i2c_mutex);
125 /* switch the pads to ddc mode */
126 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
127 temp = RREG32(rec->mask_clk_reg);
129 WREG32(rec->mask_clk_reg, temp);
132 /* clear the output pin values */
133 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
134 WREG32(rec->a_clk_reg, temp);
136 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
137 WREG32(rec->a_data_reg, temp);
139 /* set the pins to input */
140 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
141 WREG32(rec->en_clk_reg, temp);
143 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
144 WREG32(rec->en_data_reg, temp);
146 /* mask the gpio pins for software use */
147 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
148 WREG32(rec->mask_clk_reg, temp);
149 temp = RREG32(rec->mask_clk_reg);
151 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
152 WREG32(rec->mask_data_reg, temp);
153 temp = RREG32(rec->mask_data_reg);
158 static void post_xfer(struct i2c_adapter *i2c_adap)
160 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
161 struct radeon_device *rdev = i2c->dev->dev_private;
162 struct radeon_i2c_bus_rec *rec = &i2c->rec;
165 /* unmask the gpio pins for software use */
166 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
167 WREG32(rec->mask_clk_reg, temp);
168 temp = RREG32(rec->mask_clk_reg);
170 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
171 WREG32(rec->mask_data_reg, temp);
172 temp = RREG32(rec->mask_data_reg);
175 static int get_clock(void *i2c_priv)
177 struct radeon_i2c_chan *i2c = i2c_priv;
178 struct radeon_device *rdev = i2c->dev->dev_private;
179 struct radeon_i2c_bus_rec *rec = &i2c->rec;
182 /* read the value off the pin */
183 val = RREG32(rec->y_clk_reg);
184 val &= rec->y_clk_mask;
190 static int get_data(void *i2c_priv)
192 struct radeon_i2c_chan *i2c = i2c_priv;
193 struct radeon_device *rdev = i2c->dev->dev_private;
194 struct radeon_i2c_bus_rec *rec = &i2c->rec;
197 /* read the value off the pin */
198 val = RREG32(rec->y_data_reg);
199 val &= rec->y_data_mask;
204 static void set_clock(void *i2c_priv, int clock)
206 struct radeon_i2c_chan *i2c = i2c_priv;
207 struct radeon_device *rdev = i2c->dev->dev_private;
208 struct radeon_i2c_bus_rec *rec = &i2c->rec;
211 /* set pin direction */
212 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
213 val |= clock ? 0 : rec->en_clk_mask;
214 WREG32(rec->en_clk_reg, val);
217 static void set_data(void *i2c_priv, int data)
219 struct radeon_i2c_chan *i2c = i2c_priv;
220 struct radeon_device *rdev = i2c->dev->dev_private;
221 struct radeon_i2c_bus_rec *rec = &i2c->rec;
224 /* set pin direction */
225 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
226 val |= data ? 0 : rec->en_data_mask;
227 WREG32(rec->en_data_reg, val);
232 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
234 u32 sclk = rdev->pm.current_sclk;
240 switch (rdev->family) {
254 nm = (sclk * 10) / (i2c_clock * 4);
255 for (loop = 1; loop < 255; loop++) {
256 if ((nm / loop) < loop)
261 prescale = m | (n << 8);
269 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
283 if (rdev->family == CHIP_R520)
284 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
286 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
312 DRM_ERROR("i2c: unhandled radeon chip\n");
319 /* hw i2c engine for r1xx-4xx hardware
320 * hw can buffer up to 15 bytes
322 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
323 struct i2c_msg *msgs, int num)
325 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
326 struct radeon_device *rdev = i2c->dev->dev_private;
327 struct radeon_i2c_bus_rec *rec = &i2c->rec;
329 int i, j, k, ret = num;
331 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
334 mutex_lock(&rdev->dc_hw_i2c_mutex);
335 /* take the pm lock since we need a constant sclk */
336 mutex_lock(&rdev->pm.mutex);
338 prescale = radeon_get_i2c_prescale(rdev);
340 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
341 RADEON_I2C_DRIVE_EN |
346 if (rdev->is_atom_bios) {
347 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
348 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
352 i2c_cntl_0 = RADEON_I2C_CNTL_0;
353 i2c_cntl_1 = RADEON_I2C_CNTL_1;
354 i2c_data = RADEON_I2C_DATA;
356 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
357 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
358 i2c_data = RADEON_DVI_I2C_DATA;
360 switch (rdev->family) {
367 switch (rec->mask_clk_reg) {
368 case RADEON_GPIO_DVI_DDC:
369 /* no gpio select bit */
372 DRM_ERROR("gpio not supported with hw i2c\n");
378 /* only bit 4 on r200 */
379 switch (rec->mask_clk_reg) {
380 case RADEON_GPIO_DVI_DDC:
381 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
383 case RADEON_GPIO_MONID:
384 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
387 DRM_ERROR("gpio not supported with hw i2c\n");
395 switch (rec->mask_clk_reg) {
396 case RADEON_GPIO_DVI_DDC:
397 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
399 case RADEON_GPIO_VGA_DDC:
400 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
402 case RADEON_GPIO_CRT2_DDC:
403 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
406 DRM_ERROR("gpio not supported with hw i2c\n");
413 /* only bit 4 on r300/r350 */
414 switch (rec->mask_clk_reg) {
415 case RADEON_GPIO_VGA_DDC:
416 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
418 case RADEON_GPIO_DVI_DDC:
419 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
422 DRM_ERROR("gpio not supported with hw i2c\n");
435 switch (rec->mask_clk_reg) {
436 case RADEON_GPIO_VGA_DDC:
437 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
439 case RADEON_GPIO_DVI_DDC:
440 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
442 case RADEON_GPIO_MONID:
443 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
446 DRM_ERROR("gpio not supported with hw i2c\n");
452 DRM_ERROR("unsupported asic\n");
459 /* check for bus probe */
461 if ((num == 1) && (p->len == 0)) {
462 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
465 RADEON_I2C_SOFT_RST));
466 WREG32(i2c_data, (p->addr << 1) & 0xff);
468 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
469 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
471 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
472 WREG32(i2c_cntl_0, reg);
473 for (k = 0; k < 32; k++) {
475 tmp = RREG32(i2c_cntl_0);
476 if (tmp & RADEON_I2C_GO)
478 tmp = RREG32(i2c_cntl_0);
479 if (tmp & RADEON_I2C_DONE)
482 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
483 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
491 for (i = 0; i < num; i++) {
493 for (j = 0; j < p->len; j++) {
494 if (p->flags & I2C_M_RD) {
495 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
498 RADEON_I2C_SOFT_RST));
499 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
500 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
501 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
503 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
504 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
505 for (k = 0; k < 32; k++) {
507 tmp = RREG32(i2c_cntl_0);
508 if (tmp & RADEON_I2C_GO)
510 tmp = RREG32(i2c_cntl_0);
511 if (tmp & RADEON_I2C_DONE)
514 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
515 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
520 p->buf[j] = RREG32(i2c_data) & 0xff;
522 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
525 RADEON_I2C_SOFT_RST));
526 WREG32(i2c_data, (p->addr << 1) & 0xff);
527 WREG32(i2c_data, p->buf[j]);
528 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
529 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
531 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
532 WREG32(i2c_cntl_0, reg);
533 for (k = 0; k < 32; k++) {
535 tmp = RREG32(i2c_cntl_0);
536 if (tmp & RADEON_I2C_GO)
538 tmp = RREG32(i2c_cntl_0);
539 if (tmp & RADEON_I2C_DONE)
542 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
543 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
553 WREG32(i2c_cntl_0, 0);
554 WREG32(i2c_cntl_1, 0);
555 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
558 RADEON_I2C_SOFT_RST));
560 if (rdev->is_atom_bios) {
561 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
562 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
563 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
566 mutex_unlock(&rdev->pm.mutex);
567 mutex_unlock(&rdev->dc_hw_i2c_mutex);
572 /* hw i2c engine for r5xx hardware
573 * hw can buffer up to 15 bytes
575 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
576 struct i2c_msg *msgs, int num)
578 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
579 struct radeon_device *rdev = i2c->dev->dev_private;
580 struct radeon_i2c_bus_rec *rec = &i2c->rec;
582 int i, j, remaining, current_count, buffer_offset, ret = num;
587 mutex_lock(&rdev->dc_hw_i2c_mutex);
588 /* take the pm lock since we need a constant sclk */
589 mutex_lock(&rdev->pm.mutex);
591 prescale = radeon_get_i2c_prescale(rdev);
593 /* clear gpio mask bits */
594 tmp = RREG32(rec->mask_clk_reg);
595 tmp &= ~rec->mask_clk_mask;
596 WREG32(rec->mask_clk_reg, tmp);
597 tmp = RREG32(rec->mask_clk_reg);
599 tmp = RREG32(rec->mask_data_reg);
600 tmp &= ~rec->mask_data_mask;
601 WREG32(rec->mask_data_reg, tmp);
602 tmp = RREG32(rec->mask_data_reg);
604 /* clear pin values */
605 tmp = RREG32(rec->a_clk_reg);
606 tmp &= ~rec->a_clk_mask;
607 WREG32(rec->a_clk_reg, tmp);
608 tmp = RREG32(rec->a_clk_reg);
610 tmp = RREG32(rec->a_data_reg);
611 tmp &= ~rec->a_data_mask;
612 WREG32(rec->a_data_reg, tmp);
613 tmp = RREG32(rec->a_data_reg);
615 /* set the pins to input */
616 tmp = RREG32(rec->en_clk_reg);
617 tmp &= ~rec->en_clk_mask;
618 WREG32(rec->en_clk_reg, tmp);
619 tmp = RREG32(rec->en_clk_reg);
621 tmp = RREG32(rec->en_data_reg);
622 tmp &= ~rec->en_data_mask;
623 WREG32(rec->en_data_reg, tmp);
624 tmp = RREG32(rec->en_data_reg);
627 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
628 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
629 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
630 saved2 = RREG32(0x494);
631 WREG32(0x494, saved2 | 0x1);
633 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
634 for (i = 0; i < 50; i++) {
636 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
640 DRM_ERROR("failed to get i2c bus\n");
645 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
646 switch (rec->mask_clk_reg) {
647 case AVIVO_DC_GPIO_DDC1_MASK:
648 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
650 case AVIVO_DC_GPIO_DDC2_MASK:
651 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
653 case AVIVO_DC_GPIO_DDC3_MASK:
654 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
657 DRM_ERROR("gpio not supported with hw i2c\n");
662 /* check for bus probe */
664 if ((num == 1) && (p->len == 0)) {
665 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
668 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
670 WREG32(AVIVO_DC_I2C_RESET, 0);
672 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
673 WREG32(AVIVO_DC_I2C_DATA, 0);
675 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
676 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
677 AVIVO_DC_I2C_DATA_COUNT(1) |
679 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
680 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
681 for (j = 0; j < 200; j++) {
683 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
684 if (tmp & AVIVO_DC_I2C_GO)
686 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
687 if (tmp & AVIVO_DC_I2C_DONE)
690 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
691 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
699 for (i = 0; i < num; i++) {
703 if (p->flags & I2C_M_RD) {
708 current_count = remaining;
709 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
712 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
714 WREG32(AVIVO_DC_I2C_RESET, 0);
716 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
717 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
718 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
719 AVIVO_DC_I2C_DATA_COUNT(current_count) |
721 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
722 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
723 for (j = 0; j < 200; j++) {
725 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
726 if (tmp & AVIVO_DC_I2C_GO)
728 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
729 if (tmp & AVIVO_DC_I2C_DONE)
732 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
733 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
738 for (j = 0; j < current_count; j++)
739 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
740 remaining -= current_count;
741 buffer_offset += current_count;
748 current_count = remaining;
749 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
752 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
754 WREG32(AVIVO_DC_I2C_RESET, 0);
756 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
757 for (j = 0; j < current_count; j++)
758 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
760 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
761 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
762 AVIVO_DC_I2C_DATA_COUNT(current_count) |
764 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
765 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
766 for (j = 0; j < 200; j++) {
768 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
769 if (tmp & AVIVO_DC_I2C_GO)
771 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
772 if (tmp & AVIVO_DC_I2C_DONE)
775 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
776 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
781 remaining -= current_count;
782 buffer_offset += current_count;
788 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
791 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
793 WREG32(AVIVO_DC_I2C_RESET, 0);
795 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
796 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
797 WREG32(0x494, saved2);
798 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
799 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
800 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
802 mutex_unlock(&rdev->pm.mutex);
803 mutex_unlock(&rdev->dc_hw_i2c_mutex);
808 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
809 struct i2c_msg *msgs, int num)
811 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
812 struct radeon_device *rdev = i2c->dev->dev_private;
813 struct radeon_i2c_bus_rec *rec = &i2c->rec;
816 switch (rdev->family) {
835 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
840 /* XXX fill in hw i2c implementation */
849 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
851 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
857 /* XXX fill in hw i2c implementation */
867 /* XXX fill in hw i2c implementation */
874 /* XXX fill in hw i2c implementation */
877 DRM_ERROR("i2c: unhandled radeon chip\n");
885 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
887 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
890 static const struct i2c_algorithm radeon_i2c_algo = {
891 .master_xfer = radeon_hw_i2c_xfer,
892 .functionality = radeon_hw_i2c_func,
895 static const struct i2c_algorithm radeon_atom_i2c_algo = {
896 .master_xfer = radeon_atom_hw_i2c_xfer,
897 .functionality = radeon_atom_hw_i2c_func,
900 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
901 struct radeon_i2c_bus_rec *rec,
904 struct radeon_device *rdev = dev->dev_private;
905 struct radeon_i2c_chan *i2c;
908 /* don't add the mm_i2c bus unless hw_i2c is enabled */
909 if (rec->mm_i2c && (radeon_hw_i2c == 0))
912 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
917 i2c->adapter.owner = THIS_MODULE;
918 i2c->adapter.class = I2C_CLASS_DDC;
919 i2c->adapter.dev.parent = &dev->pdev->dev;
921 i2c_set_adapdata(&i2c->adapter, i2c);
925 ((rdev->family <= CHIP_RS480) ||
926 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
927 /* set the radeon hw i2c adapter */
928 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
929 "Radeon i2c hw bus %s", name);
930 i2c->adapter.algo = &radeon_i2c_algo;
931 ret = i2c_add_adapter(&i2c->adapter);
933 DRM_ERROR("Failed to register hw i2c %s\n", name);
936 } else if (rec->hw_capable &&
938 ASIC_IS_DCE3(rdev)) {
939 /* hw i2c using atom */
940 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
941 "Radeon i2c hw bus %s", name);
942 i2c->adapter.algo = &radeon_atom_i2c_algo;
943 ret = i2c_add_adapter(&i2c->adapter);
945 DRM_ERROR("Failed to register hw i2c %s\n", name);
949 /* set the radeon bit adapter */
950 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
951 "Radeon i2c bit bus %s", name);
952 i2c->adapter.algo_data = &i2c->bit;
953 i2c->bit.pre_xfer = pre_xfer;
954 i2c->bit.post_xfer = post_xfer;
955 i2c->bit.setsda = set_data;
956 i2c->bit.setscl = set_clock;
957 i2c->bit.getsda = get_data;
958 i2c->bit.getscl = get_clock;
959 i2c->bit.udelay = 10;
960 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
962 ret = i2c_bit_add_bus(&i2c->adapter);
964 DRM_ERROR("Failed to register bit i2c %s\n", name);
976 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
980 i2c_del_adapter(&i2c->adapter);
982 drm_dp_aux_unregister_i2c_bus(&i2c->aux);
986 /* Add the default buses */
987 void radeon_i2c_init(struct radeon_device *rdev)
990 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
992 if (rdev->is_atom_bios)
993 radeon_atombios_i2c_init(rdev);
995 radeon_combios_i2c_init(rdev);
998 /* remove all the buses */
999 void radeon_i2c_fini(struct radeon_device *rdev)
1003 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1004 if (rdev->i2c_bus[i]) {
1005 radeon_i2c_destroy(rdev->i2c_bus[i]);
1006 rdev->i2c_bus[i] = NULL;
1011 /* Add additional buses */
1012 void radeon_i2c_add(struct radeon_device *rdev,
1013 struct radeon_i2c_bus_rec *rec,
1016 struct drm_device *dev = rdev->ddev;
1019 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1020 if (!rdev->i2c_bus[i]) {
1021 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1027 /* looks up bus based on id */
1028 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1029 struct radeon_i2c_bus_rec *i2c_bus)
1033 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1034 if (rdev->i2c_bus[i] &&
1035 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1036 return rdev->i2c_bus[i];
1042 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1047 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1054 struct i2c_msg msgs[] = {
1072 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1074 DRM_DEBUG("val = 0x%02x\n", *val);
1076 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1081 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1087 struct i2c_msg msg = {
1097 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1098 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1102 /* ddc router switching */
1103 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1107 if (!radeon_connector->router.ddc_valid)
1110 if (!radeon_connector->router_bus)
1113 radeon_i2c_get_byte(radeon_connector->router_bus,
1114 radeon_connector->router.i2c_addr,
1116 val &= ~radeon_connector->router.ddc_mux_control_pin;
1117 radeon_i2c_put_byte(radeon_connector->router_bus,
1118 radeon_connector->router.i2c_addr,
1120 radeon_i2c_get_byte(radeon_connector->router_bus,
1121 radeon_connector->router.i2c_addr,
1123 val &= ~radeon_connector->router.ddc_mux_control_pin;
1124 val |= radeon_connector->router.ddc_mux_state;
1125 radeon_i2c_put_byte(radeon_connector->router_bus,
1126 radeon_connector->router.i2c_addr,
1130 /* clock/data router switching */
1131 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1135 if (!radeon_connector->router.cd_valid)
1138 if (!radeon_connector->router_bus)
1141 radeon_i2c_get_byte(radeon_connector->router_bus,
1142 radeon_connector->router.i2c_addr,
1144 val &= ~radeon_connector->router.cd_mux_control_pin;
1145 radeon_i2c_put_byte(radeon_connector->router_bus,
1146 radeon_connector->router.i2c_addr,
1148 radeon_i2c_get_byte(radeon_connector->router_bus,
1149 radeon_connector->router.i2c_addr,
1151 val &= ~radeon_connector->router.cd_mux_control_pin;
1152 val |= radeon_connector->router.cd_mux_state;
1153 radeon_i2c_put_byte(radeon_connector->router_bus,
1154 radeon_connector->router.i2c_addr,