2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
37 u8 out_buf[] = { 0x0, 0x0};
40 struct i2c_msg msgs[] = {
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
63 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
65 struct radeon_device *rdev = i2c->dev->dev_private;
66 struct radeon_i2c_bus_rec *rec = &i2c->rec;
69 /* RV410 appears to have a bug where the hw i2c in reset
70 * holds the i2c port in a bad state - switch hw i2c away before
71 * doing DDC - do this for all r200s/r300s/r400s for safety sake
73 if (rec->hw_capable) {
74 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
77 if (rdev->family >= CHIP_RV350)
78 reg = RADEON_GPIO_MONID;
79 else if ((rdev->family == CHIP_R300) ||
80 (rdev->family == CHIP_R350))
81 reg = RADEON_GPIO_DVI_DDC;
83 reg = RADEON_GPIO_CRT2_DDC;
85 mutex_lock(&rdev->dc_hw_i2c_mutex);
86 if (rec->a_clk_reg == reg) {
87 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
88 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
90 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
91 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
93 mutex_unlock(&rdev->dc_hw_i2c_mutex);
97 /* clear the output pin values */
98 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
99 WREG32(rec->a_clk_reg, temp);
101 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
102 WREG32(rec->a_data_reg, temp);
104 /* set the pins to input */
105 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
106 WREG32(rec->en_clk_reg, temp);
108 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
109 WREG32(rec->en_data_reg, temp);
111 /* mask the gpio pins for software use */
112 temp = RREG32(rec->mask_clk_reg);
114 temp |= rec->mask_clk_mask;
116 temp &= ~rec->mask_clk_mask;
117 WREG32(rec->mask_clk_reg, temp);
118 temp = RREG32(rec->mask_clk_reg);
120 temp = RREG32(rec->mask_data_reg);
122 temp |= rec->mask_data_mask;
124 temp &= ~rec->mask_data_mask;
125 WREG32(rec->mask_data_reg, temp);
126 temp = RREG32(rec->mask_data_reg);
129 static int get_clock(void *i2c_priv)
131 struct radeon_i2c_chan *i2c = i2c_priv;
132 struct radeon_device *rdev = i2c->dev->dev_private;
133 struct radeon_i2c_bus_rec *rec = &i2c->rec;
136 /* read the value off the pin */
137 val = RREG32(rec->y_clk_reg);
138 val &= rec->y_clk_mask;
144 static int get_data(void *i2c_priv)
146 struct radeon_i2c_chan *i2c = i2c_priv;
147 struct radeon_device *rdev = i2c->dev->dev_private;
148 struct radeon_i2c_bus_rec *rec = &i2c->rec;
151 /* read the value off the pin */
152 val = RREG32(rec->y_data_reg);
153 val &= rec->y_data_mask;
158 static void set_clock(void *i2c_priv, int clock)
160 struct radeon_i2c_chan *i2c = i2c_priv;
161 struct radeon_device *rdev = i2c->dev->dev_private;
162 struct radeon_i2c_bus_rec *rec = &i2c->rec;
165 /* set pin direction */
166 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
167 val |= clock ? 0 : rec->en_clk_mask;
168 WREG32(rec->en_clk_reg, val);
171 static void set_data(void *i2c_priv, int data)
173 struct radeon_i2c_chan *i2c = i2c_priv;
174 struct radeon_device *rdev = i2c->dev->dev_private;
175 struct radeon_i2c_bus_rec *rec = &i2c->rec;
178 /* set pin direction */
179 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
180 val |= data ? 0 : rec->en_data_mask;
181 WREG32(rec->en_data_reg, val);
184 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
186 struct radeon_pll *spll = &rdev->clock.spll;
187 u32 sclk = radeon_get_engine_clock(rdev);
193 switch (rdev->family) {
206 n = (spll->reference_freq) / (4 * 6);
207 for (loop = 1; loop < 255; loop++) {
208 if ((loop * (loop - 1)) > n)
212 prescale = m | (loop << 8);
220 sclk = radeon_get_engine_clock(rdev);
221 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
235 sclk = radeon_get_engine_clock(rdev);
236 if (rdev->family == CHIP_R520)
237 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
239 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
265 DRM_ERROR("i2c: unhandled radeon chip\n");
272 /* hw i2c engine for r1xx-4xx hardware
273 * hw can buffer up to 15 bytes
275 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
276 struct i2c_msg *msgs, int num)
278 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
279 struct radeon_device *rdev = i2c->dev->dev_private;
280 struct radeon_i2c_bus_rec *rec = &i2c->rec;
282 int i, j, k, ret = num;
284 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
287 mutex_lock(&rdev->dc_hw_i2c_mutex);
288 /* take the pm lock since we need a constant sclk */
289 mutex_lock(&rdev->pm.mutex);
291 prescale = radeon_get_i2c_prescale(rdev);
293 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
298 if (rdev->is_atom_bios) {
299 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
300 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
304 i2c_cntl_0 = RADEON_I2C_CNTL_0;
305 i2c_cntl_1 = RADEON_I2C_CNTL_1;
306 i2c_data = RADEON_I2C_DATA;
308 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
309 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
310 i2c_data = RADEON_DVI_I2C_DATA;
312 switch (rdev->family) {
319 switch (rec->mask_clk_reg) {
320 case RADEON_GPIO_DVI_DDC:
321 /* no gpio select bit */
324 DRM_ERROR("gpio not supported with hw i2c\n");
330 /* only bit 4 on r200 */
331 switch (rec->mask_clk_reg) {
332 case RADEON_GPIO_DVI_DDC:
333 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
335 case RADEON_GPIO_MONID:
336 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
339 DRM_ERROR("gpio not supported with hw i2c\n");
347 switch (rec->mask_clk_reg) {
348 case RADEON_GPIO_DVI_DDC:
349 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
351 case RADEON_GPIO_VGA_DDC:
352 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
354 case RADEON_GPIO_CRT2_DDC:
355 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
358 DRM_ERROR("gpio not supported with hw i2c\n");
365 /* only bit 4 on r300/r350 */
366 switch (rec->mask_clk_reg) {
367 case RADEON_GPIO_VGA_DDC:
368 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
370 case RADEON_GPIO_DVI_DDC:
371 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
374 DRM_ERROR("gpio not supported with hw i2c\n");
387 switch (rec->mask_clk_reg) {
388 case RADEON_GPIO_VGA_DDC:
389 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
391 case RADEON_GPIO_DVI_DDC:
392 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
394 case RADEON_GPIO_MONID:
395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
398 DRM_ERROR("gpio not supported with hw i2c\n");
404 DRM_ERROR("unsupported asic\n");
411 /* check for bus probe */
413 if ((num == 1) && (p->len == 0)) {
414 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
417 RADEON_I2C_SOFT_RST));
418 WREG32(i2c_data, (p->addr << 1) & 0xff);
420 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
421 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
423 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
424 WREG32(i2c_cntl_0, reg);
425 for (k = 0; k < 32; k++) {
427 tmp = RREG32(i2c_cntl_0);
428 if (tmp & RADEON_I2C_GO)
430 tmp = RREG32(i2c_cntl_0);
431 if (tmp & RADEON_I2C_DONE)
434 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
435 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
443 for (i = 0; i < num; i++) {
445 for (j = 0; j < p->len; j++) {
446 if (p->flags & I2C_M_RD) {
447 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
450 RADEON_I2C_SOFT_RST));
451 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
452 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
453 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
455 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
456 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
457 for (k = 0; k < 32; k++) {
459 tmp = RREG32(i2c_cntl_0);
460 if (tmp & RADEON_I2C_GO)
462 tmp = RREG32(i2c_cntl_0);
463 if (tmp & RADEON_I2C_DONE)
466 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
467 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
472 p->buf[j] = RREG32(i2c_data) & 0xff;
474 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
477 RADEON_I2C_SOFT_RST));
478 WREG32(i2c_data, (p->addr << 1) & 0xff);
479 WREG32(i2c_data, p->buf[j]);
480 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
481 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
483 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
484 WREG32(i2c_cntl_0, reg);
485 for (k = 0; k < 32; k++) {
487 tmp = RREG32(i2c_cntl_0);
488 if (tmp & RADEON_I2C_GO)
490 tmp = RREG32(i2c_cntl_0);
491 if (tmp & RADEON_I2C_DONE)
494 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
495 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
505 WREG32(i2c_cntl_0, 0);
506 WREG32(i2c_cntl_1, 0);
507 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
510 RADEON_I2C_SOFT_RST));
512 if (rdev->is_atom_bios) {
513 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
514 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
515 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
518 mutex_unlock(&rdev->pm.mutex);
519 mutex_unlock(&rdev->dc_hw_i2c_mutex);
524 /* hw i2c engine for r5xx hardware
525 * hw can buffer up to 15 bytes
527 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
528 struct i2c_msg *msgs, int num)
530 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
531 struct radeon_device *rdev = i2c->dev->dev_private;
532 struct radeon_i2c_bus_rec *rec = &i2c->rec;
534 int i, j, remaining, current_count, buffer_offset, ret = num;
539 mutex_lock(&rdev->dc_hw_i2c_mutex);
540 /* take the pm lock since we need a constant sclk */
541 mutex_lock(&rdev->pm.mutex);
543 prescale = radeon_get_i2c_prescale(rdev);
545 /* clear gpio mask bits */
546 tmp = RREG32(rec->mask_clk_reg);
547 tmp &= ~rec->mask_clk_mask;
548 WREG32(rec->mask_clk_reg, tmp);
549 tmp = RREG32(rec->mask_clk_reg);
551 tmp = RREG32(rec->mask_data_reg);
552 tmp &= ~rec->mask_data_mask;
553 WREG32(rec->mask_data_reg, tmp);
554 tmp = RREG32(rec->mask_data_reg);
556 /* clear pin values */
557 tmp = RREG32(rec->a_clk_reg);
558 tmp &= ~rec->a_clk_mask;
559 WREG32(rec->a_clk_reg, tmp);
560 tmp = RREG32(rec->a_clk_reg);
562 tmp = RREG32(rec->a_data_reg);
563 tmp &= ~rec->a_data_mask;
564 WREG32(rec->a_data_reg, tmp);
565 tmp = RREG32(rec->a_data_reg);
567 /* set the pins to input */
568 tmp = RREG32(rec->en_clk_reg);
569 tmp &= ~rec->en_clk_mask;
570 WREG32(rec->en_clk_reg, tmp);
571 tmp = RREG32(rec->en_clk_reg);
573 tmp = RREG32(rec->en_data_reg);
574 tmp &= ~rec->en_data_mask;
575 WREG32(rec->en_data_reg, tmp);
576 tmp = RREG32(rec->en_data_reg);
579 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
580 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
581 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
582 saved2 = RREG32(0x494);
583 WREG32(0x494, saved2 | 0x1);
585 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
586 for (i = 0; i < 50; i++) {
588 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
592 DRM_ERROR("failed to get i2c bus\n");
597 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
598 switch (rec->mask_clk_reg) {
599 case AVIVO_DC_GPIO_DDC1_MASK:
600 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
602 case AVIVO_DC_GPIO_DDC2_MASK:
603 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
605 case AVIVO_DC_GPIO_DDC3_MASK:
606 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
609 DRM_ERROR("gpio not supported with hw i2c\n");
614 /* check for bus probe */
616 if ((num == 1) && (p->len == 0)) {
617 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
620 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
622 WREG32(AVIVO_DC_I2C_RESET, 0);
624 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
625 WREG32(AVIVO_DC_I2C_DATA, 0);
627 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
628 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
629 AVIVO_DC_I2C_DATA_COUNT(1) |
631 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
632 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
633 for (j = 0; j < 200; j++) {
635 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
636 if (tmp & AVIVO_DC_I2C_GO)
638 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
639 if (tmp & AVIVO_DC_I2C_DONE)
642 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
643 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
651 for (i = 0; i < num; i++) {
655 if (p->flags & I2C_M_RD) {
660 current_count = remaining;
661 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
664 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
666 WREG32(AVIVO_DC_I2C_RESET, 0);
668 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
669 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
670 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
671 AVIVO_DC_I2C_DATA_COUNT(current_count) |
673 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
674 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
675 for (j = 0; j < 200; j++) {
677 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
678 if (tmp & AVIVO_DC_I2C_GO)
680 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
681 if (tmp & AVIVO_DC_I2C_DONE)
684 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
685 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
690 for (j = 0; j < current_count; j++)
691 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
692 remaining -= current_count;
693 buffer_offset += current_count;
700 current_count = remaining;
701 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
704 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
706 WREG32(AVIVO_DC_I2C_RESET, 0);
708 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
709 for (j = 0; j < current_count; j++)
710 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
712 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
713 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
714 AVIVO_DC_I2C_DATA_COUNT(current_count) |
716 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
717 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
718 for (j = 0; j < 200; j++) {
720 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
721 if (tmp & AVIVO_DC_I2C_GO)
723 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
724 if (tmp & AVIVO_DC_I2C_DONE)
727 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
728 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
733 remaining -= current_count;
734 buffer_offset += current_count;
740 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
743 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
745 WREG32(AVIVO_DC_I2C_RESET, 0);
747 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
748 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
749 WREG32(0x494, saved2);
750 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
751 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
752 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
754 mutex_unlock(&rdev->pm.mutex);
755 mutex_unlock(&rdev->dc_hw_i2c_mutex);
760 static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
761 struct i2c_msg *msgs, int num)
763 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
766 radeon_i2c_do_lock(i2c, 1);
767 ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
768 radeon_i2c_do_lock(i2c, 0);
773 static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
774 struct i2c_msg *msgs, int num)
776 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
777 struct radeon_device *rdev = i2c->dev->dev_private;
778 struct radeon_i2c_bus_rec *rec = &i2c->rec;
781 switch (rdev->family) {
801 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
803 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
808 /* XXX fill in hw i2c implementation */
809 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
817 if (rec->hw_capable) {
819 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
821 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
823 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
829 /* XXX fill in hw i2c implementation */
830 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
840 /* XXX fill in hw i2c implementation */
841 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
848 /* XXX fill in hw i2c implementation */
849 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
852 DRM_ERROR("i2c: unhandled radeon chip\n");
860 static u32 radeon_i2c_func(struct i2c_adapter *adap)
862 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
865 static const struct i2c_algorithm radeon_i2c_algo = {
866 .master_xfer = radeon_i2c_xfer,
867 .functionality = radeon_i2c_func,
870 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
871 struct radeon_i2c_bus_rec *rec,
874 struct radeon_i2c_chan *i2c;
877 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
881 /* set the internal bit adapter */
882 i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
883 i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
884 sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
885 i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
886 i2c->algo.radeon.bit_data.setsda = set_data;
887 i2c->algo.radeon.bit_data.setscl = set_clock;
888 i2c->algo.radeon.bit_data.getsda = get_data;
889 i2c->algo.radeon.bit_data.getscl = get_clock;
890 i2c->algo.radeon.bit_data.udelay = 20;
891 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
892 * make this, 2 jiffies is a lot more reliable */
893 i2c->algo.radeon.bit_data.timeout = 2;
894 i2c->algo.radeon.bit_data.data = i2c;
895 ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
897 DRM_ERROR("Failed to register internal bit i2c %s\n", name);
900 /* set the radeon i2c adapter */
903 i2c->adapter.owner = THIS_MODULE;
904 i2c_set_adapdata(&i2c->adapter, i2c);
905 sprintf(i2c->adapter.name, "Radeon i2c %s", name);
906 i2c->adapter.algo_data = &i2c->algo.radeon;
907 i2c->adapter.algo = &radeon_i2c_algo;
908 ret = i2c_add_adapter(&i2c->adapter);
910 DRM_ERROR("Failed to register i2c %s\n", name);
921 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
922 struct radeon_i2c_bus_rec *rec,
925 struct radeon_i2c_chan *i2c;
928 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
933 i2c->adapter.owner = THIS_MODULE;
935 i2c_set_adapdata(&i2c->adapter, i2c);
936 i2c->adapter.algo_data = &i2c->algo.dp;
937 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
938 i2c->algo.dp.address = 0;
939 ret = i2c_dp_aux_add_bus(&i2c->adapter);
941 DRM_INFO("Failed to register i2c %s\n", name);
952 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
956 i2c_del_adapter(&i2c->algo.radeon.bit_adapter);
957 i2c_del_adapter(&i2c->adapter);
961 void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
966 i2c_del_adapter(&i2c->adapter);
970 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
975 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
982 struct i2c_msg msgs[] = {
1000 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1002 DRM_DEBUG("val = 0x%02x\n", *val);
1004 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
1009 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1015 struct i2c_msg msg = {
1025 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1026 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",