drivers/gpu/drm/radeon/radeon_i2c.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29 #include "atom.h"
  30
  31 /**
  32  * radeon_ddc_probe
  33  *
  34  */
  35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
  36 {
  37         u8 out_buf[] = { 0x0, 0x0};
  38         u8 buf[2];
  39         int ret;
  40         struct i2c_msg msgs[] = {
  41                 {
  42                         .addr = 0x50,
  43                         .flags = 0,
  44                         .len = 1,
  45                         .buf = out_buf,
  46                 },
  47                 {
  48                         .addr = 0x50,
  49                         .flags = I2C_M_RD,
  50                         .len = 1,
  51                         .buf = buf,
  52                 }
  53         };
  54
  55         ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
  56         if (ret == 2)
  57                 return true;
  58
  59         return false;
  60 }
  61
  62
  63 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
  64 {
  65         struct radeon_device *rdev = i2c->dev->dev_private;
  66         struct radeon_i2c_bus_rec *rec = &i2c->rec;
  67         uint32_t temp;
  68
  69         /* RV410 appears to have a bug where the hw i2c in reset
  70          * holds the i2c port in a bad state - switch hw i2c away before
  71          * doing DDC - do this for all r200s/r300s/r400s for safety sake
  72          */
  73         if (rec->hw_capable) {
  74                 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
  75                         u32 reg;
  76
  77                         if (rdev->family >= CHIP_RV350)
  78                                 reg = RADEON_GPIO_MONID;
  79                         else if ((rdev->family == CHIP_R300) ||
  80                                  (rdev->family == CHIP_R350))
  81                                 reg = RADEON_GPIO_DVI_DDC;
  82                         else
  83                                 reg = RADEON_GPIO_CRT2_DDC;
  84
  85                         mutex_lock(&rdev->dc_hw_i2c_mutex);
  86                         if (rec->a_clk_reg == reg) {
  87                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
  88                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
  89                         } else {
  90                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
  91                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
  92                         }
  93                         mutex_unlock(&rdev->dc_hw_i2c_mutex);
  94                 }
  95         }
  96
  97         /* clear the output pin values */
  98         temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
  99         WREG32(rec->a_clk_reg, temp);
 100
 101         temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
 102         WREG32(rec->a_data_reg, temp);
 103
 104         /* set the pins to input */
 105         temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 106         WREG32(rec->en_clk_reg, temp);
 107
 108         temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 109         WREG32(rec->en_data_reg, temp);
 110
 111         /* mask the gpio pins for software use */
 112         temp = RREG32(rec->mask_clk_reg);
 113         if (lock_state)
 114                 temp |= rec->mask_clk_mask;
 115         else
 116                 temp &= ~rec->mask_clk_mask;
 117         WREG32(rec->mask_clk_reg, temp);
 118         temp = RREG32(rec->mask_clk_reg);
 119
 120         temp = RREG32(rec->mask_data_reg);
 121         if (lock_state)
 122                 temp |= rec->mask_data_mask;
 123         else
 124                 temp &= ~rec->mask_data_mask;
 125         WREG32(rec->mask_data_reg, temp);
 126         temp = RREG32(rec->mask_data_reg);
 127 }
 128
 129 static int get_clock(void *i2c_priv)
 130 {
 131         struct radeon_i2c_chan *i2c = i2c_priv;
 132         struct radeon_device *rdev = i2c->dev->dev_private;
 133         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 134         uint32_t val;
 135
 136         /* read the value off the pin */
 137         val = RREG32(rec->y_clk_reg);
 138         val &= rec->y_clk_mask;
 139
 140         return (val != 0);
 141 }
 142
 143
 144 static int get_data(void *i2c_priv)
 145 {
 146         struct radeon_i2c_chan *i2c = i2c_priv;
 147         struct radeon_device *rdev = i2c->dev->dev_private;
 148         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 149         uint32_t val;
 150
 151         /* read the value off the pin */
 152         val = RREG32(rec->y_data_reg);
 153         val &= rec->y_data_mask;
 154
 155         return (val != 0);
 156 }
 157
 158 static void set_clock(void *i2c_priv, int clock)
 159 {
 160         struct radeon_i2c_chan *i2c = i2c_priv;
 161         struct radeon_device *rdev = i2c->dev->dev_private;
 162         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 163         uint32_t val;
 164
 165         /* set pin direction */
 166         val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 167         val |= clock ? 0 : rec->en_clk_mask;
 168         WREG32(rec->en_clk_reg, val);
 169 }
 170
 171 static void set_data(void *i2c_priv, int data)
 172 {
 173         struct radeon_i2c_chan *i2c = i2c_priv;
 174         struct radeon_device *rdev = i2c->dev->dev_private;
 175         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 176         uint32_t val;
 177
 178         /* set pin direction */
 179         val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 180         val |= data ? 0 : rec->en_data_mask;
 181         WREG32(rec->en_data_reg, val);
 182 }
 183
 184 /* hw i2c engine for r1xx-4xx hardware
 185  * hw can buffer up to 15 bytes
 186  */
 187 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 188                             struct i2c_msg *msgs, int num)
 189 {
 190         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 191         struct radeon_device *rdev = i2c->dev->dev_private;
 192         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 193         struct i2c_msg *p;
 194         int i, j, k, ret = num;
 195         /* XXX: use get_engine_clock() to get the current sclk */
 196         u32 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 197         u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
 198         u32 tmp, reg;
 199
 200         mutex_lock(&rdev->dc_hw_i2c_mutex);
 201
 202         reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
 203                RADEON_I2C_START |
 204                RADEON_I2C_STOP |
 205                RADEON_I2C_GO);
 206
 207         if (rdev->is_atom_bios) {
 208                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 209                 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 210         }
 211
 212         if (rec->mm_i2c) {
 213                 i2c_cntl_0 = RADEON_I2C_CNTL_0;
 214                 i2c_cntl_1 = RADEON_I2C_CNTL_1;
 215                 i2c_data = RADEON_I2C_DATA;
 216         } else {
 217                 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
 218                 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
 219                 i2c_data = RADEON_DVI_I2C_DATA;
 220
 221                 switch (rdev->family) {
 222                 case CHIP_R100:
 223                 case CHIP_RV100:
 224                 case CHIP_RS100:
 225                 case CHIP_RV200:
 226                 case CHIP_RS200:
 227                 case CHIP_RS300:
 228                         switch (rec->mask_clk_reg) {
 229                         case RADEON_GPIO_DVI_DDC:
 230                                 /* no gpio select bit */
 231                                 break;
 232                         default:
 233                                 DRM_ERROR("gpio not supported with hw i2c\n");
 234                                 ret = -EINVAL;
 235                                 goto done;
 236                         }
 237                         break;
 238                 case CHIP_R200:
 239                         /* only bit 4 on r200 */
 240                         switch (rec->mask_clk_reg) {
 241                         case RADEON_GPIO_DVI_DDC:
 242                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 243                                 break;
 244                         case RADEON_GPIO_MONID:
 245                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 246                                 break;
 247                         default:
 248                                 DRM_ERROR("gpio not supported with hw i2c\n");
 249                                 ret = -EINVAL;
 250                                 goto done;
 251                         }
 252                         break;
 253                 case CHIP_RV250:
 254                 case CHIP_RV280:
 255                         /* bits 3 and 4 */
 256                         switch (rec->mask_clk_reg) {
 257                         case RADEON_GPIO_DVI_DDC:
 258                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 259                                 break;
 260                         case RADEON_GPIO_VGA_DDC:
 261                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 262                                 break;
 263                         case RADEON_GPIO_CRT2_DDC:
 264                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 265                                 break;
 266                         default:
 267                                 DRM_ERROR("gpio not supported with hw i2c\n");
 268                                 ret = -EINVAL;
 269                                 goto done;
 270                         }
 271                         break;
 272                 case CHIP_R300:
 273                 case CHIP_R350:
 274                         /* only bit 4 on r300/r350 */
 275                         switch (rec->mask_clk_reg) {
 276                         case RADEON_GPIO_VGA_DDC:
 277                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 278                                 break;
 279                         case RADEON_GPIO_DVI_DDC:
 280                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 281                                 break;
 282                         default:
 283                                 DRM_ERROR("gpio not supported with hw i2c\n");
 284                                 ret = -EINVAL;
 285                                 goto done;
 286                         }
 287                         break;
 288                 case CHIP_RV350:
 289                 case CHIP_RV380:
 290                 case CHIP_R420:
 291                 case CHIP_R423:
 292                 case CHIP_RV410:
 293                 case CHIP_RS400:
 294                 case CHIP_RS480:
 295                         /* bits 3 and 4 */
 296                         switch (rec->mask_clk_reg) {
 297                         case RADEON_GPIO_VGA_DDC:
 298                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 299                                 break;
 300                         case RADEON_GPIO_DVI_DDC:
 301                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 302                                 break;
 303                         case RADEON_GPIO_MONID:
 304                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 305                                 break;
 306                         default:
 307                                 DRM_ERROR("gpio not supported with hw i2c\n");
 308                                 ret = -EINVAL;
 309                                 goto done;
 310                         }
 311                         break;
 312                 default:
 313                         DRM_ERROR("unsupported asic\n");
 314                         ret = -EINVAL;
 315                         goto done;
 316                         break;
 317                 }
 318         }
 319
 320         /* check for bus probe */
 321         p = &msgs[0];
 322         if ((num == 1) && (p->len == 0)) {
 323                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 324                                     RADEON_I2C_NACK |
 325                                     RADEON_I2C_HALT |
 326                                     RADEON_I2C_SOFT_RST));
 327                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 328                 WREG32(i2c_data, 0);
 329                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 330                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 331                                     RADEON_I2C_EN |
 332                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 333                 WREG32(i2c_cntl_0, reg);
 334                 for (k = 0; k < 32; k++) {
 335                         udelay(10);
 336                         tmp = RREG32(i2c_cntl_0);
 337                         if (tmp & RADEON_I2C_GO)
 338                                 continue;
 339                         tmp = RREG32(i2c_cntl_0);
 340                         if (tmp & RADEON_I2C_DONE)
 341                                 break;
 342                         else {
 343                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 344                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 345                                 ret = -EIO;
 346                                 goto done;
 347                         }
 348                 }
 349                 goto done;
 350         }
 351
 352         for (i = 0; i < num; i++) {
 353                 p = &msgs[i];
 354                 for (j = 0; j < p->len; j++) {
 355                         if (p->flags & I2C_M_RD) {
 356                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 357                                                     RADEON_I2C_NACK |
 358                                                     RADEON_I2C_HALT |
 359                                                     RADEON_I2C_SOFT_RST));
 360                                 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
 361                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 362                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 363                                                     RADEON_I2C_EN |
 364                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 365                                 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
 366                                 for (k = 0; k < 32; k++) {
 367                                         udelay(10);
 368                                         tmp = RREG32(i2c_cntl_0);
 369                                         if (tmp & RADEON_I2C_GO)
 370                                                 continue;
 371                                         tmp = RREG32(i2c_cntl_0);
 372                                         if (tmp & RADEON_I2C_DONE)
 373                                                 break;
 374                                         else {
 375                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 376                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 377                                                 ret = -EIO;
 378                                                 goto done;
 379                                         }
 380                                 }
 381                                 p->buf[j] = RREG32(i2c_data) & 0xff;
 382                         } else {
 383                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 384                                                     RADEON_I2C_NACK |
 385                                                     RADEON_I2C_HALT |
 386                                                     RADEON_I2C_SOFT_RST));
 387                                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 388                                 WREG32(i2c_data, p->buf[j]);
 389                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 390                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 391                                                     RADEON_I2C_EN |
 392                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 393                                 WREG32(i2c_cntl_0, reg);
 394                                 for (k = 0; k < 32; k++) {
 395                                         udelay(10);
 396                                         tmp = RREG32(i2c_cntl_0);
 397                                         if (tmp & RADEON_I2C_GO)
 398                                                 continue;
 399                                         tmp = RREG32(i2c_cntl_0);
 400                                         if (tmp & RADEON_I2C_DONE)
 401                                                 break;
 402                                         else {
 403                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 404                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 405                                                 ret = -EIO;
 406                                                 goto done;
 407                                         }
 408                                 }
 409                         }
 410                 }
 411         }
 412
 413 done:
 414         WREG32(i2c_cntl_0, 0);
 415         WREG32(i2c_cntl_1, 0);
 416         WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 417                             RADEON_I2C_NACK |
 418                             RADEON_I2C_HALT |
 419                             RADEON_I2C_SOFT_RST));
 420
 421         if (rdev->is_atom_bios) {
 422                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 423                 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 424                 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 425         }
 426
 427         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 428
 429         return ret;
 430 }
 431
 432 /* hw i2c engine for r5xx hardware
 433  * hw can buffer up to 15 bytes
 434  */
 435 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 436                             struct i2c_msg *msgs, int num)
 437 {
 438         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 439         struct radeon_device *rdev = i2c->dev->dev_private;
 440         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 441         struct i2c_msg *p;
 442         int i2c_clock = 50;
 443         int i, j, remaining, current_count, buffer_offset, ret = num;
 444         /* XXX: use get_engine_clock() to get the current sclk */
 445         u32 prescale;
 446         u32 tmp, reg;
 447         u32 saved1, saved2;
 448
 449         mutex_lock(&rdev->dc_hw_i2c_mutex);
 450
 451         /* clear gpio mask bits */
 452         tmp = RREG32(rec->mask_clk_reg);
 453         tmp &= ~rec->mask_clk_mask;
 454         WREG32(rec->mask_clk_reg, tmp);
 455         tmp = RREG32(rec->mask_clk_reg);
 456
 457         tmp = RREG32(rec->mask_data_reg);
 458         tmp &= ~rec->mask_data_mask;
 459         WREG32(rec->mask_data_reg, tmp);
 460         tmp = RREG32(rec->mask_data_reg);
 461
 462         /* clear pin values */
 463         tmp = RREG32(rec->a_clk_reg);
 464         tmp &= ~rec->a_clk_mask;
 465         WREG32(rec->a_clk_reg, tmp);
 466         tmp = RREG32(rec->a_clk_reg);
 467
 468         tmp = RREG32(rec->a_data_reg);
 469         tmp &= ~rec->a_data_mask;
 470         WREG32(rec->a_data_reg, tmp);
 471         tmp = RREG32(rec->a_data_reg);
 472
 473         /* set the pins to input */
 474         tmp = RREG32(rec->en_clk_reg);
 475         tmp &= ~rec->en_clk_mask;
 476         WREG32(rec->en_clk_reg, tmp);
 477         tmp = RREG32(rec->en_clk_reg);
 478
 479         tmp = RREG32(rec->en_data_reg);
 480         tmp &= ~rec->en_data_mask;
 481         WREG32(rec->en_data_reg, tmp);
 482         tmp = RREG32(rec->en_data_reg);
 483
 484         /* */
 485         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 486         WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 487         saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
 488         saved2 = RREG32(0x494);
 489         WREG32(0x494, saved2 | 0x1);
 490
 491         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
 492         for (i = 0; i < 50; i++) {
 493                 udelay(1);
 494                 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
 495                         break;
 496         }
 497         if (i == 50) {
 498                 DRM_ERROR("failed to get i2c bus\n");
 499                 ret = -EBUSY;
 500                 goto done;
 501         }
 502
 503         if (rdev->family == CHIP_R520)
 504                 prescale = (127 << 8) + ((rdev->clock.default_sclk * 10) / (4 * 127 * i2c_clock));
 505         else
 506                 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 507
 508         reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
 509         switch (rec->mask_clk_reg) {
 510         case AVIVO_DC_GPIO_DDC1_MASK:
 511                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
 512                 break;
 513         case AVIVO_DC_GPIO_DDC2_MASK:
 514                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
 515                 break;
 516         case AVIVO_DC_GPIO_DDC3_MASK:
 517                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
 518                 break;
 519         default:
 520                 DRM_ERROR("gpio not supported with hw i2c\n");
 521                 ret = -EINVAL;
 522                 goto done;
 523         }
 524
 525         /* check for bus probe */
 526         p = &msgs[0];
 527         if ((num == 1) && (p->len == 0)) {
 528                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 529                                               AVIVO_DC_I2C_NACK |
 530                                               AVIVO_DC_I2C_HALT));
 531                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 532                 udelay(1);
 533                 WREG32(AVIVO_DC_I2C_RESET, 0);
 534
 535                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 536                 WREG32(AVIVO_DC_I2C_DATA, 0);
 537
 538                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 539                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 540                                                AVIVO_DC_I2C_DATA_COUNT(1) |
 541                                                (prescale << 16)));
 542                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 543                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 544                 for (j = 0; j < 200; j++) {
 545                         udelay(50);
 546                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 547                         if (tmp & AVIVO_DC_I2C_GO)
 548                                 continue;
 549                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 550                         if (tmp & AVIVO_DC_I2C_DONE)
 551                                 break;
 552                         else {
 553                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 554                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 555                                 ret = -EIO;
 556                                 goto done;
 557                         }
 558                 }
 559                 goto done;
 560         }
 561
 562         for (i = 0; i < num; i++) {
 563                 p = &msgs[i];
 564                 remaining = p->len;
 565                 buffer_offset = 0;
 566                 if (p->flags & I2C_M_RD) {
 567                         while (remaining) {
 568                                 if (remaining > 15)
 569                                         current_count = 15;
 570                                 else
 571                                         current_count = remaining;
 572                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 573                                                               AVIVO_DC_I2C_NACK |
 574                                                               AVIVO_DC_I2C_HALT));
 575                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 576                                 udelay(1);
 577                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 578
 579                                 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
 580                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 581                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 582                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 583                                                                (prescale << 16)));
 584                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
 585                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 586                                 for (j = 0; j < 200; j++) {
 587                                         udelay(50);
 588                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 589                                         if (tmp & AVIVO_DC_I2C_GO)
 590                                                 continue;
 591                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 592                                         if (tmp & AVIVO_DC_I2C_DONE)
 593                                                 break;
 594                                         else {
 595                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 596                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 597                                                 ret = -EIO;
 598                                                 goto done;
 599                                         }
 600                                 }
 601                                 for (j = 0; j < current_count; j++)
 602                                         p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
 603                                 remaining -= current_count;
 604                                 buffer_offset += current_count;
 605                         }
 606                 } else {
 607                         while (remaining) {
 608                                 if (remaining > 15)
 609                                         current_count = 15;
 610                                 else
 611                                         current_count = remaining;
 612                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 613                                                               AVIVO_DC_I2C_NACK |
 614                                                               AVIVO_DC_I2C_HALT));
 615                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 616                                 udelay(1);
 617                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 618
 619                                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 620                                 for (j = 0; j < current_count; j++)
 621                                         WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
 622
 623                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 624                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 625                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 626                                                                (prescale << 16)));
 627                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 628                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 629                                 for (j = 0; j < 200; j++) {
 630                                         udelay(50);
 631                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 632                                         if (tmp & AVIVO_DC_I2C_GO)
 633                                                 continue;
 634                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 635                                         if (tmp & AVIVO_DC_I2C_DONE)
 636                                                 break;
 637                                         else {
 638                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 639                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 640                                                 ret = -EIO;
 641                                                 goto done;
 642                                         }
 643                                 }
 644                                 remaining -= current_count;
 645                                 buffer_offset += current_count;
 646                         }
 647                 }
 648         }
 649
 650 done:
 651         WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 652                                       AVIVO_DC_I2C_NACK |
 653                                       AVIVO_DC_I2C_HALT));
 654         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 655         udelay(1);
 656         WREG32(AVIVO_DC_I2C_RESET, 0);
 657
 658         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
 659         WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
 660         WREG32(0x494, saved2);
 661         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 662         tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 663         WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 664
 665         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 666
 667         return ret;
 668 }
 669
 670 static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
 671                               struct i2c_msg *msgs, int num)
 672 {
 673         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 674         int ret;
 675
 676         radeon_i2c_do_lock(i2c, 1);
 677         ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
 678         radeon_i2c_do_lock(i2c, 0);
 679
 680         return ret;
 681 }
 682
 683 static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
 684                            struct i2c_msg *msgs, int num)
 685 {
 686         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 687         struct radeon_device *rdev = i2c->dev->dev_private;
 688         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 689         int ret;
 690
 691         switch (rdev->family) {
 692         case CHIP_R100:
 693         case CHIP_RV100:
 694         case CHIP_RS100:
 695         case CHIP_RV200:
 696         case CHIP_RS200:
 697         case CHIP_R200:
 698         case CHIP_RV250:
 699         case CHIP_RS300:
 700         case CHIP_RV280:
 701         case CHIP_R300:
 702         case CHIP_R350:
 703         case CHIP_RV350:
 704         case CHIP_RV380:
 705         case CHIP_R420:
 706         case CHIP_R423:
 707         case CHIP_RV410:
 708         case CHIP_RS400:
 709         case CHIP_RS480:
 710                 if (rec->hw_capable)
 711                         ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 712                 else
 713                         ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 714                 break;
 715         case CHIP_RS600:
 716         case CHIP_RS690:
 717         case CHIP_RS740:
 718                 /* XXX fill in hw i2c implementation */
 719                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 720                 break;
 721         case CHIP_RV515:
 722         case CHIP_R520:
 723         case CHIP_RV530:
 724         case CHIP_RV560:
 725         case CHIP_RV570:
 726         case CHIP_R580:
 727                 if (rec->hw_capable) {
 728                         if (rec->mm_i2c)
 729                                 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 730                         else
 731                                 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
 732                 } else
 733                         ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 734                 break;
 735         case CHIP_R600:
 736         case CHIP_RV610:
 737         case CHIP_RV630:
 738         case CHIP_RV670:
 739                 /* XXX fill in hw i2c implementation */
 740                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 741                 break;
 742         case CHIP_RV620:
 743         case CHIP_RV635:
 744         case CHIP_RS780:
 745         case CHIP_RS880:
 746         case CHIP_RV770:
 747         case CHIP_RV730:
 748         case CHIP_RV710:
 749         case CHIP_RV740:
 750                 /* XXX fill in hw i2c implementation */
 751                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 752                 break;
 753         default:
 754                 DRM_ERROR("i2c: unhandled radeon chip\n");
 755                 ret = -EIO;
 756                 break;
 757         }
 758
 759         return ret;
 760 }
 761
 762 static u32 radeon_i2c_func(struct i2c_adapter *adap)
 763 {
 764         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 765 }
 766
 767 static const struct i2c_algorithm radeon_i2c_algo = {
 768         .master_xfer = radeon_i2c_xfer,
 769         .functionality = radeon_i2c_func,
 770 };
 771
 772 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 773                                           struct radeon_i2c_bus_rec *rec,
 774                                           const char *name)
 775 {
 776         struct radeon_i2c_chan *i2c;
 777         int ret;
 778
 779         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 780         if (i2c == NULL)
 781                 return NULL;
 782
 783         /* set the internal bit adapter */
 784         i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
 785         i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
 786         sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
 787         i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
 788         i2c->algo.radeon.bit_data.setsda = set_data;
 789         i2c->algo.radeon.bit_data.setscl = set_clock;
 790         i2c->algo.radeon.bit_data.getsda = get_data;
 791         i2c->algo.radeon.bit_data.getscl = get_clock;
 792         i2c->algo.radeon.bit_data.udelay = 20;
 793         /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
 794          * make this, 2 jiffies is a lot more reliable */
 795         i2c->algo.radeon.bit_data.timeout = 2;
 796         i2c->algo.radeon.bit_data.data = i2c;
 797         ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
 798         if (ret) {
 799                 DRM_ERROR("Failed to register internal bit i2c %s\n", name);
 800                 goto out_free;
 801         }
 802         /* set the radeon i2c adapter */
 803         i2c->dev = dev;
 804         i2c->rec = *rec;
 805         i2c->adapter.owner = THIS_MODULE;
 806         i2c_set_adapdata(&i2c->adapter, i2c);
 807         sprintf(i2c->adapter.name, "Radeon i2c %s", name);
 808         i2c->adapter.algo_data = &i2c->algo.radeon;
 809         i2c->adapter.algo = &radeon_i2c_algo;
 810         ret = i2c_add_adapter(&i2c->adapter);
 811         if (ret) {
 812                 DRM_ERROR("Failed to register i2c %s\n", name);
 813                 goto out_free;
 814         }
 815
 816         return i2c;
 817 out_free:
 818         kfree(i2c);
 819         return NULL;
 820
 821 }
 822
 823 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 824                                              struct radeon_i2c_bus_rec *rec,
 825                                              const char *name)
 826 {
 827         struct radeon_i2c_chan *i2c;
 828         int ret;
 829
 830         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 831         if (i2c == NULL)
 832                 return NULL;
 833
 834         i2c->rec = *rec;
 835         i2c->adapter.owner = THIS_MODULE;
 836         i2c->dev = dev;
 837         i2c_set_adapdata(&i2c->adapter, i2c);
 838         i2c->adapter.algo_data = &i2c->algo.dp;
 839         i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
 840         i2c->algo.dp.address = 0;
 841         ret = i2c_dp_aux_add_bus(&i2c->adapter);
 842         if (ret) {
 843                 DRM_INFO("Failed to register i2c %s\n", name);
 844                 goto out_free;
 845         }
 846
 847         return i2c;
 848 out_free:
 849         kfree(i2c);
 850         return NULL;
 851
 852 }
 853
 854 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 855 {
 856         if (!i2c)
 857                 return;
 858         i2c_del_adapter(&i2c->algo.radeon.bit_adapter);
 859         i2c_del_adapter(&i2c->adapter);
 860         kfree(i2c);
 861 }
 862
 863 void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
 864 {
 865         if (!i2c)
 866                 return;
 867
 868         i2c_del_adapter(&i2c->adapter);
 869         kfree(i2c);
 870 }
 871
 872 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
 873 {
 874         return NULL;
 875 }
 876
 877 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 878                          u8 slave_addr,
 879                          u8 addr,
 880                          u8 *val)
 881 {
 882         u8 out_buf[2];
 883         u8 in_buf[2];
 884         struct i2c_msg msgs[] = {
 885                 {
 886                         .addr = slave_addr,
 887                         .flags = 0,
 888                         .len = 1,
 889                         .buf = out_buf,
 890                 },
 891                 {
 892                         .addr = slave_addr,
 893                         .flags = I2C_M_RD,
 894                         .len = 1,
 895                         .buf = in_buf,
 896                 }
 897         };
 898
 899         out_buf[0] = addr;
 900         out_buf[1] = 0;
 901
 902         if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
 903                 *val = in_buf[0];
 904                 DRM_DEBUG("val = 0x%02x\n", *val);
 905         } else {
 906                 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
 907                           addr, *val);
 908         }
 909 }
 910
 911 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
 912                          u8 slave_addr,
 913                          u8 addr,
 914                          u8 val)
 915 {
 916         uint8_t out_buf[2];
 917         struct i2c_msg msg = {
 918                 .addr = slave_addr,
 919                 .flags = 0,
 920                 .len = 2,
 921                 .buf = out_buf,
 922         };
 923
 924         out_buf[0] = addr;
 925         out_buf[1] = val;
 926
 927         if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
 928                 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
 929                           addr, val);
 930 }
 931