2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "drm_sarea.h"
31 #include "radeon_drm.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
36 int radeon_driver_unload_kms(struct drm_device *dev)
38 struct radeon_device *rdev = dev->dev_private;
42 radeon_modeset_fini(rdev);
43 radeon_device_fini(rdev);
45 dev->dev_private = NULL;
49 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
51 struct radeon_device *rdev;
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
58 dev->dev_private = (void *)rdev;
61 if (drm_device_is_agp(dev)) {
62 flags |= RADEON_IS_AGP;
63 } else if (drm_device_is_pcie(dev)) {
64 flags |= RADEON_IS_PCIE;
66 flags |= RADEON_IS_PCI;
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
75 r = radeon_device_init(rdev, dev, dev->pdev, flags);
77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
84 dev_err(&dev->pdev->dev, "Error during ACPI methods call\n");
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
90 r = radeon_modeset_init(rdev);
92 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
95 radeon_driver_unload_kms(dev);
101 * Userspace get informations ioctl
103 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
105 struct radeon_device *rdev = dev->dev_private;
106 struct drm_radeon_info *info;
107 struct radeon_mode_info *minfo = &rdev->mode_info;
110 struct drm_crtc *crtc;
114 value_ptr = (uint32_t *)((unsigned long)info->value);
116 switch (info->request) {
117 case RADEON_INFO_DEVICE_ID:
118 value = dev->pci_device;
120 case RADEON_INFO_NUM_GB_PIPES:
121 value = rdev->num_gb_pipes;
123 case RADEON_INFO_NUM_Z_PIPES:
124 value = rdev->num_z_pipes;
126 case RADEON_INFO_ACCEL_WORKING:
127 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
128 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
131 value = rdev->accel_working;
133 case RADEON_INFO_CRTC_FROM_ID:
134 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
135 crtc = (struct drm_crtc *)minfo->crtcs[i];
136 if (crtc && crtc->base.id == value) {
143 DRM_DEBUG("unknown crtc id %d\n", value);
147 case RADEON_INFO_ACCEL_WORKING2:
148 value = rdev->accel_working;
151 DRM_DEBUG("Invalid request %d\n", info->request);
154 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
155 DRM_ERROR("copy_to_user\n");
163 * Outdated mess for old drm with Xorg being in charge (void function now).
165 int radeon_driver_firstopen_kms(struct drm_device *dev)
171 void radeon_driver_lastclose_kms(struct drm_device *dev)
173 vga_switcheroo_process_delayed_switch();
176 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
181 void radeon_driver_postclose_kms(struct drm_device *dev,
182 struct drm_file *file_priv)
186 void radeon_driver_preclose_kms(struct drm_device *dev,
187 struct drm_file *file_priv)
193 * VBlank related functions.
195 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
197 struct radeon_device *rdev = dev->dev_private;
199 if (crtc < 0 || crtc >= rdev->num_crtc) {
200 DRM_ERROR("Invalid crtc %d\n", crtc);
204 return radeon_get_vblank_counter(rdev, crtc);
207 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
209 struct radeon_device *rdev = dev->dev_private;
211 if (crtc < 0 || crtc >= rdev->num_crtc) {
212 DRM_ERROR("Invalid crtc %d\n", crtc);
216 rdev->irq.crtc_vblank_int[crtc] = true;
218 return radeon_irq_set(rdev);
221 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
223 struct radeon_device *rdev = dev->dev_private;
225 if (crtc < 0 || crtc >= rdev->num_crtc) {
226 DRM_ERROR("Invalid crtc %d\n", crtc);
230 rdev->irq.crtc_vblank_int[crtc] = false;
232 radeon_irq_set(rdev);
239 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
240 struct drm_file *file_priv)
242 /* Not valid in KMS. */
246 #define KMS_INVALID_IOCTL(name) \
247 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
249 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
254 * All these ioctls are invalid in kms world.
256 KMS_INVALID_IOCTL(radeon_cp_init_kms)
257 KMS_INVALID_IOCTL(radeon_cp_start_kms)
258 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
259 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
260 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
261 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
262 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
263 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
264 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
265 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
266 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
267 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
268 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
269 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
270 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
271 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
272 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
273 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
274 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
275 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
276 KMS_INVALID_IOCTL(radeon_mem_free_kms)
277 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
278 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
279 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
280 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
281 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
282 KMS_INVALID_IOCTL(radeon_surface_free_kms)
285 struct drm_ioctl_desc radeon_ioctls_kms[] = {
286 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
287 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
288 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
289 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
290 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
291 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
292 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
293 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
294 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
295 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
296 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
297 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
298 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
299 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
300 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
301 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
302 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
303 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
304 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
305 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
306 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
307 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
308 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
309 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
310 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
311 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
312 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
314 DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
315 DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
316 DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
317 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
318 DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
319 DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
320 DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
321 DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
322 DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
323 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
324 DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
325 DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
327 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);