drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35
  36 /**
  37  * radeon_driver_unload_kms - Main unload function for KMS.
  38  *
  39  * @dev: drm dev pointer
  40  *
  41  * This is the main unload function for KMS (all asics).
  42  * It calls radeon_modeset_fini() to tear down the
  43  * displays, and radeon_device_fini() to tear down
  44  * the rest of the device (CP, writeback, etc.).
  45  * Returns 0 on success.
  46  */
  47 int radeon_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct radeon_device *rdev = dev->dev_private;
  50
  51         if (rdev == NULL)
  52                 return 0;
  53         radeon_acpi_fini(rdev);
  54         radeon_modeset_fini(rdev);
  55         radeon_device_fini(rdev);
  56         kfree(rdev);
  57         dev->dev_private = NULL;
  58         return 0;
  59 }
  60
  61 /**
  62  * radeon_driver_load_kms - Main load function for KMS.
  63  *
  64  * @dev: drm dev pointer
  65  * @flags: device flags
  66  *
  67  * This is the main load function for KMS (all asics).
  68  * It calls radeon_device_init() to set up the non-display
  69  * parts of the chip (asic init, CP, writeback, etc.), and
  70  * radeon_modeset_init() to set up the display parts
  71  * (crtcs, encoders, hotplug detect, etc.).
  72  * Returns 0 on success, error on failure.
  73  */
  74 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  75 {
  76         struct radeon_device *rdev;
  77         int r, acpi_status;
  78
  79         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  80         if (rdev == NULL) {
  81                 return -ENOMEM;
  82         }
  83         dev->dev_private = (void *)rdev;
  84
  85         /* update BUS flag */
  86         if (drm_pci_device_is_agp(dev)) {
  87                 flags |= RADEON_IS_AGP;
  88         } else if (pci_is_pcie(dev->pdev)) {
  89                 flags |= RADEON_IS_PCIE;
  90         } else {
  91                 flags |= RADEON_IS_PCI;
  92         }
  93
  94         /* radeon_device_init should report only fatal error
  95          * like memory allocation failure or iomapping failure,
  96          * or memory manager initialization failure, it must
  97          * properly initialize the GPU MC controller and permit
  98          * VRAM allocation
  99          */
 100         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 101         if (r) {
 102                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 103                 goto out;
 104         }
 105
 106         /* Again modeset_init should fail only on fatal error
 107          * otherwise it should provide enough functionalities
 108          * for shadowfb to run
 109          */
 110         r = radeon_modeset_init(rdev);
 111         if (r)
 112                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 113
 114         /* Call ACPI methods: require modeset init
 115          * but failure is not fatal
 116          */
 117         if (!r) {
 118                 acpi_status = radeon_acpi_init(rdev);
 119                 if (acpi_status)
 120                 dev_dbg(&dev->pdev->dev,
 121                                 "Error during ACPI methods call\n");
 122         }
 123
 124 out:
 125         if (r)
 126                 radeon_driver_unload_kms(dev);
 127         return r;
 128 }
 129
 130 /**
 131  * radeon_set_filp_rights - Set filp right.
 132  *
 133  * @dev: drm dev pointer
 134  * @owner: drm file
 135  * @applier: drm file
 136  * @value: value
 137  *
 138  * Sets the filp rights for the device (all asics).
 139  */
 140 static void radeon_set_filp_rights(struct drm_device *dev,
 141                                    struct drm_file **owner,
 142                                    struct drm_file *applier,
 143                                    uint32_t *value)
 144 {
 145         mutex_lock(&dev->struct_mutex);
 146         if (*value == 1) {
 147                 /* wants rights */
 148                 if (!*owner)
 149                         *owner = applier;
 150         } else if (*value == 0) {
 151                 /* revokes rights */
 152                 if (*owner == applier)
 153                         *owner = NULL;
 154         }
 155         *value = *owner == applier ? 1 : 0;
 156         mutex_unlock(&dev->struct_mutex);
 157 }
 158
 159 /*
 160  * Userspace get information ioctl
 161  */
 162 /**
 163  * radeon_info_ioctl - answer a device specific request.
 164  *
 165  * @rdev: radeon device pointer
 166  * @data: request object
 167  * @filp: drm filp
 168  *
 169  * This function is used to pass device specific parameters to the userspace
 170  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 171  * etc. (all asics).
 172  * Returns 0 on success, -EINVAL on failure.
 173  */
 174 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 175 {
 176         struct radeon_device *rdev = dev->dev_private;
 177         struct drm_radeon_info *info = data;
 178         struct radeon_mode_info *minfo = &rdev->mode_info;
 179         uint32_t *value, value_tmp, *value_ptr, value_size;
 180         uint64_t value64;
 181         struct drm_crtc *crtc;
 182         int i, found;
 183
 184         value_ptr = (uint32_t *)((unsigned long)info->value);
 185         value = &value_tmp;
 186         value_size = sizeof(uint32_t);
 187
 188         switch (info->request) {
 189         case RADEON_INFO_DEVICE_ID:
 190                 *value = dev->pci_device;
 191                 break;
 192         case RADEON_INFO_NUM_GB_PIPES:
 193                 *value = rdev->num_gb_pipes;
 194                 break;
 195         case RADEON_INFO_NUM_Z_PIPES:
 196                 *value = rdev->num_z_pipes;
 197                 break;
 198         case RADEON_INFO_ACCEL_WORKING:
 199                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 200                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 201                         *value = false;
 202                 else
 203                         *value = rdev->accel_working;
 204                 break;
 205         case RADEON_INFO_CRTC_FROM_ID:
 206                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 207                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 208                         return -EFAULT;
 209                 }
 210                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 211                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 212                         if (crtc && crtc->base.id == *value) {
 213                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 214                                 *value = radeon_crtc->crtc_id;
 215                                 found = 1;
 216                                 break;
 217                         }
 218                 }
 219                 if (!found) {
 220                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 221                         return -EINVAL;
 222                 }
 223                 break;
 224         case RADEON_INFO_ACCEL_WORKING2:
 225                 *value = rdev->accel_working;
 226                 break;
 227         case RADEON_INFO_TILING_CONFIG:
 228                 if (rdev->family >= CHIP_TAHITI)
 229                         *value = rdev->config.si.tile_config;
 230                 else if (rdev->family >= CHIP_CAYMAN)
 231                         *value = rdev->config.cayman.tile_config;
 232                 else if (rdev->family >= CHIP_CEDAR)
 233                         *value = rdev->config.evergreen.tile_config;
 234                 else if (rdev->family >= CHIP_RV770)
 235                         *value = rdev->config.rv770.tile_config;
 236                 else if (rdev->family >= CHIP_R600)
 237                         *value = rdev->config.r600.tile_config;
 238                 else {
 239                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 240                         return -EINVAL;
 241                 }
 242                 break;
 243         case RADEON_INFO_WANT_HYPERZ:
 244                 /* The "value" here is both an input and output parameter.
 245                  * If the input value is 1, filp requests hyper-z access.
 246                  * If the input value is 0, filp revokes its hyper-z access.
 247                  *
 248                  * When returning, the value is 1 if filp owns hyper-z access,
 249                  * 0 otherwise. */
 250                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 251                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 252                         return -EFAULT;
 253                 }
 254                 if (*value >= 2) {
 255                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 256                         return -EINVAL;
 257                 }
 258                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 259                 break;
 260         case RADEON_INFO_WANT_CMASK:
 261                 /* The same logic as Hyper-Z. */
 262                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 263                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 264                         return -EFAULT;
 265                 }
 266                 if (*value >= 2) {
 267                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 268                         return -EINVAL;
 269                 }
 270                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 271                 break;
 272         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 273                 /* return clock value in KHz */
 274                 if (rdev->asic->get_xclk)
 275                         *value = radeon_get_xclk(rdev) * 10;
 276                 else
 277                         *value = rdev->clock.spll.reference_freq * 10;
 278                 break;
 279         case RADEON_INFO_NUM_BACKENDS:
 280                 if (rdev->family >= CHIP_TAHITI)
 281                         *value = rdev->config.si.max_backends_per_se *
 282                                 rdev->config.si.max_shader_engines;
 283                 else if (rdev->family >= CHIP_CAYMAN)
 284                         *value = rdev->config.cayman.max_backends_per_se *
 285                                 rdev->config.cayman.max_shader_engines;
 286                 else if (rdev->family >= CHIP_CEDAR)
 287                         *value = rdev->config.evergreen.max_backends;
 288                 else if (rdev->family >= CHIP_RV770)
 289                         *value = rdev->config.rv770.max_backends;
 290                 else if (rdev->family >= CHIP_R600)
 291                         *value = rdev->config.r600.max_backends;
 292                 else {
 293                         return -EINVAL;
 294                 }
 295                 break;
 296         case RADEON_INFO_NUM_TILE_PIPES:
 297                 if (rdev->family >= CHIP_TAHITI)
 298                         *value = rdev->config.si.max_tile_pipes;
 299                 else if (rdev->family >= CHIP_CAYMAN)
 300                         *value = rdev->config.cayman.max_tile_pipes;
 301                 else if (rdev->family >= CHIP_CEDAR)
 302                         *value = rdev->config.evergreen.max_tile_pipes;
 303                 else if (rdev->family >= CHIP_RV770)
 304                         *value = rdev->config.rv770.max_tile_pipes;
 305                 else if (rdev->family >= CHIP_R600)
 306                         *value = rdev->config.r600.max_tile_pipes;
 307                 else {
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case RADEON_INFO_FUSION_GART_WORKING:
 312                 *value = 1;
 313                 break;
 314         case RADEON_INFO_BACKEND_MAP:
 315                 if (rdev->family >= CHIP_TAHITI)
 316                         *value = rdev->config.si.backend_map;
 317                 else if (rdev->family >= CHIP_CAYMAN)
 318                         *value = rdev->config.cayman.backend_map;
 319                 else if (rdev->family >= CHIP_CEDAR)
 320                         *value = rdev->config.evergreen.backend_map;
 321                 else if (rdev->family >= CHIP_RV770)
 322                         *value = rdev->config.rv770.backend_map;
 323                 else if (rdev->family >= CHIP_R600)
 324                         *value = rdev->config.r600.backend_map;
 325                 else {
 326                         return -EINVAL;
 327                 }
 328                 break;
 329         case RADEON_INFO_VA_START:
 330                 /* this is where we report if vm is supported or not */
 331                 if (rdev->family < CHIP_CAYMAN)
 332                         return -EINVAL;
 333                 *value = RADEON_VA_RESERVED_SIZE;
 334                 break;
 335         case RADEON_INFO_IB_VM_MAX_SIZE:
 336                 /* this is where we report if vm is supported or not */
 337                 if (rdev->family < CHIP_CAYMAN)
 338                         return -EINVAL;
 339                 *value = RADEON_IB_VM_MAX_SIZE;
 340                 break;
 341         case RADEON_INFO_MAX_PIPES:
 342                 if (rdev->family >= CHIP_TAHITI)
 343                         *value = rdev->config.si.max_cu_per_sh;
 344                 else if (rdev->family >= CHIP_CAYMAN)
 345                         *value = rdev->config.cayman.max_pipes_per_simd;
 346                 else if (rdev->family >= CHIP_CEDAR)
 347                         *value = rdev->config.evergreen.max_pipes;
 348                 else if (rdev->family >= CHIP_RV770)
 349                         *value = rdev->config.rv770.max_pipes;
 350                 else if (rdev->family >= CHIP_R600)
 351                         *value = rdev->config.r600.max_pipes;
 352                 else {
 353                         return -EINVAL;
 354                 }
 355                 break;
 356         case RADEON_INFO_TIMESTAMP:
 357                 if (rdev->family < CHIP_R600) {
 358                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 359                         return -EINVAL;
 360                 }
 361                 value = (uint32_t*)&value64;
 362                 value_size = sizeof(uint64_t);
 363                 value64 = radeon_get_gpu_clock_counter(rdev);
 364                 break;
 365         case RADEON_INFO_MAX_SE:
 366                 if (rdev->family >= CHIP_TAHITI)
 367                         *value = rdev->config.si.max_shader_engines;
 368                 else if (rdev->family >= CHIP_CAYMAN)
 369                         *value = rdev->config.cayman.max_shader_engines;
 370                 else if (rdev->family >= CHIP_CEDAR)
 371                         *value = rdev->config.evergreen.num_ses;
 372                 else
 373                         *value = 1;
 374                 break;
 375         case RADEON_INFO_MAX_SH_PER_SE:
 376                 if (rdev->family >= CHIP_TAHITI)
 377                         *value = rdev->config.si.max_sh_per_se;
 378                 else
 379                         return -EINVAL;
 380                 break;
 381         case RADEON_INFO_FASTFB_WORKING:
 382                 *value = rdev->fastfb_working;
 383                 break;
 384         case RADEON_INFO_RING_WORKING:
 385                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 386                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 387                         return -EFAULT;
 388                 }
 389                 switch (*value) {
 390                 case RADEON_CS_RING_GFX:
 391                 case RADEON_CS_RING_COMPUTE:
 392                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 393                         break;
 394                 case RADEON_CS_RING_DMA:
 395                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 396                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 397                         break;
 398                 case RADEON_CS_RING_UVD:
 399                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 400                         break;
 401                 default:
 402                         return -EINVAL;
 403                 }
 404                 break;
 405         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 406                 if (rdev->family < CHIP_TAHITI) {
 407                         DRM_DEBUG_KMS("tile mode array is si only!\n");
 408                         return -EINVAL;
 409                 }
 410                 value = rdev->config.si.tile_mode_array;
 411                 value_size = sizeof(uint32_t)*32;
 412                 break;
 413         default:
 414                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 415                 return -EINVAL;
 416         }
 417         if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
 418                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 419                 return -EFAULT;
 420         }
 421         return 0;
 422 }
 423
 424
 425 /*
 426  * Outdated mess for old drm with Xorg being in charge (void function now).
 427  */
 428 /**
 429  * radeon_driver_firstopen_kms - drm callback for first open
 430  *
 431  * @dev: drm dev pointer
 432  *
 433  * Nothing to be done for KMS (all asics).
 434  * Returns 0 on success.
 435  */
 436 int radeon_driver_firstopen_kms(struct drm_device *dev)
 437 {
 438         return 0;
 439 }
 440
 441 /**
 442  * radeon_driver_firstopen_kms - drm callback for last close
 443  *
 444  * @dev: drm dev pointer
 445  *
 446  * Switch vga switcheroo state after last close (all asics).
 447  */
 448 void radeon_driver_lastclose_kms(struct drm_device *dev)
 449 {
 450         vga_switcheroo_process_delayed_switch();
 451 }
 452
 453 /**
 454  * radeon_driver_open_kms - drm callback for open
 455  *
 456  * @dev: drm dev pointer
 457  * @file_priv: drm file
 458  *
 459  * On device open, init vm on cayman+ (all asics).
 460  * Returns 0 on success, error on failure.
 461  */
 462 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 463 {
 464         struct radeon_device *rdev = dev->dev_private;
 465
 466         file_priv->driver_priv = NULL;
 467
 468         /* new gpu have virtual address space support */
 469         if (rdev->family >= CHIP_CAYMAN) {
 470                 struct radeon_fpriv *fpriv;
 471                 struct radeon_bo_va *bo_va;
 472                 int r;
 473
 474                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 475                 if (unlikely(!fpriv)) {
 476                         return -ENOMEM;
 477                 }
 478
 479                 radeon_vm_init(rdev, &fpriv->vm);
 480
 481                 /* map the ib pool buffer read only into
 482                  * virtual address space */
 483                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 484                                          rdev->ring_tmp_bo.bo);
 485                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 486                                           RADEON_VM_PAGE_READABLE |
 487                                           RADEON_VM_PAGE_SNOOPED);
 488                 if (r) {
 489                         radeon_vm_fini(rdev, &fpriv->vm);
 490                         kfree(fpriv);
 491                         return r;
 492                 }
 493
 494                 file_priv->driver_priv = fpriv;
 495         }
 496         return 0;
 497 }
 498
 499 /**
 500  * radeon_driver_postclose_kms - drm callback for post close
 501  *
 502  * @dev: drm dev pointer
 503  * @file_priv: drm file
 504  *
 505  * On device post close, tear down vm on cayman+ (all asics).
 506  */
 507 void radeon_driver_postclose_kms(struct drm_device *dev,
 508                                  struct drm_file *file_priv)
 509 {
 510         struct radeon_device *rdev = dev->dev_private;
 511
 512         /* new gpu have virtual address space support */
 513         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 514                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 515                 struct radeon_bo_va *bo_va;
 516                 int r;
 517
 518                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 519                 if (!r) {
 520                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 521                                                   rdev->ring_tmp_bo.bo);
 522                         if (bo_va)
 523                                 radeon_vm_bo_rmv(rdev, bo_va);
 524                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 525                 }
 526
 527                 radeon_vm_fini(rdev, &fpriv->vm);
 528                 kfree(fpriv);
 529                 file_priv->driver_priv = NULL;
 530         }
 531 }
 532
 533 /**
 534  * radeon_driver_preclose_kms - drm callback for pre close
 535  *
 536  * @dev: drm dev pointer
 537  * @file_priv: drm file
 538  *
 539  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 540  * (all asics).
 541  */
 542 void radeon_driver_preclose_kms(struct drm_device *dev,
 543                                 struct drm_file *file_priv)
 544 {
 545         struct radeon_device *rdev = dev->dev_private;
 546         if (rdev->hyperz_filp == file_priv)
 547                 rdev->hyperz_filp = NULL;
 548         if (rdev->cmask_filp == file_priv)
 549                 rdev->cmask_filp = NULL;
 550         radeon_uvd_free_handles(rdev, file_priv);
 551 }
 552
 553 /*
 554  * VBlank related functions.
 555  */
 556 /**
 557  * radeon_get_vblank_counter_kms - get frame count
 558  *
 559  * @dev: drm dev pointer
 560  * @crtc: crtc to get the frame count from
 561  *
 562  * Gets the frame count on the requested crtc (all asics).
 563  * Returns frame count on success, -EINVAL on failure.
 564  */
 565 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 566 {
 567         struct radeon_device *rdev = dev->dev_private;
 568
 569         if (crtc < 0 || crtc >= rdev->num_crtc) {
 570                 DRM_ERROR("Invalid crtc %d\n", crtc);
 571                 return -EINVAL;
 572         }
 573
 574         return radeon_get_vblank_counter(rdev, crtc);
 575 }
 576
 577 /**
 578  * radeon_enable_vblank_kms - enable vblank interrupt
 579  *
 580  * @dev: drm dev pointer
 581  * @crtc: crtc to enable vblank interrupt for
 582  *
 583  * Enable the interrupt on the requested crtc (all asics).
 584  * Returns 0 on success, -EINVAL on failure.
 585  */
 586 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 587 {
 588         struct radeon_device *rdev = dev->dev_private;
 589         unsigned long irqflags;
 590         int r;
 591
 592         if (crtc < 0 || crtc >= rdev->num_crtc) {
 593                 DRM_ERROR("Invalid crtc %d\n", crtc);
 594                 return -EINVAL;
 595         }
 596
 597         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 598         rdev->irq.crtc_vblank_int[crtc] = true;
 599         r = radeon_irq_set(rdev);
 600         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 601         return r;
 602 }
 603
 604 /**
 605  * radeon_disable_vblank_kms - disable vblank interrupt
 606  *
 607  * @dev: drm dev pointer
 608  * @crtc: crtc to disable vblank interrupt for
 609  *
 610  * Disable the interrupt on the requested crtc (all asics).
 611  */
 612 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 613 {
 614         struct radeon_device *rdev = dev->dev_private;
 615         unsigned long irqflags;
 616
 617         if (crtc < 0 || crtc >= rdev->num_crtc) {
 618                 DRM_ERROR("Invalid crtc %d\n", crtc);
 619                 return;
 620         }
 621
 622         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 623         rdev->irq.crtc_vblank_int[crtc] = false;
 624         radeon_irq_set(rdev);
 625         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 626 }
 627
 628 /**
 629  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 630  *
 631  * @dev: drm dev pointer
 632  * @crtc: crtc to get the timestamp for
 633  * @max_error: max error
 634  * @vblank_time: time value
 635  * @flags: flags passed to the driver
 636  *
 637  * Gets the timestamp on the requested crtc based on the
 638  * scanout position.  (all asics).
 639  * Returns postive status flags on success, negative error on failure.
 640  */
 641 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 642                                     int *max_error,
 643                                     struct timeval *vblank_time,
 644                                     unsigned flags)
 645 {
 646         struct drm_crtc *drmcrtc;
 647         struct radeon_device *rdev = dev->dev_private;
 648
 649         if (crtc < 0 || crtc >= dev->num_crtcs) {
 650                 DRM_ERROR("Invalid crtc %d\n", crtc);
 651                 return -EINVAL;
 652         }
 653
 654         /* Get associated drm_crtc: */
 655         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 656
 657         /* Helper routine in DRM core does all the work: */
 658         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 659                                                      vblank_time, flags,
 660                                                      drmcrtc);
 661 }
 662
 663 /*
 664  * IOCTL.
 665  */
 666 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 667                          struct drm_file *file_priv)
 668 {
 669         /* Not valid in KMS. */
 670         return -EINVAL;
 671 }
 672
 673 #define KMS_INVALID_IOCTL(name)                                         \
 674 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 675 {                                                                       \
 676         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 677         return -EINVAL;                                                 \
 678 }
 679
 680 /*
 681  * All these ioctls are invalid in kms world.
 682  */
 683 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 684 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 685 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 686 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 687 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 688 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 689 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 690 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 691 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 692 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 693 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 694 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 695 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 696 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 697 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 698 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 699 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 700 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 701 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 702 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 703 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 704 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 705 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 706 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 707 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 708 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 709 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 710
 711
 712 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 713         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 714         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 715         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 716         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 717         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 718         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 719         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 720         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 721         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 722         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 723         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 724         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 725         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 726         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 727         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 728         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 729         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 730         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 731         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 732         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 733         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 734         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 735         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 736         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 737         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 738         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 739         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 740         /* KMS */
 741         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 742         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 743         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 744         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 745         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 746         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 747         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 748         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 749         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 750         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 751         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 752         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 753         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
 754 };
 755 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);