2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39 struct drm_encoder_helper_funcs *encoder_funcs;
41 encoder_funcs = encoder->helper_private;
42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
43 radeon_encoder->active_device = 0;
46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
48 struct drm_device *dev = encoder->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
52 int panel_pwr_delay = 2000;
54 uint8_t backlight_level;
57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
60 if (radeon_encoder->enc_priv) {
61 if (rdev->is_atom_bios) {
62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
63 panel_pwr_delay = lvds->panel_pwr_delay;
65 backlight_level = lvds->backlight_level;
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
68 panel_pwr_delay = lvds->panel_pwr_delay;
70 backlight_level = lvds->backlight_level;
74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
75 * Taken from radeonfb.
77 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
84 case DRM_MODE_DPMS_ON:
85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
98 RADEON_LVDS_BL_MOD_LEVEL_MASK);
99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
104 mdelay(panel_pwr_delay);
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
107 case DRM_MODE_DPMS_STANDBY:
108 case DRM_MODE_DPMS_SUSPEND:
109 case DRM_MODE_DPMS_OFF:
110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
121 mdelay(panel_pwr_delay);
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
124 mdelay(panel_pwr_delay);
128 if (rdev->is_atom_bios)
129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
137 struct radeon_device *rdev = encoder->dev->dev_private;
138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
141 if (radeon_encoder->enc_priv) {
142 if (rdev->is_atom_bios) {
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
144 lvds->dpms_mode = mode;
146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
147 lvds->dpms_mode = mode;
151 radeon_legacy_lvds_update(encoder, mode);
154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
156 struct radeon_device *rdev = encoder->dev->dev_private;
158 if (rdev->is_atom_bios)
159 radeon_atom_output_lock(encoder, true);
161 radeon_combios_output_lock(encoder, true);
162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
167 struct radeon_device *rdev = encoder->dev->dev_private;
169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
170 if (rdev->is_atom_bios)
171 radeon_atom_output_lock(encoder, false);
173 radeon_combios_output_lock(encoder, false);
176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
177 struct drm_display_mode *mode,
178 struct drm_display_mode *adjusted_mode)
180 struct drm_device *dev = encoder->dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
192 if (rdev->is_atom_bios) {
193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
194 * need to call that on resume to set up the reg properly.
196 radeon_encoder->pixel_clock = adjusted_mode->clock;
197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
203 lvds_gen_cntl = lvds->lvds_gen_cntl;
204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
212 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
217 if (ASIC_IS_R300(rdev))
218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
220 if (radeon_crtc->crtc_id == 0) {
221 if (ASIC_IS_R300(rdev)) {
222 if (radeon_encoder->rmx_type != RMX_OFF)
223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
227 if (ASIC_IS_R300(rdev))
228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
237 if (rdev->family == CHIP_RV410)
238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
240 if (rdev->is_atom_bios)
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
247 const struct drm_display_mode *mode,
248 struct drm_display_mode *adjusted_mode)
250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 /* set the active encoder to connector routing */
253 radeon_encoder_set_active_device(encoder);
254 drm_mode_set_crtcinfo(adjusted_mode, 0);
256 /* get the native mode for LVDS */
257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
258 radeon_panel_mode_fixup(encoder, adjusted_mode);
263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
264 .dpms = radeon_legacy_lvds_dpms,
265 .mode_fixup = radeon_legacy_mode_fixup,
266 .prepare = radeon_legacy_lvds_prepare,
267 .mode_set = radeon_legacy_lvds_mode_set,
268 .commit = radeon_legacy_lvds_commit,
269 .disable = radeon_legacy_encoder_disable,
273 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
275 struct drm_device *dev = radeon_encoder->base.dev;
276 struct radeon_device *rdev = dev->dev_private;
279 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
280 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
282 return backlight_level;
286 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
288 struct drm_device *dev = radeon_encoder->base.dev;
289 struct radeon_device *rdev = dev->dev_private;
290 int dpms_mode = DRM_MODE_DPMS_ON;
292 if (radeon_encoder->enc_priv) {
293 if (rdev->is_atom_bios) {
294 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
295 if (lvds->backlight_level > 0)
296 dpms_mode = lvds->dpms_mode;
298 dpms_mode = DRM_MODE_DPMS_OFF;
299 lvds->backlight_level = level;
301 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
302 if (lvds->backlight_level > 0)
303 dpms_mode = lvds->dpms_mode;
305 dpms_mode = DRM_MODE_DPMS_OFF;
306 lvds->backlight_level = level;
310 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
313 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
315 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
317 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
320 /* Convert brightness to hardware level */
321 if (bd->props.brightness < 0)
323 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
324 level = RADEON_MAX_BL_LEVEL;
326 level = bd->props.brightness;
329 level = RADEON_MAX_BL_LEVEL - level;
334 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
336 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
337 struct radeon_encoder *radeon_encoder = pdata->encoder;
339 radeon_legacy_set_backlight_level(radeon_encoder,
340 radeon_legacy_lvds_level(bd));
345 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
347 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
348 struct radeon_encoder *radeon_encoder = pdata->encoder;
349 struct drm_device *dev = radeon_encoder->base.dev;
350 struct radeon_device *rdev = dev->dev_private;
351 uint8_t backlight_level;
353 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
354 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
356 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
359 static const struct backlight_ops radeon_backlight_ops = {
360 .get_brightness = radeon_legacy_backlight_get_brightness,
361 .update_status = radeon_legacy_backlight_update_status,
364 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
365 struct drm_connector *drm_connector)
367 struct drm_device *dev = radeon_encoder->base.dev;
368 struct radeon_device *rdev = dev->dev_private;
369 struct backlight_device *bd;
370 struct backlight_properties props;
371 struct radeon_backlight_privdata *pdata;
372 uint8_t backlight_level;
375 if (!radeon_encoder->enc_priv)
378 #ifdef CONFIG_PMAC_BACKLIGHT
379 if (!pmac_has_backlight_type("ati") &&
380 !pmac_has_backlight_type("mnca"))
384 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
386 DRM_ERROR("Memory allocation failed\n");
390 memset(&props, 0, sizeof(props));
391 props.max_brightness = RADEON_MAX_BL_LEVEL;
392 props.type = BACKLIGHT_RAW;
393 snprintf(bl_name, sizeof(bl_name),
394 "radeon_bl%d", dev->primary->index);
395 bd = backlight_device_register(bl_name, &drm_connector->kdev,
396 pdata, &radeon_backlight_ops, &props);
398 DRM_ERROR("Backlight registration failed\n");
402 pdata->encoder = radeon_encoder;
404 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
405 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
407 /* First, try to detect backlight level sense based on the assumption
408 * that firmware set it up at full brightness
410 if (backlight_level == 0)
411 pdata->negative = true;
412 else if (backlight_level == 0xff)
413 pdata->negative = false;
415 /* XXX hack... maybe some day we can figure out in what direction
416 * backlight should work on a given panel?
418 pdata->negative = (rdev->family != CHIP_RV200 &&
419 rdev->family != CHIP_RV250 &&
420 rdev->family != CHIP_RV280 &&
421 rdev->family != CHIP_RV350);
423 #ifdef CONFIG_PMAC_BACKLIGHT
424 pdata->negative = (pdata->negative ||
425 of_machine_is_compatible("PowerBook4,3") ||
426 of_machine_is_compatible("PowerBook6,3") ||
427 of_machine_is_compatible("PowerBook6,5"));
431 if (rdev->is_atom_bios) {
432 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
435 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
439 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
440 bd->props.power = FB_BLANK_UNBLANK;
441 backlight_update_status(bd);
443 DRM_INFO("radeon legacy LVDS backlight initialized\n");
452 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
454 struct drm_device *dev = radeon_encoder->base.dev;
455 struct radeon_device *rdev = dev->dev_private;
456 struct backlight_device *bd = NULL;
458 if (!radeon_encoder->enc_priv)
461 if (rdev->is_atom_bios) {
462 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
466 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
472 struct radeon_backlight_privdata *pdata;
474 pdata = bl_get_data(bd);
475 backlight_device_unregister(bd);
478 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
482 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
484 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
488 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
495 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 if (radeon_encoder->enc_priv) {
500 radeon_legacy_backlight_exit(radeon_encoder);
501 kfree(radeon_encoder->enc_priv);
503 drm_encoder_cleanup(encoder);
504 kfree(radeon_encoder);
507 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
508 .destroy = radeon_lvds_enc_destroy,
511 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
513 struct drm_device *dev = encoder->dev;
514 struct radeon_device *rdev = dev->dev_private;
515 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
516 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
517 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
522 case DRM_MODE_DPMS_ON:
523 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
524 dac_cntl &= ~RADEON_DAC_PDWN;
525 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
529 case DRM_MODE_DPMS_STANDBY:
530 case DRM_MODE_DPMS_SUSPEND:
531 case DRM_MODE_DPMS_OFF:
532 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
533 dac_cntl |= RADEON_DAC_PDWN;
534 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
540 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
541 WREG32(RADEON_DAC_CNTL, dac_cntl);
542 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
544 if (rdev->is_atom_bios)
545 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
547 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
551 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
553 struct radeon_device *rdev = encoder->dev->dev_private;
555 if (rdev->is_atom_bios)
556 radeon_atom_output_lock(encoder, true);
558 radeon_combios_output_lock(encoder, true);
559 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
562 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
564 struct radeon_device *rdev = encoder->dev->dev_private;
566 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
568 if (rdev->is_atom_bios)
569 radeon_atom_output_lock(encoder, false);
571 radeon_combios_output_lock(encoder, false);
574 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
575 struct drm_display_mode *mode,
576 struct drm_display_mode *adjusted_mode)
578 struct drm_device *dev = encoder->dev;
579 struct radeon_device *rdev = dev->dev_private;
580 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
581 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
582 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
586 if (radeon_crtc->crtc_id == 0) {
587 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
588 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
589 ~(RADEON_DISP_DAC_SOURCE_MASK);
590 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
592 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
593 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
596 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
597 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
598 ~(RADEON_DISP_DAC_SOURCE_MASK);
599 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
600 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
602 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
603 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
607 dac_cntl = (RADEON_DAC_MASK_ALL |
608 RADEON_DAC_VGA_ADR_EN |
612 WREG32_P(RADEON_DAC_CNTL,
614 RADEON_DAC_RANGE_CNTL |
615 RADEON_DAC_BLANKING);
617 if (radeon_encoder->enc_priv) {
618 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
619 dac_macro_cntl = p_dac->ps2_pdac_adj;
621 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
622 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
623 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
625 if (rdev->is_atom_bios)
626 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
628 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
631 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
632 struct drm_connector *connector)
634 struct drm_device *dev = encoder->dev;
635 struct radeon_device *rdev = dev->dev_private;
636 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
637 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
638 enum drm_connector_status found = connector_status_disconnected;
641 /* save the regs we need */
642 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
643 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
644 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
645 dac_cntl = RREG32(RADEON_DAC_CNTL);
646 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
648 tmp = vclk_ecp_cntl &
649 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
650 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
652 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
653 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
655 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
656 RADEON_DAC_FORCE_DATA_EN;
659 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
661 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
663 if (ASIC_IS_R300(rdev))
664 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
666 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
668 WREG32(RADEON_DAC_EXT_CNTL, tmp);
670 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
671 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
672 WREG32(RADEON_DAC_CNTL, tmp);
674 tmp &= ~(RADEON_DAC_PDWN_R |
678 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
682 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
683 found = connector_status_connected;
685 /* restore the regs we used */
686 WREG32(RADEON_DAC_CNTL, dac_cntl);
687 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
688 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
689 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
690 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
695 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
696 .dpms = radeon_legacy_primary_dac_dpms,
697 .mode_fixup = radeon_legacy_mode_fixup,
698 .prepare = radeon_legacy_primary_dac_prepare,
699 .mode_set = radeon_legacy_primary_dac_mode_set,
700 .commit = radeon_legacy_primary_dac_commit,
701 .detect = radeon_legacy_primary_dac_detect,
702 .disable = radeon_legacy_encoder_disable,
706 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
707 .destroy = radeon_enc_destroy,
710 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
712 struct drm_device *dev = encoder->dev;
713 struct radeon_device *rdev = dev->dev_private;
714 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
718 case DRM_MODE_DPMS_ON:
719 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
721 case DRM_MODE_DPMS_STANDBY:
722 case DRM_MODE_DPMS_SUSPEND:
723 case DRM_MODE_DPMS_OFF:
724 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
728 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
730 if (rdev->is_atom_bios)
731 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
733 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
737 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
739 struct radeon_device *rdev = encoder->dev->dev_private;
741 if (rdev->is_atom_bios)
742 radeon_atom_output_lock(encoder, true);
744 radeon_combios_output_lock(encoder, true);
745 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
748 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
750 struct radeon_device *rdev = encoder->dev->dev_private;
752 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
754 if (rdev->is_atom_bios)
755 radeon_atom_output_lock(encoder, true);
757 radeon_combios_output_lock(encoder, true);
760 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
761 struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode)
764 struct drm_device *dev = encoder->dev;
765 struct radeon_device *rdev = dev->dev_private;
766 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
767 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
768 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
773 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
775 if (rdev->family == CHIP_RV280) {
776 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
778 tmds_pll_cntl ^= (1 << 22);
781 if (radeon_encoder->enc_priv) {
782 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
784 for (i = 0; i < 4; i++) {
785 if (tmds->tmds_pll[i].freq == 0)
787 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
788 tmp = tmds->tmds_pll[i].value ;
794 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
795 if (tmp & 0xfff00000)
798 tmds_pll_cntl &= 0xfff00000;
799 tmds_pll_cntl |= tmp;
804 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
805 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
807 if (rdev->family == CHIP_R200 ||
808 rdev->family == CHIP_R100 ||
810 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
811 else /* RV chips got this bit reversed */
812 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
814 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
815 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
816 RADEON_FP_CRTC_DONT_SHADOW_HEND));
818 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
820 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
821 RADEON_FP_DFP_SYNC_SEL |
822 RADEON_FP_CRT_SYNC_SEL |
823 RADEON_FP_CRTC_LOCK_8DOT |
824 RADEON_FP_USE_SHADOW_EN |
825 RADEON_FP_CRTC_USE_SHADOW_VEND |
826 RADEON_FP_CRT_SYNC_ALT);
828 if (1) /* FIXME rgbBits == 8 */
829 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
831 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
833 if (radeon_crtc->crtc_id == 0) {
834 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
835 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
836 if (radeon_encoder->rmx_type != RMX_OFF)
837 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
839 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
841 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
843 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
844 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
845 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
847 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
850 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
851 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
852 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
854 if (rdev->is_atom_bios)
855 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
857 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
860 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
861 .dpms = radeon_legacy_tmds_int_dpms,
862 .mode_fixup = radeon_legacy_mode_fixup,
863 .prepare = radeon_legacy_tmds_int_prepare,
864 .mode_set = radeon_legacy_tmds_int_mode_set,
865 .commit = radeon_legacy_tmds_int_commit,
866 .disable = radeon_legacy_encoder_disable,
870 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
871 .destroy = radeon_enc_destroy,
874 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
876 struct drm_device *dev = encoder->dev;
877 struct radeon_device *rdev = dev->dev_private;
878 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
882 case DRM_MODE_DPMS_ON:
883 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
884 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
886 case DRM_MODE_DPMS_STANDBY:
887 case DRM_MODE_DPMS_SUSPEND:
888 case DRM_MODE_DPMS_OFF:
889 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
890 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
894 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
896 if (rdev->is_atom_bios)
897 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
899 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
903 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
905 struct radeon_device *rdev = encoder->dev->dev_private;
907 if (rdev->is_atom_bios)
908 radeon_atom_output_lock(encoder, true);
910 radeon_combios_output_lock(encoder, true);
911 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
914 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
916 struct radeon_device *rdev = encoder->dev->dev_private;
917 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
919 if (rdev->is_atom_bios)
920 radeon_atom_output_lock(encoder, false);
922 radeon_combios_output_lock(encoder, false);
925 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
926 struct drm_display_mode *mode,
927 struct drm_display_mode *adjusted_mode)
929 struct drm_device *dev = encoder->dev;
930 struct radeon_device *rdev = dev->dev_private;
931 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
932 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
933 uint32_t fp2_gen_cntl;
937 if (rdev->is_atom_bios) {
938 radeon_encoder->pixel_clock = adjusted_mode->clock;
939 atombios_dvo_setup(encoder, ATOM_ENABLE);
940 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
942 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
944 if (1) /* FIXME rgbBits == 8 */
945 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
947 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
949 fp2_gen_cntl &= ~(RADEON_FP2_ON |
951 RADEON_FP2_DVO_RATE_SEL_SDR);
953 /* XXX: these are oem specific */
954 if (ASIC_IS_R300(rdev)) {
955 if ((dev->pdev->device == 0x4850) &&
956 (dev->pdev->subsystem_vendor == 0x1028) &&
957 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
958 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
960 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
962 /*if (mode->clock > 165000)
963 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
965 if (!radeon_combios_external_tmds_setup(encoder))
966 radeon_external_tmds_setup(encoder);
969 if (radeon_crtc->crtc_id == 0) {
970 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
971 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
972 if (radeon_encoder->rmx_type != RMX_OFF)
973 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
975 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
977 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
979 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
980 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
981 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
983 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
986 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
988 if (rdev->is_atom_bios)
989 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
991 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
994 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
996 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
997 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
998 kfree(radeon_encoder->enc_priv);
999 drm_encoder_cleanup(encoder);
1000 kfree(radeon_encoder);
1003 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1004 .dpms = radeon_legacy_tmds_ext_dpms,
1005 .mode_fixup = radeon_legacy_mode_fixup,
1006 .prepare = radeon_legacy_tmds_ext_prepare,
1007 .mode_set = radeon_legacy_tmds_ext_mode_set,
1008 .commit = radeon_legacy_tmds_ext_commit,
1009 .disable = radeon_legacy_encoder_disable,
1013 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1014 .destroy = radeon_ext_tmds_enc_destroy,
1017 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1019 struct drm_device *dev = encoder->dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1022 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1023 uint32_t tv_master_cntl = 0;
1025 DRM_DEBUG_KMS("\n");
1027 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1029 if (rdev->family == CHIP_R200)
1030 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1033 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1035 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1036 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1040 case DRM_MODE_DPMS_ON:
1041 if (rdev->family == CHIP_R200) {
1042 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1045 tv_master_cntl |= RADEON_TV_ON;
1047 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1049 if (rdev->family == CHIP_R420 ||
1050 rdev->family == CHIP_R423 ||
1051 rdev->family == CHIP_RV410)
1052 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1053 R420_TV_DAC_GDACPD |
1054 R420_TV_DAC_BDACPD |
1055 RADEON_TV_DAC_BGSLEEP);
1057 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1058 RADEON_TV_DAC_GDACPD |
1059 RADEON_TV_DAC_BDACPD |
1060 RADEON_TV_DAC_BGSLEEP);
1063 case DRM_MODE_DPMS_STANDBY:
1064 case DRM_MODE_DPMS_SUSPEND:
1065 case DRM_MODE_DPMS_OFF:
1066 if (rdev->family == CHIP_R200)
1067 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1070 tv_master_cntl &= ~RADEON_TV_ON;
1072 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1074 if (rdev->family == CHIP_R420 ||
1075 rdev->family == CHIP_R423 ||
1076 rdev->family == CHIP_RV410)
1077 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1078 R420_TV_DAC_GDACPD |
1079 R420_TV_DAC_BDACPD |
1080 RADEON_TV_DAC_BGSLEEP);
1082 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1083 RADEON_TV_DAC_GDACPD |
1084 RADEON_TV_DAC_BDACPD |
1085 RADEON_TV_DAC_BGSLEEP);
1090 if (rdev->family == CHIP_R200) {
1091 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1094 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1096 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1097 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1100 if (rdev->is_atom_bios)
1101 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1103 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1107 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1109 struct radeon_device *rdev = encoder->dev->dev_private;
1111 if (rdev->is_atom_bios)
1112 radeon_atom_output_lock(encoder, true);
1114 radeon_combios_output_lock(encoder, true);
1115 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1118 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1120 struct radeon_device *rdev = encoder->dev->dev_private;
1122 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1124 if (rdev->is_atom_bios)
1125 radeon_atom_output_lock(encoder, true);
1127 radeon_combios_output_lock(encoder, true);
1130 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1131 struct drm_display_mode *mode,
1132 struct drm_display_mode *adjusted_mode)
1134 struct drm_device *dev = encoder->dev;
1135 struct radeon_device *rdev = dev->dev_private;
1136 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1137 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1138 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1139 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1140 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1143 DRM_DEBUG_KMS("\n");
1145 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1147 if (rdev->family != CHIP_R200) {
1148 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1149 if (rdev->family == CHIP_R420 ||
1150 rdev->family == CHIP_R423 ||
1151 rdev->family == CHIP_RV410) {
1152 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1153 RADEON_TV_DAC_BGADJ_MASK |
1154 R420_TV_DAC_DACADJ_MASK |
1155 R420_TV_DAC_RDACPD |
1156 R420_TV_DAC_GDACPD |
1157 R420_TV_DAC_BDACPD |
1158 R420_TV_DAC_TVENABLE);
1160 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1161 RADEON_TV_DAC_BGADJ_MASK |
1162 RADEON_TV_DAC_DACADJ_MASK |
1163 RADEON_TV_DAC_RDACPD |
1164 RADEON_TV_DAC_GDACPD |
1165 RADEON_TV_DAC_BDACPD);
1168 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1171 if (tv_dac->tv_std == TV_STD_NTSC ||
1172 tv_dac->tv_std == TV_STD_NTSC_J ||
1173 tv_dac->tv_std == TV_STD_PAL_M ||
1174 tv_dac->tv_std == TV_STD_PAL_60)
1175 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1177 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1179 if (tv_dac->tv_std == TV_STD_NTSC ||
1180 tv_dac->tv_std == TV_STD_NTSC_J)
1181 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1183 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1185 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1186 tv_dac->ps2_tvdac_adj);
1188 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1191 if (ASIC_IS_R300(rdev)) {
1192 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1193 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1194 } else if (rdev->family != CHIP_R200)
1195 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1196 else if (rdev->family == CHIP_R200)
1197 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1199 if (rdev->family >= CHIP_R200)
1200 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1205 dac_cntl = RREG32(RADEON_DAC_CNTL);
1206 dac_cntl &= ~RADEON_DAC_TVO_EN;
1207 WREG32(RADEON_DAC_CNTL, dac_cntl);
1209 if (ASIC_IS_R300(rdev))
1210 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1212 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1213 if (radeon_crtc->crtc_id == 0) {
1214 if (ASIC_IS_R300(rdev)) {
1215 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1216 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1217 RADEON_DISP_TV_SOURCE_CRTC);
1219 if (rdev->family >= CHIP_R200) {
1220 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1222 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1225 if (ASIC_IS_R300(rdev)) {
1226 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1227 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1229 if (rdev->family >= CHIP_R200) {
1230 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1232 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1235 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1238 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1240 if (radeon_crtc->crtc_id == 0) {
1241 if (ASIC_IS_R300(rdev)) {
1242 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1243 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1244 } else if (rdev->family == CHIP_R200) {
1245 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1246 RADEON_FP2_DVO_RATE_SEL_SDR);
1248 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1250 if (ASIC_IS_R300(rdev)) {
1251 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1252 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1253 } else if (rdev->family == CHIP_R200) {
1254 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1255 RADEON_FP2_DVO_RATE_SEL_SDR);
1256 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1258 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1260 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1263 if (ASIC_IS_R300(rdev)) {
1264 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1265 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1266 } else if (rdev->family != CHIP_R200)
1267 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1268 else if (rdev->family == CHIP_R200)
1269 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1271 if (rdev->family >= CHIP_R200)
1272 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1275 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1277 if (rdev->is_atom_bios)
1278 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1280 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1284 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1285 struct drm_connector *connector)
1287 struct drm_device *dev = encoder->dev;
1288 struct radeon_device *rdev = dev->dev_private;
1289 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1290 uint32_t disp_output_cntl, gpiopad_a, tmp;
1293 /* save regs needed */
1294 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1295 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1296 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1297 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1298 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1299 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1301 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1303 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1305 WREG32(RADEON_CRTC2_GEN_CNTL,
1306 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1308 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1309 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1310 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1312 WREG32(RADEON_DAC_EXT_CNTL,
1313 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1314 RADEON_DAC2_FORCE_DATA_EN |
1315 RADEON_DAC_FORCE_DATA_SEL_RGB |
1316 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1318 WREG32(RADEON_TV_DAC_CNTL,
1319 RADEON_TV_DAC_STD_NTSC |
1320 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1321 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1323 RREG32(RADEON_TV_DAC_CNTL);
1326 WREG32(RADEON_TV_DAC_CNTL,
1327 RADEON_TV_DAC_NBLANK |
1328 RADEON_TV_DAC_NHOLD |
1329 RADEON_TV_MONITOR_DETECT_EN |
1330 RADEON_TV_DAC_STD_NTSC |
1331 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1332 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1334 RREG32(RADEON_TV_DAC_CNTL);
1337 tmp = RREG32(RADEON_TV_DAC_CNTL);
1338 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1340 DRM_DEBUG_KMS("S-video TV connection detected\n");
1341 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1343 DRM_DEBUG_KMS("Composite TV connection detected\n");
1346 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1347 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1348 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1349 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1350 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1351 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1355 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1356 struct drm_connector *connector)
1358 struct drm_device *dev = encoder->dev;
1359 struct radeon_device *rdev = dev->dev_private;
1360 uint32_t tv_dac_cntl, dac_cntl2;
1361 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1364 if (ASIC_IS_R300(rdev))
1365 return r300_legacy_tv_detect(encoder, connector);
1367 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1368 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1369 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1370 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1371 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1373 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1374 WREG32(RADEON_DAC_CNTL2, tmp);
1376 tmp = tv_master_cntl | RADEON_TV_ON;
1377 tmp &= ~(RADEON_TV_ASYNC_RST |
1378 RADEON_RESTART_PHASE_FIX |
1379 RADEON_CRT_FIFO_CE_EN |
1380 RADEON_TV_FIFO_CE_EN |
1381 RADEON_RE_SYNC_NOW_SEL_MASK);
1382 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1383 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1385 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1386 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1387 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1389 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1390 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1392 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1393 WREG32(RADEON_TV_DAC_CNTL, tmp);
1395 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1396 RADEON_RED_MX_FORCE_DAC_DATA |
1397 RADEON_GRN_MX_FORCE_DAC_DATA |
1398 RADEON_BLU_MX_FORCE_DAC_DATA |
1399 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1400 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1403 tmp = RREG32(RADEON_TV_DAC_CNTL);
1404 if (tmp & RADEON_TV_DAC_GDACDET) {
1406 DRM_DEBUG_KMS("S-video TV connection detected\n");
1407 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1409 DRM_DEBUG_KMS("Composite TV connection detected\n");
1412 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1413 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1414 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1415 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1419 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1420 struct drm_connector *connector)
1422 struct drm_device *dev = encoder->dev;
1423 struct radeon_device *rdev = dev->dev_private;
1424 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1425 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1426 enum drm_connector_status found = connector_status_disconnected;
1427 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1428 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1430 struct drm_crtc *crtc;
1432 /* find out if crtc2 is in use or if this encoder is using it */
1433 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1435 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1436 if (encoder->crtc != crtc) {
1437 return connector_status_disconnected;
1442 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1443 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1444 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1447 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1448 return connector_status_disconnected;
1450 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1451 if (tv_detect && tv_dac)
1452 found = connector_status_connected;
1456 /* don't probe if the encoder is being used for something else not CRT related */
1457 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1458 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1459 return connector_status_disconnected;
1462 /* save the regs we need */
1463 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1464 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1465 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1466 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1467 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1468 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1469 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1470 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1472 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1473 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1474 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1476 if (ASIC_IS_R300(rdev))
1477 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1479 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1480 tmp |= RADEON_CRTC2_CRT2_ON |
1481 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1483 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1485 if (ASIC_IS_R300(rdev)) {
1486 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1487 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1488 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1490 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1491 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1494 tmp = RADEON_TV_DAC_NBLANK |
1495 RADEON_TV_DAC_NHOLD |
1496 RADEON_TV_MONITOR_DETECT_EN |
1497 RADEON_TV_DAC_STD_PS2;
1499 WREG32(RADEON_TV_DAC_CNTL, tmp);
1501 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1502 RADEON_DAC2_FORCE_DATA_EN;
1505 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1507 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1509 if (ASIC_IS_R300(rdev))
1510 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1512 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1514 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1516 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1517 WREG32(RADEON_DAC_CNTL2, tmp);
1521 if (ASIC_IS_R300(rdev)) {
1522 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1523 found = connector_status_connected;
1525 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1526 found = connector_status_connected;
1529 /* restore regs we used */
1530 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1531 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1532 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1533 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1535 if (ASIC_IS_R300(rdev)) {
1536 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1537 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1539 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1541 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1547 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1548 .dpms = radeon_legacy_tv_dac_dpms,
1549 .mode_fixup = radeon_legacy_mode_fixup,
1550 .prepare = radeon_legacy_tv_dac_prepare,
1551 .mode_set = radeon_legacy_tv_dac_mode_set,
1552 .commit = radeon_legacy_tv_dac_commit,
1553 .detect = radeon_legacy_tv_dac_detect,
1554 .disable = radeon_legacy_encoder_disable,
1558 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1559 .destroy = radeon_enc_destroy,
1563 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1565 struct drm_device *dev = encoder->base.dev;
1566 struct radeon_device *rdev = dev->dev_private;
1567 struct radeon_encoder_int_tmds *tmds = NULL;
1570 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1575 if (rdev->is_atom_bios)
1576 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1578 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1581 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1586 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1588 struct drm_device *dev = encoder->base.dev;
1589 struct radeon_device *rdev = dev->dev_private;
1590 struct radeon_encoder_ext_tmds *tmds = NULL;
1593 if (rdev->is_atom_bios)
1596 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1601 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1604 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1610 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1612 struct radeon_device *rdev = dev->dev_private;
1613 struct drm_encoder *encoder;
1614 struct radeon_encoder *radeon_encoder;
1616 /* see if we already added it */
1617 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1618 radeon_encoder = to_radeon_encoder(encoder);
1619 if (radeon_encoder->encoder_enum == encoder_enum) {
1620 radeon_encoder->devices |= supported_device;
1627 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1628 if (!radeon_encoder)
1631 encoder = &radeon_encoder->base;
1632 if (rdev->flags & RADEON_SINGLE_CRTC)
1633 encoder->possible_crtcs = 0x1;
1635 encoder->possible_crtcs = 0x3;
1637 radeon_encoder->enc_priv = NULL;
1639 radeon_encoder->encoder_enum = encoder_enum;
1640 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1641 radeon_encoder->devices = supported_device;
1642 radeon_encoder->rmx_type = RMX_OFF;
1644 switch (radeon_encoder->encoder_id) {
1645 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1646 encoder->possible_crtcs = 0x1;
1647 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1648 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1649 if (rdev->is_atom_bios)
1650 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1652 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1653 radeon_encoder->rmx_type = RMX_FULL;
1655 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1656 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1657 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1658 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1660 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1661 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1662 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1663 if (rdev->is_atom_bios)
1664 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1666 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1668 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1669 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1670 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1671 if (rdev->is_atom_bios)
1672 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1674 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1676 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1677 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1678 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1679 if (!rdev->is_atom_bios)
1680 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);