2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
34 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
35 struct drm_encoder_helper_funcs *encoder_funcs;
37 encoder_funcs = encoder->helper_private;
38 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
39 radeon_encoder->active_device = 0;
42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
44 struct drm_device *dev = encoder->dev;
45 struct radeon_device *rdev = dev->dev_private;
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000;
51 if (radeon_encoder->enc_priv) {
52 if (rdev->is_atom_bios) {
53 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
54 panel_pwr_delay = lvds->panel_pwr_delay;
56 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
57 panel_pwr_delay = lvds->panel_pwr_delay;
62 case DRM_MODE_DPMS_ON:
63 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
64 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
65 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
66 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
67 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
68 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
71 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
72 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
73 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
75 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
76 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
77 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
78 udelay(panel_pwr_delay * 1000);
79 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
81 case DRM_MODE_DPMS_STANDBY:
82 case DRM_MODE_DPMS_SUSPEND:
83 case DRM_MODE_DPMS_OFF:
84 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
85 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
86 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
87 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
88 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
89 udelay(panel_pwr_delay * 1000);
90 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
91 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
95 if (rdev->is_atom_bios)
96 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
98 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
101 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
103 struct radeon_device *rdev = encoder->dev->dev_private;
105 if (rdev->is_atom_bios)
106 radeon_atom_output_lock(encoder, true);
108 radeon_combios_output_lock(encoder, true);
109 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
112 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
114 struct radeon_device *rdev = encoder->dev->dev_private;
116 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
117 if (rdev->is_atom_bios)
118 radeon_atom_output_lock(encoder, false);
120 radeon_combios_output_lock(encoder, false);
123 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
124 struct drm_display_mode *mode,
125 struct drm_display_mode *adjusted_mode)
127 struct drm_device *dev = encoder->dev;
128 struct radeon_device *rdev = dev->dev_private;
129 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
130 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
131 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
135 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
136 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
138 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
139 if (rdev->is_atom_bios) {
140 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
141 * need to call that on resume to set up the reg properly.
143 radeon_encoder->pixel_clock = adjusted_mode->clock;
144 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
145 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
147 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
149 DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
150 lvds_gen_cntl = lvds->lvds_gen_cntl;
151 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
152 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
153 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
154 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
156 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
158 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
159 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
164 if (ASIC_IS_R300(rdev))
165 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
167 if (radeon_crtc->crtc_id == 0) {
168 if (ASIC_IS_R300(rdev)) {
169 if (radeon_encoder->rmx_type != RMX_OFF)
170 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
172 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
174 if (ASIC_IS_R300(rdev))
175 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
177 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
180 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
181 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
182 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
184 if (rdev->family == CHIP_RV410)
185 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
187 if (rdev->is_atom_bios)
188 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
190 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
193 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
194 struct drm_display_mode *mode,
195 struct drm_display_mode *adjusted_mode)
197 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
199 /* set the active encoder to connector routing */
200 radeon_encoder_set_active_device(encoder);
201 drm_mode_set_crtcinfo(adjusted_mode, 0);
203 /* get the native mode for LVDS */
204 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
205 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
206 int mode_id = adjusted_mode->base.id;
207 *adjusted_mode = *native_mode;
208 adjusted_mode->hdisplay = mode->hdisplay;
209 adjusted_mode->vdisplay = mode->vdisplay;
210 adjusted_mode->base.id = mode_id;
216 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
217 .dpms = radeon_legacy_lvds_dpms,
218 .mode_fixup = radeon_legacy_mode_fixup,
219 .prepare = radeon_legacy_lvds_prepare,
220 .mode_set = radeon_legacy_lvds_mode_set,
221 .commit = radeon_legacy_lvds_commit,
222 .disable = radeon_legacy_encoder_disable,
226 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
227 .destroy = radeon_enc_destroy,
230 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
232 struct drm_device *dev = encoder->dev;
233 struct radeon_device *rdev = dev->dev_private;
234 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
235 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
236 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
241 case DRM_MODE_DPMS_ON:
242 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
243 dac_cntl &= ~RADEON_DAC_PDWN;
244 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
248 case DRM_MODE_DPMS_STANDBY:
249 case DRM_MODE_DPMS_SUSPEND:
250 case DRM_MODE_DPMS_OFF:
251 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
252 dac_cntl |= RADEON_DAC_PDWN;
253 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
259 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
260 WREG32(RADEON_DAC_CNTL, dac_cntl);
261 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
263 if (rdev->is_atom_bios)
264 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
266 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
269 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
271 struct radeon_device *rdev = encoder->dev->dev_private;
273 if (rdev->is_atom_bios)
274 radeon_atom_output_lock(encoder, true);
276 radeon_combios_output_lock(encoder, true);
277 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
280 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
282 struct radeon_device *rdev = encoder->dev->dev_private;
284 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
286 if (rdev->is_atom_bios)
287 radeon_atom_output_lock(encoder, false);
289 radeon_combios_output_lock(encoder, false);
292 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
293 struct drm_display_mode *mode,
294 struct drm_display_mode *adjusted_mode)
296 struct drm_device *dev = encoder->dev;
297 struct radeon_device *rdev = dev->dev_private;
298 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
304 if (radeon_crtc->crtc_id == 0) {
305 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
306 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
307 ~(RADEON_DISP_DAC_SOURCE_MASK);
308 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
310 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
311 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
314 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
315 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
316 ~(RADEON_DISP_DAC_SOURCE_MASK);
317 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
318 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
320 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
321 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
325 dac_cntl = (RADEON_DAC_MASK_ALL |
326 RADEON_DAC_VGA_ADR_EN |
330 WREG32_P(RADEON_DAC_CNTL,
332 RADEON_DAC_RANGE_CNTL |
333 RADEON_DAC_BLANKING);
335 if (radeon_encoder->enc_priv) {
336 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
337 dac_macro_cntl = p_dac->ps2_pdac_adj;
339 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
340 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
341 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
343 if (rdev->is_atom_bios)
344 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
346 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
349 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
350 struct drm_connector *connector)
352 struct drm_device *dev = encoder->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
355 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
356 enum drm_connector_status found = connector_status_disconnected;
359 /* save the regs we need */
360 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
361 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
362 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
363 dac_cntl = RREG32(RADEON_DAC_CNTL);
364 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
366 tmp = vclk_ecp_cntl &
367 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
368 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
370 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
371 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
373 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
374 RADEON_DAC_FORCE_DATA_EN;
377 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
379 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
381 if (ASIC_IS_R300(rdev))
382 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
384 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
386 WREG32(RADEON_DAC_EXT_CNTL, tmp);
388 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
389 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
390 WREG32(RADEON_DAC_CNTL, tmp);
392 tmp &= ~(RADEON_DAC_PDWN_R |
396 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
400 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
401 found = connector_status_connected;
403 /* restore the regs we used */
404 WREG32(RADEON_DAC_CNTL, dac_cntl);
405 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
406 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
407 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
408 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
413 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
414 .dpms = radeon_legacy_primary_dac_dpms,
415 .mode_fixup = radeon_legacy_mode_fixup,
416 .prepare = radeon_legacy_primary_dac_prepare,
417 .mode_set = radeon_legacy_primary_dac_mode_set,
418 .commit = radeon_legacy_primary_dac_commit,
419 .detect = radeon_legacy_primary_dac_detect,
420 .disable = radeon_legacy_encoder_disable,
424 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
425 .destroy = radeon_enc_destroy,
428 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
430 struct drm_device *dev = encoder->dev;
431 struct radeon_device *rdev = dev->dev_private;
432 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
436 case DRM_MODE_DPMS_ON:
437 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
439 case DRM_MODE_DPMS_STANDBY:
440 case DRM_MODE_DPMS_SUSPEND:
441 case DRM_MODE_DPMS_OFF:
442 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
446 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
448 if (rdev->is_atom_bios)
449 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
451 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
454 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
456 struct radeon_device *rdev = encoder->dev->dev_private;
458 if (rdev->is_atom_bios)
459 radeon_atom_output_lock(encoder, true);
461 radeon_combios_output_lock(encoder, true);
462 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
465 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
467 struct radeon_device *rdev = encoder->dev->dev_private;
469 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
471 if (rdev->is_atom_bios)
472 radeon_atom_output_lock(encoder, true);
474 radeon_combios_output_lock(encoder, true);
477 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
478 struct drm_display_mode *mode,
479 struct drm_display_mode *adjusted_mode)
481 struct drm_device *dev = encoder->dev;
482 struct radeon_device *rdev = dev->dev_private;
483 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
485 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
490 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
492 if (rdev->family == CHIP_RV280) {
493 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
495 tmds_pll_cntl ^= (1 << 22);
498 if (radeon_encoder->enc_priv) {
499 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
501 for (i = 0; i < 4; i++) {
502 if (tmds->tmds_pll[i].freq == 0)
504 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
505 tmp = tmds->tmds_pll[i].value ;
511 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
512 if (tmp & 0xfff00000)
515 tmds_pll_cntl &= 0xfff00000;
516 tmds_pll_cntl |= tmp;
521 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
522 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
524 if (rdev->family == CHIP_R200 ||
525 rdev->family == CHIP_R100 ||
527 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
528 else /* RV chips got this bit reversed */
529 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
531 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
532 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
533 RADEON_FP_CRTC_DONT_SHADOW_HEND));
535 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
537 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
538 RADEON_FP_DFP_SYNC_SEL |
539 RADEON_FP_CRT_SYNC_SEL |
540 RADEON_FP_CRTC_LOCK_8DOT |
541 RADEON_FP_USE_SHADOW_EN |
542 RADEON_FP_CRTC_USE_SHADOW_VEND |
543 RADEON_FP_CRT_SYNC_ALT);
545 if (1) /* FIXME rgbBits == 8 */
546 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
548 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
550 if (radeon_crtc->crtc_id == 0) {
551 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
552 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
553 if (radeon_encoder->rmx_type != RMX_OFF)
554 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
556 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
558 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
560 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
561 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
562 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
564 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
567 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
568 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
569 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
571 if (rdev->is_atom_bios)
572 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
574 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
577 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
578 .dpms = radeon_legacy_tmds_int_dpms,
579 .mode_fixup = radeon_legacy_mode_fixup,
580 .prepare = radeon_legacy_tmds_int_prepare,
581 .mode_set = radeon_legacy_tmds_int_mode_set,
582 .commit = radeon_legacy_tmds_int_commit,
583 .disable = radeon_legacy_encoder_disable,
587 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
588 .destroy = radeon_enc_destroy,
591 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
593 struct drm_device *dev = encoder->dev;
594 struct radeon_device *rdev = dev->dev_private;
595 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
599 case DRM_MODE_DPMS_ON:
600 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
601 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
603 case DRM_MODE_DPMS_STANDBY:
604 case DRM_MODE_DPMS_SUSPEND:
605 case DRM_MODE_DPMS_OFF:
606 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
607 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
611 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
613 if (rdev->is_atom_bios)
614 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
616 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
619 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
621 struct radeon_device *rdev = encoder->dev->dev_private;
623 if (rdev->is_atom_bios)
624 radeon_atom_output_lock(encoder, true);
626 radeon_combios_output_lock(encoder, true);
627 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
630 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
632 struct radeon_device *rdev = encoder->dev->dev_private;
633 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
635 if (rdev->is_atom_bios)
636 radeon_atom_output_lock(encoder, false);
638 radeon_combios_output_lock(encoder, false);
641 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
642 struct drm_display_mode *mode,
643 struct drm_display_mode *adjusted_mode)
645 struct drm_device *dev = encoder->dev;
646 struct radeon_device *rdev = dev->dev_private;
647 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
648 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
649 uint32_t fp2_gen_cntl;
653 if (rdev->is_atom_bios) {
654 radeon_encoder->pixel_clock = adjusted_mode->clock;
655 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
656 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
658 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
660 if (1) /* FIXME rgbBits == 8 */
661 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
663 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
665 fp2_gen_cntl &= ~(RADEON_FP2_ON |
667 RADEON_FP2_DVO_RATE_SEL_SDR);
669 /* XXX: these are oem specific */
670 if (ASIC_IS_R300(rdev)) {
671 if ((dev->pdev->device == 0x4850) &&
672 (dev->pdev->subsystem_vendor == 0x1028) &&
673 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
674 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
676 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
678 /*if (mode->clock > 165000)
679 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
681 if (!radeon_combios_external_tmds_setup(encoder))
682 radeon_external_tmds_setup(encoder);
685 if (radeon_crtc->crtc_id == 0) {
686 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
687 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
688 if (radeon_encoder->rmx_type != RMX_OFF)
689 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
691 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
693 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
695 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
696 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
697 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
699 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
702 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
704 if (rdev->is_atom_bios)
705 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
707 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
710 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
712 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
713 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
716 radeon_i2c_destroy(tmds->i2c_bus);
718 kfree(radeon_encoder->enc_priv);
719 drm_encoder_cleanup(encoder);
720 kfree(radeon_encoder);
723 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
724 .dpms = radeon_legacy_tmds_ext_dpms,
725 .mode_fixup = radeon_legacy_mode_fixup,
726 .prepare = radeon_legacy_tmds_ext_prepare,
727 .mode_set = radeon_legacy_tmds_ext_mode_set,
728 .commit = radeon_legacy_tmds_ext_commit,
729 .disable = radeon_legacy_encoder_disable,
733 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
734 .destroy = radeon_ext_tmds_enc_destroy,
737 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
739 struct drm_device *dev = encoder->dev;
740 struct radeon_device *rdev = dev->dev_private;
741 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
742 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
743 uint32_t tv_master_cntl = 0;
747 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
749 if (rdev->family == CHIP_R200)
750 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
753 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
755 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
756 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
760 case DRM_MODE_DPMS_ON:
761 if (rdev->family == CHIP_R200) {
762 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
765 tv_master_cntl |= RADEON_TV_ON;
767 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
769 if (rdev->family == CHIP_R420 ||
770 rdev->family == CHIP_R423 ||
771 rdev->family == CHIP_RV410)
772 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
775 RADEON_TV_DAC_BGSLEEP);
777 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
778 RADEON_TV_DAC_GDACPD |
779 RADEON_TV_DAC_BDACPD |
780 RADEON_TV_DAC_BGSLEEP);
783 case DRM_MODE_DPMS_STANDBY:
784 case DRM_MODE_DPMS_SUSPEND:
785 case DRM_MODE_DPMS_OFF:
786 if (rdev->family == CHIP_R200)
787 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
790 tv_master_cntl &= ~RADEON_TV_ON;
792 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
794 if (rdev->family == CHIP_R420 ||
795 rdev->family == CHIP_R423 ||
796 rdev->family == CHIP_RV410)
797 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
800 RADEON_TV_DAC_BGSLEEP);
802 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
803 RADEON_TV_DAC_GDACPD |
804 RADEON_TV_DAC_BDACPD |
805 RADEON_TV_DAC_BGSLEEP);
810 if (rdev->family == CHIP_R200) {
811 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
814 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
816 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
817 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
820 if (rdev->is_atom_bios)
821 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
823 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
826 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
828 struct radeon_device *rdev = encoder->dev->dev_private;
830 if (rdev->is_atom_bios)
831 radeon_atom_output_lock(encoder, true);
833 radeon_combios_output_lock(encoder, true);
834 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
837 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
839 struct radeon_device *rdev = encoder->dev->dev_private;
841 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
843 if (rdev->is_atom_bios)
844 radeon_atom_output_lock(encoder, true);
846 radeon_combios_output_lock(encoder, true);
849 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
850 struct drm_display_mode *mode,
851 struct drm_display_mode *adjusted_mode)
853 struct drm_device *dev = encoder->dev;
854 struct radeon_device *rdev = dev->dev_private;
855 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
856 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
857 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
858 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
859 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
864 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
866 if (rdev->family != CHIP_R200) {
867 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
868 if (rdev->family == CHIP_R420 ||
869 rdev->family == CHIP_R423 ||
870 rdev->family == CHIP_RV410) {
871 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
872 RADEON_TV_DAC_BGADJ_MASK |
873 R420_TV_DAC_DACADJ_MASK |
877 R420_TV_DAC_TVENABLE);
879 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
880 RADEON_TV_DAC_BGADJ_MASK |
881 RADEON_TV_DAC_DACADJ_MASK |
882 RADEON_TV_DAC_RDACPD |
883 RADEON_TV_DAC_GDACPD |
884 RADEON_TV_DAC_BDACPD);
889 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
890 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
891 RADEON_TV_DAC_NHOLD |
892 RADEON_TV_DAC_STD_PS2 |
893 tv_dac->ps2_tvdac_adj);
895 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
896 RADEON_TV_DAC_NHOLD |
897 RADEON_TV_DAC_STD_PS2);
899 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
902 if (ASIC_IS_R300(rdev)) {
903 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
904 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
907 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
908 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
910 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
912 if (rdev->family == CHIP_R200)
913 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
918 dac_cntl = RREG32(RADEON_DAC_CNTL);
919 dac_cntl &= ~RADEON_DAC_TVO_EN;
920 WREG32(RADEON_DAC_CNTL, dac_cntl);
922 if (ASIC_IS_R300(rdev))
923 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
925 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
926 if (radeon_crtc->crtc_id == 0) {
927 if (ASIC_IS_R300(rdev)) {
928 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
929 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
930 RADEON_DISP_TV_SOURCE_CRTC);
932 if (rdev->family >= CHIP_R200) {
933 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
935 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
938 if (ASIC_IS_R300(rdev)) {
939 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
940 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
942 if (rdev->family >= CHIP_R200) {
943 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
945 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
948 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
951 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
953 if (radeon_crtc->crtc_id == 0) {
954 if (ASIC_IS_R300(rdev)) {
955 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
956 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
957 } else if (rdev->family == CHIP_R200) {
958 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
959 RADEON_FP2_DVO_RATE_SEL_SDR);
961 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
963 if (ASIC_IS_R300(rdev)) {
964 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
965 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
966 } else if (rdev->family == CHIP_R200) {
967 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
968 RADEON_FP2_DVO_RATE_SEL_SDR);
969 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
971 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
973 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
976 if (ASIC_IS_R300(rdev)) {
977 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
978 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
981 if (rdev->family >= CHIP_R200)
982 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
984 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
986 if (rdev->family == CHIP_R200)
987 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
990 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
992 if (rdev->is_atom_bios)
993 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
995 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
999 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1000 struct drm_connector *connector)
1002 struct drm_device *dev = encoder->dev;
1003 struct radeon_device *rdev = dev->dev_private;
1004 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1005 uint32_t disp_output_cntl, gpiopad_a, tmp;
1008 /* save regs needed */
1009 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1010 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1011 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1012 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1013 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1014 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1016 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1018 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1020 WREG32(RADEON_CRTC2_GEN_CNTL,
1021 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1023 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1024 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1025 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1027 WREG32(RADEON_DAC_EXT_CNTL,
1028 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1029 RADEON_DAC2_FORCE_DATA_EN |
1030 RADEON_DAC_FORCE_DATA_SEL_RGB |
1031 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1033 WREG32(RADEON_TV_DAC_CNTL,
1034 RADEON_TV_DAC_STD_NTSC |
1035 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1036 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1038 RREG32(RADEON_TV_DAC_CNTL);
1041 WREG32(RADEON_TV_DAC_CNTL,
1042 RADEON_TV_DAC_NBLANK |
1043 RADEON_TV_DAC_NHOLD |
1044 RADEON_TV_MONITOR_DETECT_EN |
1045 RADEON_TV_DAC_STD_NTSC |
1046 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1047 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1049 RREG32(RADEON_TV_DAC_CNTL);
1052 tmp = RREG32(RADEON_TV_DAC_CNTL);
1053 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1055 DRM_DEBUG("S-video TV connection detected\n");
1056 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1058 DRM_DEBUG("Composite TV connection detected\n");
1061 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1062 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1063 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1064 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1065 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1066 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1070 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1071 struct drm_connector *connector)
1073 struct drm_device *dev = encoder->dev;
1074 struct radeon_device *rdev = dev->dev_private;
1075 uint32_t tv_dac_cntl, dac_cntl2;
1076 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1079 if (ASIC_IS_R300(rdev))
1080 return r300_legacy_tv_detect(encoder, connector);
1082 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1083 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1084 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1085 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1086 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1088 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1089 WREG32(RADEON_DAC_CNTL2, tmp);
1091 tmp = tv_master_cntl | RADEON_TV_ON;
1092 tmp &= ~(RADEON_TV_ASYNC_RST |
1093 RADEON_RESTART_PHASE_FIX |
1094 RADEON_CRT_FIFO_CE_EN |
1095 RADEON_TV_FIFO_CE_EN |
1096 RADEON_RE_SYNC_NOW_SEL_MASK);
1097 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1098 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1100 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1101 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1102 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1104 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1105 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1107 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1108 WREG32(RADEON_TV_DAC_CNTL, tmp);
1110 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1111 RADEON_RED_MX_FORCE_DAC_DATA |
1112 RADEON_GRN_MX_FORCE_DAC_DATA |
1113 RADEON_BLU_MX_FORCE_DAC_DATA |
1114 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1115 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1118 tmp = RREG32(RADEON_TV_DAC_CNTL);
1119 if (tmp & RADEON_TV_DAC_GDACDET) {
1121 DRM_DEBUG("S-video TV connection detected\n");
1122 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1124 DRM_DEBUG("Composite TV connection detected\n");
1127 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1128 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1129 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1130 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1134 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1135 struct drm_connector *connector)
1137 struct drm_device *dev = encoder->dev;
1138 struct radeon_device *rdev = dev->dev_private;
1139 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1140 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1141 enum drm_connector_status found = connector_status_disconnected;
1142 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1143 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1146 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1147 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1148 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1151 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1152 return connector_status_disconnected;
1154 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1155 if (tv_detect && tv_dac)
1156 found = connector_status_connected;
1160 /* don't probe if the encoder is being used for something else not CRT related */
1161 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1162 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1163 return connector_status_disconnected;
1166 /* save the regs we need */
1167 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1168 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1169 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1170 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1171 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1172 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1173 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1174 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1176 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1177 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1178 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1180 if (ASIC_IS_R300(rdev))
1181 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1183 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1184 tmp |= RADEON_CRTC2_CRT2_ON |
1185 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1187 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1189 if (ASIC_IS_R300(rdev)) {
1190 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1191 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1192 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1194 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1195 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1198 tmp = RADEON_TV_DAC_NBLANK |
1199 RADEON_TV_DAC_NHOLD |
1200 RADEON_TV_MONITOR_DETECT_EN |
1201 RADEON_TV_DAC_STD_PS2;
1203 WREG32(RADEON_TV_DAC_CNTL, tmp);
1205 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1206 RADEON_DAC2_FORCE_DATA_EN;
1209 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1211 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1213 if (ASIC_IS_R300(rdev))
1214 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1216 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1218 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1220 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1221 WREG32(RADEON_DAC_CNTL2, tmp);
1225 if (ASIC_IS_R300(rdev)) {
1226 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1227 found = connector_status_connected;
1229 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1230 found = connector_status_connected;
1233 /* restore regs we used */
1234 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1235 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1236 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1237 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1239 if (ASIC_IS_R300(rdev)) {
1240 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1241 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1243 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1245 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1251 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1252 .dpms = radeon_legacy_tv_dac_dpms,
1253 .mode_fixup = radeon_legacy_mode_fixup,
1254 .prepare = radeon_legacy_tv_dac_prepare,
1255 .mode_set = radeon_legacy_tv_dac_mode_set,
1256 .commit = radeon_legacy_tv_dac_commit,
1257 .detect = radeon_legacy_tv_dac_detect,
1258 .disable = radeon_legacy_encoder_disable,
1262 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1263 .destroy = radeon_enc_destroy,
1267 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1269 struct drm_device *dev = encoder->base.dev;
1270 struct radeon_device *rdev = dev->dev_private;
1271 struct radeon_encoder_int_tmds *tmds = NULL;
1274 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1279 if (rdev->is_atom_bios)
1280 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1282 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1285 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1290 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1292 struct drm_device *dev = encoder->base.dev;
1293 struct radeon_device *rdev = dev->dev_private;
1294 struct radeon_encoder_ext_tmds *tmds = NULL;
1297 if (rdev->is_atom_bios)
1300 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1305 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1308 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1314 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1316 struct radeon_device *rdev = dev->dev_private;
1317 struct drm_encoder *encoder;
1318 struct radeon_encoder *radeon_encoder;
1320 /* see if we already added it */
1321 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1322 radeon_encoder = to_radeon_encoder(encoder);
1323 if (radeon_encoder->encoder_id == encoder_id) {
1324 radeon_encoder->devices |= supported_device;
1331 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1332 if (!radeon_encoder)
1335 encoder = &radeon_encoder->base;
1336 if (rdev->flags & RADEON_SINGLE_CRTC)
1337 encoder->possible_crtcs = 0x1;
1339 encoder->possible_crtcs = 0x3;
1341 radeon_encoder->enc_priv = NULL;
1343 radeon_encoder->encoder_id = encoder_id;
1344 radeon_encoder->devices = supported_device;
1345 radeon_encoder->rmx_type = RMX_OFF;
1347 switch (radeon_encoder->encoder_id) {
1348 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1349 encoder->possible_crtcs = 0x1;
1350 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1351 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1352 if (rdev->is_atom_bios)
1353 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1355 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1356 radeon_encoder->rmx_type = RMX_FULL;
1358 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1359 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1360 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1361 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1363 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1364 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1365 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1366 if (rdev->is_atom_bios)
1367 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1369 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1371 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1372 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1373 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1374 if (rdev->is_atom_bios)
1375 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1377 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1379 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1380 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1381 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1382 if (!rdev->is_atom_bios)
1383 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);