2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
34 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
35 struct drm_encoder_helper_funcs *encoder_funcs;
37 encoder_funcs = encoder->helper_private;
38 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
39 radeon_encoder->active_device = 0;
42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
44 struct drm_device *dev = encoder->dev;
45 struct radeon_device *rdev = dev->dev_private;
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000;
52 if (radeon_encoder->enc_priv) {
53 if (rdev->is_atom_bios) {
54 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
55 panel_pwr_delay = lvds->panel_pwr_delay;
57 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
58 panel_pwr_delay = lvds->panel_pwr_delay;
62 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
63 * Taken from radeonfb.
65 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
66 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
67 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
68 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
72 case DRM_MODE_DPMS_ON:
73 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
74 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
75 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
76 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
77 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
78 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
81 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
82 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
83 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
85 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
86 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
88 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
89 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
90 udelay(panel_pwr_delay * 1000);
91 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
93 case DRM_MODE_DPMS_STANDBY:
94 case DRM_MODE_DPMS_SUSPEND:
95 case DRM_MODE_DPMS_OFF:
96 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
98 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
99 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
101 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
102 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
103 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
108 udelay(panel_pwr_delay * 1000);
109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
114 if (rdev->is_atom_bios)
115 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
117 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
121 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
123 struct radeon_device *rdev = encoder->dev->dev_private;
125 if (rdev->is_atom_bios)
126 radeon_atom_output_lock(encoder, true);
128 radeon_combios_output_lock(encoder, true);
129 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
132 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
134 struct radeon_device *rdev = encoder->dev->dev_private;
136 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
137 if (rdev->is_atom_bios)
138 radeon_atom_output_lock(encoder, false);
140 radeon_combios_output_lock(encoder, false);
143 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
144 struct drm_display_mode *mode,
145 struct drm_display_mode *adjusted_mode)
147 struct drm_device *dev = encoder->dev;
148 struct radeon_device *rdev = dev->dev_private;
149 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
150 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
151 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
155 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
156 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
158 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
159 if (rdev->is_atom_bios) {
160 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
161 * need to call that on resume to set up the reg properly.
163 radeon_encoder->pixel_clock = adjusted_mode->clock;
164 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
165 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
167 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
169 DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
170 lvds_gen_cntl = lvds->lvds_gen_cntl;
171 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
172 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
173 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
174 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
176 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
178 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
179 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
184 if (ASIC_IS_R300(rdev))
185 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
187 if (radeon_crtc->crtc_id == 0) {
188 if (ASIC_IS_R300(rdev)) {
189 if (radeon_encoder->rmx_type != RMX_OFF)
190 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
192 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
194 if (ASIC_IS_R300(rdev))
195 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
197 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
200 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
201 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
202 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
204 if (rdev->family == CHIP_RV410)
205 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
207 if (rdev->is_atom_bios)
208 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
210 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
213 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
214 struct drm_display_mode *mode,
215 struct drm_display_mode *adjusted_mode)
217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
219 /* set the active encoder to connector routing */
220 radeon_encoder_set_active_device(encoder);
221 drm_mode_set_crtcinfo(adjusted_mode, 0);
223 /* get the native mode for LVDS */
224 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
225 radeon_panel_mode_fixup(encoder, adjusted_mode);
230 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
231 .dpms = radeon_legacy_lvds_dpms,
232 .mode_fixup = radeon_legacy_mode_fixup,
233 .prepare = radeon_legacy_lvds_prepare,
234 .mode_set = radeon_legacy_lvds_mode_set,
235 .commit = radeon_legacy_lvds_commit,
236 .disable = radeon_legacy_encoder_disable,
240 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
241 .destroy = radeon_enc_destroy,
244 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
246 struct drm_device *dev = encoder->dev;
247 struct radeon_device *rdev = dev->dev_private;
248 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
249 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
250 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
255 case DRM_MODE_DPMS_ON:
256 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
257 dac_cntl &= ~RADEON_DAC_PDWN;
258 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
262 case DRM_MODE_DPMS_STANDBY:
263 case DRM_MODE_DPMS_SUSPEND:
264 case DRM_MODE_DPMS_OFF:
265 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
266 dac_cntl |= RADEON_DAC_PDWN;
267 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
273 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
274 WREG32(RADEON_DAC_CNTL, dac_cntl);
275 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
277 if (rdev->is_atom_bios)
278 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
280 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
284 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
286 struct radeon_device *rdev = encoder->dev->dev_private;
288 if (rdev->is_atom_bios)
289 radeon_atom_output_lock(encoder, true);
291 radeon_combios_output_lock(encoder, true);
292 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
295 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
297 struct radeon_device *rdev = encoder->dev->dev_private;
299 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
301 if (rdev->is_atom_bios)
302 radeon_atom_output_lock(encoder, false);
304 radeon_combios_output_lock(encoder, false);
307 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
308 struct drm_display_mode *mode,
309 struct drm_display_mode *adjusted_mode)
311 struct drm_device *dev = encoder->dev;
312 struct radeon_device *rdev = dev->dev_private;
313 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
314 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
315 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
319 if (radeon_crtc->crtc_id == 0) {
320 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
321 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
322 ~(RADEON_DISP_DAC_SOURCE_MASK);
323 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
325 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
326 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
329 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
330 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
331 ~(RADEON_DISP_DAC_SOURCE_MASK);
332 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
333 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
335 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
336 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
340 dac_cntl = (RADEON_DAC_MASK_ALL |
341 RADEON_DAC_VGA_ADR_EN |
345 WREG32_P(RADEON_DAC_CNTL,
347 RADEON_DAC_RANGE_CNTL |
348 RADEON_DAC_BLANKING);
350 if (radeon_encoder->enc_priv) {
351 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
352 dac_macro_cntl = p_dac->ps2_pdac_adj;
354 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
355 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
356 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
358 if (rdev->is_atom_bios)
359 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
361 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
364 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
365 struct drm_connector *connector)
367 struct drm_device *dev = encoder->dev;
368 struct radeon_device *rdev = dev->dev_private;
369 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
370 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
371 enum drm_connector_status found = connector_status_disconnected;
374 /* save the regs we need */
375 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
376 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
377 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
378 dac_cntl = RREG32(RADEON_DAC_CNTL);
379 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
381 tmp = vclk_ecp_cntl &
382 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
383 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
385 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
386 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
388 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
389 RADEON_DAC_FORCE_DATA_EN;
392 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
394 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
396 if (ASIC_IS_R300(rdev))
397 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
399 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
401 WREG32(RADEON_DAC_EXT_CNTL, tmp);
403 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
404 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
405 WREG32(RADEON_DAC_CNTL, tmp);
407 tmp &= ~(RADEON_DAC_PDWN_R |
411 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
415 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
416 found = connector_status_connected;
418 /* restore the regs we used */
419 WREG32(RADEON_DAC_CNTL, dac_cntl);
420 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
421 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
422 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
423 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
428 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
429 .dpms = radeon_legacy_primary_dac_dpms,
430 .mode_fixup = radeon_legacy_mode_fixup,
431 .prepare = radeon_legacy_primary_dac_prepare,
432 .mode_set = radeon_legacy_primary_dac_mode_set,
433 .commit = radeon_legacy_primary_dac_commit,
434 .detect = radeon_legacy_primary_dac_detect,
435 .disable = radeon_legacy_encoder_disable,
439 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
440 .destroy = radeon_enc_destroy,
443 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
445 struct drm_device *dev = encoder->dev;
446 struct radeon_device *rdev = dev->dev_private;
447 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
451 case DRM_MODE_DPMS_ON:
452 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
454 case DRM_MODE_DPMS_STANDBY:
455 case DRM_MODE_DPMS_SUSPEND:
456 case DRM_MODE_DPMS_OFF:
457 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
461 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
463 if (rdev->is_atom_bios)
464 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
466 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
470 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
472 struct radeon_device *rdev = encoder->dev->dev_private;
474 if (rdev->is_atom_bios)
475 radeon_atom_output_lock(encoder, true);
477 radeon_combios_output_lock(encoder, true);
478 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
481 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
483 struct radeon_device *rdev = encoder->dev->dev_private;
485 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
487 if (rdev->is_atom_bios)
488 radeon_atom_output_lock(encoder, true);
490 radeon_combios_output_lock(encoder, true);
493 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
494 struct drm_display_mode *mode,
495 struct drm_display_mode *adjusted_mode)
497 struct drm_device *dev = encoder->dev;
498 struct radeon_device *rdev = dev->dev_private;
499 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
501 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
506 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
508 if (rdev->family == CHIP_RV280) {
509 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
511 tmds_pll_cntl ^= (1 << 22);
514 if (radeon_encoder->enc_priv) {
515 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
517 for (i = 0; i < 4; i++) {
518 if (tmds->tmds_pll[i].freq == 0)
520 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
521 tmp = tmds->tmds_pll[i].value ;
527 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
528 if (tmp & 0xfff00000)
531 tmds_pll_cntl &= 0xfff00000;
532 tmds_pll_cntl |= tmp;
537 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
538 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
540 if (rdev->family == CHIP_R200 ||
541 rdev->family == CHIP_R100 ||
543 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
544 else /* RV chips got this bit reversed */
545 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
547 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
548 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
549 RADEON_FP_CRTC_DONT_SHADOW_HEND));
551 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
553 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
554 RADEON_FP_DFP_SYNC_SEL |
555 RADEON_FP_CRT_SYNC_SEL |
556 RADEON_FP_CRTC_LOCK_8DOT |
557 RADEON_FP_USE_SHADOW_EN |
558 RADEON_FP_CRTC_USE_SHADOW_VEND |
559 RADEON_FP_CRT_SYNC_ALT);
561 if (1) /* FIXME rgbBits == 8 */
562 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
564 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
566 if (radeon_crtc->crtc_id == 0) {
567 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
568 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
569 if (radeon_encoder->rmx_type != RMX_OFF)
570 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
572 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
574 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
576 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
577 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
578 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
580 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
583 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
584 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
585 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
587 if (rdev->is_atom_bios)
588 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
590 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
593 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
594 .dpms = radeon_legacy_tmds_int_dpms,
595 .mode_fixup = radeon_legacy_mode_fixup,
596 .prepare = radeon_legacy_tmds_int_prepare,
597 .mode_set = radeon_legacy_tmds_int_mode_set,
598 .commit = radeon_legacy_tmds_int_commit,
599 .disable = radeon_legacy_encoder_disable,
603 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
604 .destroy = radeon_enc_destroy,
607 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
609 struct drm_device *dev = encoder->dev;
610 struct radeon_device *rdev = dev->dev_private;
611 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
615 case DRM_MODE_DPMS_ON:
616 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
617 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
619 case DRM_MODE_DPMS_STANDBY:
620 case DRM_MODE_DPMS_SUSPEND:
621 case DRM_MODE_DPMS_OFF:
622 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
623 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
627 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
629 if (rdev->is_atom_bios)
630 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
632 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
636 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
638 struct radeon_device *rdev = encoder->dev->dev_private;
640 if (rdev->is_atom_bios)
641 radeon_atom_output_lock(encoder, true);
643 radeon_combios_output_lock(encoder, true);
644 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
647 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
649 struct radeon_device *rdev = encoder->dev->dev_private;
650 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
652 if (rdev->is_atom_bios)
653 radeon_atom_output_lock(encoder, false);
655 radeon_combios_output_lock(encoder, false);
658 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
659 struct drm_display_mode *mode,
660 struct drm_display_mode *adjusted_mode)
662 struct drm_device *dev = encoder->dev;
663 struct radeon_device *rdev = dev->dev_private;
664 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
665 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
666 uint32_t fp2_gen_cntl;
670 if (rdev->is_atom_bios) {
671 radeon_encoder->pixel_clock = adjusted_mode->clock;
672 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
673 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
675 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
677 if (1) /* FIXME rgbBits == 8 */
678 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
680 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
682 fp2_gen_cntl &= ~(RADEON_FP2_ON |
684 RADEON_FP2_DVO_RATE_SEL_SDR);
686 /* XXX: these are oem specific */
687 if (ASIC_IS_R300(rdev)) {
688 if ((dev->pdev->device == 0x4850) &&
689 (dev->pdev->subsystem_vendor == 0x1028) &&
690 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
691 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
693 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
695 /*if (mode->clock > 165000)
696 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
698 if (!radeon_combios_external_tmds_setup(encoder))
699 radeon_external_tmds_setup(encoder);
702 if (radeon_crtc->crtc_id == 0) {
703 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
704 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
705 if (radeon_encoder->rmx_type != RMX_OFF)
706 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
708 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
710 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
712 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
713 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
714 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
716 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
719 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
721 if (rdev->is_atom_bios)
722 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
724 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
727 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
729 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
730 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
733 radeon_i2c_destroy(tmds->i2c_bus);
735 kfree(radeon_encoder->enc_priv);
736 drm_encoder_cleanup(encoder);
737 kfree(radeon_encoder);
740 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
741 .dpms = radeon_legacy_tmds_ext_dpms,
742 .mode_fixup = radeon_legacy_mode_fixup,
743 .prepare = radeon_legacy_tmds_ext_prepare,
744 .mode_set = radeon_legacy_tmds_ext_mode_set,
745 .commit = radeon_legacy_tmds_ext_commit,
746 .disable = radeon_legacy_encoder_disable,
750 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
751 .destroy = radeon_ext_tmds_enc_destroy,
754 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
756 struct drm_device *dev = encoder->dev;
757 struct radeon_device *rdev = dev->dev_private;
758 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
759 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
760 uint32_t tv_master_cntl = 0;
764 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
766 if (rdev->family == CHIP_R200)
767 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
770 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
772 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
773 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
777 case DRM_MODE_DPMS_ON:
778 if (rdev->family == CHIP_R200) {
779 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
782 tv_master_cntl |= RADEON_TV_ON;
784 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
786 if (rdev->family == CHIP_R420 ||
787 rdev->family == CHIP_R423 ||
788 rdev->family == CHIP_RV410)
789 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
792 RADEON_TV_DAC_BGSLEEP);
794 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
795 RADEON_TV_DAC_GDACPD |
796 RADEON_TV_DAC_BDACPD |
797 RADEON_TV_DAC_BGSLEEP);
800 case DRM_MODE_DPMS_STANDBY:
801 case DRM_MODE_DPMS_SUSPEND:
802 case DRM_MODE_DPMS_OFF:
803 if (rdev->family == CHIP_R200)
804 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
807 tv_master_cntl &= ~RADEON_TV_ON;
809 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
811 if (rdev->family == CHIP_R420 ||
812 rdev->family == CHIP_R423 ||
813 rdev->family == CHIP_RV410)
814 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
817 RADEON_TV_DAC_BGSLEEP);
819 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
820 RADEON_TV_DAC_GDACPD |
821 RADEON_TV_DAC_BDACPD |
822 RADEON_TV_DAC_BGSLEEP);
827 if (rdev->family == CHIP_R200) {
828 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
831 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
833 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
834 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
837 if (rdev->is_atom_bios)
838 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
840 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
844 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
846 struct radeon_device *rdev = encoder->dev->dev_private;
848 if (rdev->is_atom_bios)
849 radeon_atom_output_lock(encoder, true);
851 radeon_combios_output_lock(encoder, true);
852 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
855 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
857 struct radeon_device *rdev = encoder->dev->dev_private;
859 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
861 if (rdev->is_atom_bios)
862 radeon_atom_output_lock(encoder, true);
864 radeon_combios_output_lock(encoder, true);
867 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
868 struct drm_display_mode *mode,
869 struct drm_display_mode *adjusted_mode)
871 struct drm_device *dev = encoder->dev;
872 struct radeon_device *rdev = dev->dev_private;
873 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
874 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
875 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
876 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
877 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
882 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
884 if (rdev->family != CHIP_R200) {
885 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
886 if (rdev->family == CHIP_R420 ||
887 rdev->family == CHIP_R423 ||
888 rdev->family == CHIP_RV410) {
889 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
890 RADEON_TV_DAC_BGADJ_MASK |
891 R420_TV_DAC_DACADJ_MASK |
895 R420_TV_DAC_TVENABLE);
897 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
898 RADEON_TV_DAC_BGADJ_MASK |
899 RADEON_TV_DAC_DACADJ_MASK |
900 RADEON_TV_DAC_RDACPD |
901 RADEON_TV_DAC_GDACPD |
902 RADEON_TV_DAC_BDACPD);
905 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
908 if (tv_dac->tv_std == TV_STD_NTSC ||
909 tv_dac->tv_std == TV_STD_NTSC_J ||
910 tv_dac->tv_std == TV_STD_PAL_M ||
911 tv_dac->tv_std == TV_STD_PAL_60)
912 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
914 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
916 if (tv_dac->tv_std == TV_STD_NTSC ||
917 tv_dac->tv_std == TV_STD_NTSC_J)
918 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
920 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
922 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
923 tv_dac->ps2_tvdac_adj);
925 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
928 if (ASIC_IS_R300(rdev)) {
929 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
930 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
933 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
934 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
936 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
938 if (rdev->family == CHIP_R200)
939 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
944 dac_cntl = RREG32(RADEON_DAC_CNTL);
945 dac_cntl &= ~RADEON_DAC_TVO_EN;
946 WREG32(RADEON_DAC_CNTL, dac_cntl);
948 if (ASIC_IS_R300(rdev))
949 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
951 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
952 if (radeon_crtc->crtc_id == 0) {
953 if (ASIC_IS_R300(rdev)) {
954 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
955 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
956 RADEON_DISP_TV_SOURCE_CRTC);
958 if (rdev->family >= CHIP_R200) {
959 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
961 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
964 if (ASIC_IS_R300(rdev)) {
965 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
966 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
968 if (rdev->family >= CHIP_R200) {
969 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
971 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
974 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
977 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
979 if (radeon_crtc->crtc_id == 0) {
980 if (ASIC_IS_R300(rdev)) {
981 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
982 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
983 } else if (rdev->family == CHIP_R200) {
984 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
985 RADEON_FP2_DVO_RATE_SEL_SDR);
987 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
989 if (ASIC_IS_R300(rdev)) {
990 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
991 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
992 } else if (rdev->family == CHIP_R200) {
993 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
994 RADEON_FP2_DVO_RATE_SEL_SDR);
995 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
997 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
999 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1002 if (ASIC_IS_R300(rdev)) {
1003 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1004 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1007 if (rdev->family >= CHIP_R200)
1008 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1010 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1012 if (rdev->family == CHIP_R200)
1013 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1016 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1018 if (rdev->is_atom_bios)
1019 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1021 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1025 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1026 struct drm_connector *connector)
1028 struct drm_device *dev = encoder->dev;
1029 struct radeon_device *rdev = dev->dev_private;
1030 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1031 uint32_t disp_output_cntl, gpiopad_a, tmp;
1034 /* save regs needed */
1035 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1036 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1037 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1038 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1039 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1040 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1042 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1044 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1046 WREG32(RADEON_CRTC2_GEN_CNTL,
1047 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1049 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1050 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1051 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1053 WREG32(RADEON_DAC_EXT_CNTL,
1054 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1055 RADEON_DAC2_FORCE_DATA_EN |
1056 RADEON_DAC_FORCE_DATA_SEL_RGB |
1057 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1059 WREG32(RADEON_TV_DAC_CNTL,
1060 RADEON_TV_DAC_STD_NTSC |
1061 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1062 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1064 RREG32(RADEON_TV_DAC_CNTL);
1067 WREG32(RADEON_TV_DAC_CNTL,
1068 RADEON_TV_DAC_NBLANK |
1069 RADEON_TV_DAC_NHOLD |
1070 RADEON_TV_MONITOR_DETECT_EN |
1071 RADEON_TV_DAC_STD_NTSC |
1072 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1073 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1075 RREG32(RADEON_TV_DAC_CNTL);
1078 tmp = RREG32(RADEON_TV_DAC_CNTL);
1079 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1081 DRM_DEBUG("S-video TV connection detected\n");
1082 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1084 DRM_DEBUG("Composite TV connection detected\n");
1087 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1088 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1089 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1090 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1091 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1092 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1096 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1097 struct drm_connector *connector)
1099 struct drm_device *dev = encoder->dev;
1100 struct radeon_device *rdev = dev->dev_private;
1101 uint32_t tv_dac_cntl, dac_cntl2;
1102 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1105 if (ASIC_IS_R300(rdev))
1106 return r300_legacy_tv_detect(encoder, connector);
1108 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1109 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1110 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1111 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1112 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1114 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1115 WREG32(RADEON_DAC_CNTL2, tmp);
1117 tmp = tv_master_cntl | RADEON_TV_ON;
1118 tmp &= ~(RADEON_TV_ASYNC_RST |
1119 RADEON_RESTART_PHASE_FIX |
1120 RADEON_CRT_FIFO_CE_EN |
1121 RADEON_TV_FIFO_CE_EN |
1122 RADEON_RE_SYNC_NOW_SEL_MASK);
1123 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1124 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1126 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1127 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1128 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1130 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1131 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1133 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1134 WREG32(RADEON_TV_DAC_CNTL, tmp);
1136 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1137 RADEON_RED_MX_FORCE_DAC_DATA |
1138 RADEON_GRN_MX_FORCE_DAC_DATA |
1139 RADEON_BLU_MX_FORCE_DAC_DATA |
1140 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1141 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1144 tmp = RREG32(RADEON_TV_DAC_CNTL);
1145 if (tmp & RADEON_TV_DAC_GDACDET) {
1147 DRM_DEBUG("S-video TV connection detected\n");
1148 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1150 DRM_DEBUG("Composite TV connection detected\n");
1153 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1154 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1155 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1156 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1160 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1161 struct drm_connector *connector)
1163 struct drm_device *dev = encoder->dev;
1164 struct radeon_device *rdev = dev->dev_private;
1165 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1166 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1167 enum drm_connector_status found = connector_status_disconnected;
1168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1169 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1171 struct drm_crtc *crtc;
1173 /* find out if crtc2 is in use or if this encoder is using it */
1174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1175 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1176 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1177 if (encoder->crtc != crtc) {
1178 return connector_status_disconnected;
1183 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1184 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1185 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1188 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1189 return connector_status_disconnected;
1191 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1192 if (tv_detect && tv_dac)
1193 found = connector_status_connected;
1197 /* don't probe if the encoder is being used for something else not CRT related */
1198 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1199 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1200 return connector_status_disconnected;
1203 /* save the regs we need */
1204 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1205 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1206 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1207 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1208 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1209 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1210 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1211 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1213 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1214 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1215 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1217 if (ASIC_IS_R300(rdev))
1218 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1220 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1221 tmp |= RADEON_CRTC2_CRT2_ON |
1222 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1224 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1226 if (ASIC_IS_R300(rdev)) {
1227 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1228 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1229 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1231 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1232 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1235 tmp = RADEON_TV_DAC_NBLANK |
1236 RADEON_TV_DAC_NHOLD |
1237 RADEON_TV_MONITOR_DETECT_EN |
1238 RADEON_TV_DAC_STD_PS2;
1240 WREG32(RADEON_TV_DAC_CNTL, tmp);
1242 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1243 RADEON_DAC2_FORCE_DATA_EN;
1246 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1248 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1250 if (ASIC_IS_R300(rdev))
1251 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1253 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1255 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1257 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1258 WREG32(RADEON_DAC_CNTL2, tmp);
1262 if (ASIC_IS_R300(rdev)) {
1263 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1264 found = connector_status_connected;
1266 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1267 found = connector_status_connected;
1270 /* restore regs we used */
1271 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1272 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1273 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1274 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1276 if (ASIC_IS_R300(rdev)) {
1277 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1278 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1280 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1282 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1288 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1289 .dpms = radeon_legacy_tv_dac_dpms,
1290 .mode_fixup = radeon_legacy_mode_fixup,
1291 .prepare = radeon_legacy_tv_dac_prepare,
1292 .mode_set = radeon_legacy_tv_dac_mode_set,
1293 .commit = radeon_legacy_tv_dac_commit,
1294 .detect = radeon_legacy_tv_dac_detect,
1295 .disable = radeon_legacy_encoder_disable,
1299 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1300 .destroy = radeon_enc_destroy,
1304 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1306 struct drm_device *dev = encoder->base.dev;
1307 struct radeon_device *rdev = dev->dev_private;
1308 struct radeon_encoder_int_tmds *tmds = NULL;
1311 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1316 if (rdev->is_atom_bios)
1317 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1319 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1322 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1327 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1329 struct drm_device *dev = encoder->base.dev;
1330 struct radeon_device *rdev = dev->dev_private;
1331 struct radeon_encoder_ext_tmds *tmds = NULL;
1334 if (rdev->is_atom_bios)
1337 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1342 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1345 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1351 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1353 struct radeon_device *rdev = dev->dev_private;
1354 struct drm_encoder *encoder;
1355 struct radeon_encoder *radeon_encoder;
1357 /* see if we already added it */
1358 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1359 radeon_encoder = to_radeon_encoder(encoder);
1360 if (radeon_encoder->encoder_id == encoder_id) {
1361 radeon_encoder->devices |= supported_device;
1368 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1369 if (!radeon_encoder)
1372 encoder = &radeon_encoder->base;
1373 if (rdev->flags & RADEON_SINGLE_CRTC)
1374 encoder->possible_crtcs = 0x1;
1376 encoder->possible_crtcs = 0x3;
1378 radeon_encoder->enc_priv = NULL;
1380 radeon_encoder->encoder_id = encoder_id;
1381 radeon_encoder->devices = supported_device;
1382 radeon_encoder->rmx_type = RMX_OFF;
1384 switch (radeon_encoder->encoder_id) {
1385 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1386 encoder->possible_crtcs = 0x1;
1387 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1388 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1389 if (rdev->is_atom_bios)
1390 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1392 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1393 radeon_encoder->rmx_type = RMX_FULL;
1395 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1396 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1397 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1398 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1400 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1401 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1402 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1403 if (rdev->is_atom_bios)
1404 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1406 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1408 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1409 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1410 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1411 if (rdev->is_atom_bios)
1412 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1414 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1416 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1417 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1418 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1419 if (!rdev->is_atom_bios)
1420 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);