drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include "radeon_drm.h"
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 void radeon_bo_clear_va(struct radeon_bo *bo)
  50 {
  51         struct radeon_bo_va *bo_va, *tmp;
  52
  53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  54                 /* remove from all vm address space */
  55                 radeon_vm_bo_rmv(bo->rdev, bo_va->vm, bo);
  56         }
  57 }
  58
  59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  60 {
  61         struct radeon_bo *bo;
  62
  63         bo = container_of(tbo, struct radeon_bo, tbo);
  64         mutex_lock(&bo->rdev->gem.mutex);
  65         list_del_init(&bo->list);
  66         mutex_unlock(&bo->rdev->gem.mutex);
  67         radeon_bo_clear_surface_reg(bo);
  68         radeon_bo_clear_va(bo);
  69         drm_gem_object_release(&bo->gem_base);
  70         kfree(bo);
  71 }
  72
  73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  74 {
  75         if (bo->destroy == &radeon_ttm_bo_destroy)
  76                 return true;
  77         return false;
  78 }
  79
  80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  81 {
  82         u32 c = 0;
  83
  84         rbo->placement.fpfn = 0;
  85         rbo->placement.lpfn = 0;
  86         rbo->placement.placement = rbo->placements;
  87         rbo->placement.busy_placement = rbo->placements;
  88         if (domain & RADEON_GEM_DOMAIN_VRAM)
  89                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  90                                         TTM_PL_FLAG_VRAM;
  91         if (domain & RADEON_GEM_DOMAIN_GTT)
  92                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  93         if (domain & RADEON_GEM_DOMAIN_CPU)
  94                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  95         if (!c)
  96                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  97         rbo->placement.num_placement = c;
  98         rbo->placement.num_busy_placement = c;
  99 }
 100
 101 int radeon_bo_create(struct radeon_device *rdev,
 102                      unsigned long size, int byte_align, bool kernel, u32 domain,
 103                      struct sg_table *sg, struct radeon_bo **bo_ptr)
 104 {
 105         struct radeon_bo *bo;
 106         enum ttm_bo_type type;
 107         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 108         unsigned long max_size = 0;
 109         size_t acc_size;
 110         int r;
 111
 112         size = ALIGN(size, PAGE_SIZE);
 113
 114         rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 115         if (kernel) {
 116                 type = ttm_bo_type_kernel;
 117         } else if (sg) {
 118                 type = ttm_bo_type_sg;
 119         } else {
 120                 type = ttm_bo_type_device;
 121         }
 122         *bo_ptr = NULL;
 123
 124         /* maximun bo size is the minimun btw visible vram and gtt size */
 125         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
 126         if ((page_align << PAGE_SHIFT) >= max_size) {
 127                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
 128                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
 129                 return -ENOMEM;
 130         }
 131
 132         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 133                                        sizeof(struct radeon_bo));
 134
 135         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 136         if (bo == NULL)
 137                 return -ENOMEM;
 138         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 139         if (unlikely(r)) {
 140                 kfree(bo);
 141                 return r;
 142         }
 143         bo->rdev = rdev;
 144         bo->gem_base.driver_private = NULL;
 145         bo->surface_reg = -1;
 146         INIT_LIST_HEAD(&bo->list);
 147         INIT_LIST_HEAD(&bo->va);
 148
 149 retry:
 150         radeon_ttm_placement_from_domain(bo, domain);
 151         /* Kernel allocation are uninterruptible */
 152         down_read(&rdev->pm.mclk_lock);
 153         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 154                         &bo->placement, page_align, 0, !kernel, NULL,
 155                         acc_size, sg, &radeon_ttm_bo_destroy);
 156         up_read(&rdev->pm.mclk_lock);
 157         if (unlikely(r != 0)) {
 158                 if (r != -ERESTARTSYS) {
 159                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 160                                 domain |= RADEON_GEM_DOMAIN_GTT;
 161                                 goto retry;
 162                         }
 163                         dev_err(rdev->dev,
 164                                 "object_init failed for (%lu, 0x%08X)\n",
 165                                 size, domain);
 166                 }
 167                 return r;
 168         }
 169         *bo_ptr = bo;
 170
 171         trace_radeon_bo_create(bo);
 172
 173         return 0;
 174 }
 175
 176 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 177 {
 178         bool is_iomem;
 179         int r;
 180
 181         if (bo->kptr) {
 182                 if (ptr) {
 183                         *ptr = bo->kptr;
 184                 }
 185                 return 0;
 186         }
 187         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 188         if (r) {
 189                 return r;
 190         }
 191         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 192         if (ptr) {
 193                 *ptr = bo->kptr;
 194         }
 195         radeon_bo_check_tiling(bo, 0, 0);
 196         return 0;
 197 }
 198
 199 void radeon_bo_kunmap(struct radeon_bo *bo)
 200 {
 201         if (bo->kptr == NULL)
 202                 return;
 203         bo->kptr = NULL;
 204         radeon_bo_check_tiling(bo, 0, 0);
 205         ttm_bo_kunmap(&bo->kmap);
 206 }
 207
 208 void radeon_bo_unref(struct radeon_bo **bo)
 209 {
 210         struct ttm_buffer_object *tbo;
 211         struct radeon_device *rdev;
 212
 213         if ((*bo) == NULL)
 214                 return;
 215         rdev = (*bo)->rdev;
 216         tbo = &((*bo)->tbo);
 217         down_read(&rdev->pm.mclk_lock);
 218         ttm_bo_unref(&tbo);
 219         up_read(&rdev->pm.mclk_lock);
 220         if (tbo == NULL)
 221                 *bo = NULL;
 222 }
 223
 224 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 225                              u64 *gpu_addr)
 226 {
 227         int r, i;
 228
 229         if (bo->pin_count) {
 230                 bo->pin_count++;
 231                 if (gpu_addr)
 232                         *gpu_addr = radeon_bo_gpu_offset(bo);
 233
 234                 if (max_offset != 0) {
 235                         u64 domain_start;
 236
 237                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 238                                 domain_start = bo->rdev->mc.vram_start;
 239                         else
 240                                 domain_start = bo->rdev->mc.gtt_start;
 241                         WARN_ON_ONCE(max_offset <
 242                                      (radeon_bo_gpu_offset(bo) - domain_start));
 243                 }
 244
 245                 return 0;
 246         }
 247         radeon_ttm_placement_from_domain(bo, domain);
 248         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 249                 /* force to pin into visible video ram */
 250                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 251         }
 252         if (max_offset) {
 253                 u64 lpfn = max_offset >> PAGE_SHIFT;
 254
 255                 if (!bo->placement.lpfn)
 256                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 257
 258                 if (lpfn < bo->placement.lpfn)
 259                         bo->placement.lpfn = lpfn;
 260         }
 261         for (i = 0; i < bo->placement.num_placement; i++)
 262                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 263         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 264         if (likely(r == 0)) {
 265                 bo->pin_count = 1;
 266                 if (gpu_addr != NULL)
 267                         *gpu_addr = radeon_bo_gpu_offset(bo);
 268         }
 269         if (unlikely(r != 0))
 270                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 271         return r;
 272 }
 273
 274 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 275 {
 276         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 277 }
 278
 279 int radeon_bo_unpin(struct radeon_bo *bo)
 280 {
 281         int r, i;
 282
 283         if (!bo->pin_count) {
 284                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 285                 return 0;
 286         }
 287         bo->pin_count--;
 288         if (bo->pin_count)
 289                 return 0;
 290         for (i = 0; i < bo->placement.num_placement; i++)
 291                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 292         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 293         if (unlikely(r != 0))
 294                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 295         return r;
 296 }
 297
 298 int radeon_bo_evict_vram(struct radeon_device *rdev)
 299 {
 300         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 301         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 302                 if (rdev->mc.igp_sideport_enabled == false)
 303                         /* Useless to evict on IGP chips */
 304                         return 0;
 305         }
 306         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 307 }
 308
 309 void radeon_bo_force_delete(struct radeon_device *rdev)
 310 {
 311         struct radeon_bo *bo, *n;
 312
 313         if (list_empty(&rdev->gem.objects)) {
 314                 return;
 315         }
 316         dev_err(rdev->dev, "Userspace still has active objects !\n");
 317         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 318                 mutex_lock(&rdev->ddev->struct_mutex);
 319                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 320                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 321                         *((unsigned long *)&bo->gem_base.refcount));
 322                 mutex_lock(&bo->rdev->gem.mutex);
 323                 list_del_init(&bo->list);
 324                 mutex_unlock(&bo->rdev->gem.mutex);
 325                 /* this should unref the ttm bo */
 326                 drm_gem_object_unreference(&bo->gem_base);
 327                 mutex_unlock(&rdev->ddev->struct_mutex);
 328         }
 329 }
 330
 331 int radeon_bo_init(struct radeon_device *rdev)
 332 {
 333         /* Add an MTRR for the VRAM */
 334         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 335                         MTRR_TYPE_WRCOMB, 1);
 336         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 337                 rdev->mc.mc_vram_size >> 20,
 338                 (unsigned long long)rdev->mc.aper_size >> 20);
 339         DRM_INFO("RAM width %dbits %cDR\n",
 340                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 341         return radeon_ttm_init(rdev);
 342 }
 343
 344 void radeon_bo_fini(struct radeon_device *rdev)
 345 {
 346         radeon_ttm_fini(rdev);
 347 }
 348
 349 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 350                                 struct list_head *head)
 351 {
 352         if (lobj->wdomain) {
 353                 list_add(&lobj->tv.head, head);
 354         } else {
 355                 list_add_tail(&lobj->tv.head, head);
 356         }
 357 }
 358
 359 int radeon_bo_list_validate(struct list_head *head)
 360 {
 361         struct radeon_bo_list *lobj;
 362         struct radeon_bo *bo;
 363         u32 domain;
 364         int r;
 365
 366         r = ttm_eu_reserve_buffers(head);
 367         if (unlikely(r != 0)) {
 368                 return r;
 369         }
 370         list_for_each_entry(lobj, head, tv.head) {
 371                 bo = lobj->bo;
 372                 if (!bo->pin_count) {
 373                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 374
 375                 retry:
 376                         radeon_ttm_placement_from_domain(bo, domain);
 377                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 378                                                 true, false, false);
 379                         if (unlikely(r)) {
 380                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 381                                         domain |= RADEON_GEM_DOMAIN_GTT;
 382                                         goto retry;
 383                                 }
 384                                 return r;
 385                         }
 386                 }
 387                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 388                 lobj->tiling_flags = bo->tiling_flags;
 389         }
 390         return 0;
 391 }
 392
 393 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 394                              struct vm_area_struct *vma)
 395 {
 396         return ttm_fbdev_mmap(vma, &bo->tbo);
 397 }
 398
 399 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 400 {
 401         struct radeon_device *rdev = bo->rdev;
 402         struct radeon_surface_reg *reg;
 403         struct radeon_bo *old_object;
 404         int steal;
 405         int i;
 406
 407         BUG_ON(!atomic_read(&bo->tbo.reserved));
 408
 409         if (!bo->tiling_flags)
 410                 return 0;
 411
 412         if (bo->surface_reg >= 0) {
 413                 reg = &rdev->surface_regs[bo->surface_reg];
 414                 i = bo->surface_reg;
 415                 goto out;
 416         }
 417
 418         steal = -1;
 419         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 420
 421                 reg = &rdev->surface_regs[i];
 422                 if (!reg->bo)
 423                         break;
 424
 425                 old_object = reg->bo;
 426                 if (old_object->pin_count == 0)
 427                         steal = i;
 428         }
 429
 430         /* if we are all out */
 431         if (i == RADEON_GEM_MAX_SURFACES) {
 432                 if (steal == -1)
 433                         return -ENOMEM;
 434                 /* find someone with a surface reg and nuke their BO */
 435                 reg = &rdev->surface_regs[steal];
 436                 old_object = reg->bo;
 437                 /* blow away the mapping */
 438                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 439                 ttm_bo_unmap_virtual(&old_object->tbo);
 440                 old_object->surface_reg = -1;
 441                 i = steal;
 442         }
 443
 444         bo->surface_reg = i;
 445         reg->bo = bo;
 446
 447 out:
 448         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 449                                bo->tbo.mem.start << PAGE_SHIFT,
 450                                bo->tbo.num_pages << PAGE_SHIFT);
 451         return 0;
 452 }
 453
 454 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 455 {
 456         struct radeon_device *rdev = bo->rdev;
 457         struct radeon_surface_reg *reg;
 458
 459         if (bo->surface_reg == -1)
 460                 return;
 461
 462         reg = &rdev->surface_regs[bo->surface_reg];
 463         radeon_clear_surface_reg(rdev, bo->surface_reg);
 464
 465         reg->bo = NULL;
 466         bo->surface_reg = -1;
 467 }
 468
 469 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 470                                 uint32_t tiling_flags, uint32_t pitch)
 471 {
 472         struct radeon_device *rdev = bo->rdev;
 473         int r;
 474
 475         if (rdev->family >= CHIP_CEDAR) {
 476                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 477
 478                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 479                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 480                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 481                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 482                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 483                 switch (bankw) {
 484                 case 0:
 485                 case 1:
 486                 case 2:
 487                 case 4:
 488                 case 8:
 489                         break;
 490                 default:
 491                         return -EINVAL;
 492                 }
 493                 switch (bankh) {
 494                 case 0:
 495                 case 1:
 496                 case 2:
 497                 case 4:
 498                 case 8:
 499                         break;
 500                 default:
 501                         return -EINVAL;
 502                 }
 503                 switch (mtaspect) {
 504                 case 0:
 505                 case 1:
 506                 case 2:
 507                 case 4:
 508                 case 8:
 509                         break;
 510                 default:
 511                         return -EINVAL;
 512                 }
 513                 if (tilesplit > 6) {
 514                         return -EINVAL;
 515                 }
 516                 if (stilesplit > 6) {
 517                         return -EINVAL;
 518                 }
 519         }
 520         r = radeon_bo_reserve(bo, false);
 521         if (unlikely(r != 0))
 522                 return r;
 523         bo->tiling_flags = tiling_flags;
 524         bo->pitch = pitch;
 525         radeon_bo_unreserve(bo);
 526         return 0;
 527 }
 528
 529 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 530                                 uint32_t *tiling_flags,
 531                                 uint32_t *pitch)
 532 {
 533         BUG_ON(!atomic_read(&bo->tbo.reserved));
 534         if (tiling_flags)
 535                 *tiling_flags = bo->tiling_flags;
 536         if (pitch)
 537                 *pitch = bo->pitch;
 538 }
 539
 540 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 541                                 bool force_drop)
 542 {
 543         BUG_ON(!atomic_read(&bo->tbo.reserved));
 544
 545         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 546                 return 0;
 547
 548         if (force_drop) {
 549                 radeon_bo_clear_surface_reg(bo);
 550                 return 0;
 551         }
 552
 553         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 554                 if (!has_moved)
 555                         return 0;
 556
 557                 if (bo->surface_reg >= 0)
 558                         radeon_bo_clear_surface_reg(bo);
 559                 return 0;
 560         }
 561
 562         if ((bo->surface_reg >= 0) && !has_moved)
 563                 return 0;
 564
 565         return radeon_bo_get_surface_reg(bo);
 566 }
 567
 568 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 569                            struct ttm_mem_reg *mem)
 570 {
 571         struct radeon_bo *rbo;
 572         if (!radeon_ttm_bo_is_radeon_bo(bo))
 573                 return;
 574         rbo = container_of(bo, struct radeon_bo, tbo);
 575         radeon_bo_check_tiling(rbo, 0, 1);
 576         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 577 }
 578
 579 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 580 {
 581         struct radeon_device *rdev;
 582         struct radeon_bo *rbo;
 583         unsigned long offset, size;
 584         int r;
 585
 586         if (!radeon_ttm_bo_is_radeon_bo(bo))
 587                 return 0;
 588         rbo = container_of(bo, struct radeon_bo, tbo);
 589         radeon_bo_check_tiling(rbo, 0, 0);
 590         rdev = rbo->rdev;
 591         if (bo->mem.mem_type == TTM_PL_VRAM) {
 592                 size = bo->mem.num_pages << PAGE_SHIFT;
 593                 offset = bo->mem.start << PAGE_SHIFT;
 594                 if ((offset + size) > rdev->mc.visible_vram_size) {
 595                         /* hurrah the memory is not visible ! */
 596                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 597                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 598                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 599                         if (unlikely(r != 0))
 600                                 return r;
 601                         offset = bo->mem.start << PAGE_SHIFT;
 602                         /* this should not happen */
 603                         if ((offset + size) > rdev->mc.visible_vram_size)
 604                                 return -EINVAL;
 605                 }
 606         }
 607         return 0;
 608 }
 609
 610 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 611 {
 612         int r;
 613
 614         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 615         if (unlikely(r != 0))
 616                 return r;
 617         spin_lock(&bo->tbo.bdev->fence_lock);
 618         if (mem_type)
 619                 *mem_type = bo->tbo.mem.mem_type;
 620         if (bo->tbo.sync_obj)
 621                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 622         spin_unlock(&bo->tbo.bdev->fence_lock);
 623         ttm_bo_unreserve(&bo->tbo);
 624         return r;
 625 }
 626
 627
 628 /**
 629  * radeon_bo_reserve - reserve bo
 630  * @bo:         bo structure
 631  * @no_wait:            don't sleep while trying to reserve (return -EBUSY)
 632  *
 633  * Returns:
 634  * -EBUSY: buffer is busy and @no_wait is true
 635  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 636  * a signal. Release all buffer reservations and return to user-space.
 637  */
 638 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
 639 {
 640         int r;
 641
 642         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 643         if (unlikely(r != 0)) {
 644                 if (r != -ERESTARTSYS)
 645                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 646                 return r;
 647         }
 648         return 0;
 649 }
 650
 651 /* object have to be reserved */
 652 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
 653 {
 654         struct radeon_bo_va *bo_va;
 655
 656         list_for_each_entry(bo_va, &rbo->va, bo_list) {
 657                 if (bo_va->vm == vm) {
 658                         return bo_va;
 659                 }
 660         }
 661         return NULL;
 662 }