2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include "radeon_drm.h"
39 int radeon_ttm_init(struct radeon_device *rdev);
40 void radeon_ttm_fini(struct radeon_device *rdev);
41 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
44 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
45 * function are calling it.
48 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
52 bo = container_of(tbo, struct radeon_bo, tbo);
53 mutex_lock(&bo->rdev->gem.mutex);
54 list_del_init(&bo->list);
55 mutex_unlock(&bo->rdev->gem.mutex);
56 radeon_bo_clear_surface_reg(bo);
60 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
62 if (bo->destroy == &radeon_ttm_bo_destroy)
67 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
71 rbo->placement.fpfn = 0;
72 rbo->placement.lpfn = 0;
73 rbo->placement.placement = rbo->placements;
74 rbo->placement.busy_placement = rbo->placements;
75 if (domain & RADEON_GEM_DOMAIN_VRAM)
76 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
78 if (domain & RADEON_GEM_DOMAIN_GTT)
79 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
80 if (domain & RADEON_GEM_DOMAIN_CPU)
81 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
83 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
84 rbo->placement.num_placement = c;
85 rbo->placement.num_busy_placement = c;
88 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
89 unsigned long size, bool kernel, u32 domain,
90 struct radeon_bo **bo_ptr)
93 enum ttm_bo_type type;
96 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
97 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
100 type = ttm_bo_type_kernel;
102 type = ttm_bo_type_device;
105 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
110 bo->surface_reg = -1;
111 INIT_LIST_HEAD(&bo->list);
113 radeon_ttm_placement_from_domain(bo, domain);
114 /* Kernel allocation are uninterruptible */
115 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
116 &bo->placement, 0, 0, !kernel, NULL, size,
117 &radeon_ttm_bo_destroy);
118 if (unlikely(r != 0)) {
119 if (r != -ERESTARTSYS)
121 "object_init failed for (%lu, 0x%08X)\n",
127 mutex_lock(&bo->rdev->gem.mutex);
128 list_add_tail(&bo->list, &rdev->gem.objects);
129 mutex_unlock(&bo->rdev->gem.mutex);
134 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
145 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
149 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
153 radeon_bo_check_tiling(bo, 0, 0);
157 void radeon_bo_kunmap(struct radeon_bo *bo)
159 if (bo->kptr == NULL)
162 radeon_bo_check_tiling(bo, 0, 0);
163 ttm_bo_kunmap(&bo->kmap);
166 void radeon_bo_unref(struct radeon_bo **bo)
168 struct ttm_buffer_object *tbo;
178 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
185 *gpu_addr = radeon_bo_gpu_offset(bo);
188 radeon_ttm_placement_from_domain(bo, domain);
189 /* force to pin into visible video ram */
190 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
191 for (i = 0; i < bo->placement.num_placement; i++)
192 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
193 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
194 if (likely(r == 0)) {
196 if (gpu_addr != NULL)
197 *gpu_addr = radeon_bo_gpu_offset(bo);
199 if (unlikely(r != 0))
200 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
204 int radeon_bo_unpin(struct radeon_bo *bo)
208 if (!bo->pin_count) {
209 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
215 for (i = 0; i < bo->placement.num_placement; i++)
216 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
217 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
218 if (unlikely(r != 0))
219 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
223 int radeon_bo_evict_vram(struct radeon_device *rdev)
225 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
226 if (0 && (rdev->flags & RADEON_IS_IGP)) {
227 if (rdev->mc.igp_sideport_enabled == false)
228 /* Useless to evict on IGP chips */
231 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
234 void radeon_bo_force_delete(struct radeon_device *rdev)
236 struct radeon_bo *bo, *n;
237 struct drm_gem_object *gobj;
239 if (list_empty(&rdev->gem.objects)) {
242 dev_err(rdev->dev, "Userspace still has active objects !\n");
243 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
244 mutex_lock(&rdev->ddev->struct_mutex);
246 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
247 gobj, bo, (unsigned long)gobj->size,
248 *((unsigned long *)&gobj->refcount));
249 mutex_lock(&bo->rdev->gem.mutex);
250 list_del_init(&bo->list);
251 mutex_unlock(&bo->rdev->gem.mutex);
252 radeon_bo_unref(&bo);
253 gobj->driver_private = NULL;
254 drm_gem_object_unreference(gobj);
255 mutex_unlock(&rdev->ddev->struct_mutex);
259 int radeon_bo_init(struct radeon_device *rdev)
261 /* Add an MTRR for the VRAM */
262 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
263 MTRR_TYPE_WRCOMB, 1);
264 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
265 rdev->mc.mc_vram_size >> 20,
266 (unsigned long long)rdev->mc.aper_size >> 20);
267 DRM_INFO("RAM width %dbits %cDR\n",
268 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
269 return radeon_ttm_init(rdev);
272 void radeon_bo_fini(struct radeon_device *rdev)
274 radeon_ttm_fini(rdev);
277 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
278 struct list_head *head)
281 list_add(&lobj->list, head);
283 list_add_tail(&lobj->list, head);
287 int radeon_bo_list_reserve(struct list_head *head)
289 struct radeon_bo_list *lobj;
292 list_for_each_entry(lobj, head, list){
293 r = radeon_bo_reserve(lobj->bo, false);
294 if (unlikely(r != 0))
300 void radeon_bo_list_unreserve(struct list_head *head)
302 struct radeon_bo_list *lobj;
304 list_for_each_entry(lobj, head, list) {
305 /* only unreserve object we successfully reserved */
306 if (radeon_bo_is_reserved(lobj->bo))
307 radeon_bo_unreserve(lobj->bo);
311 int radeon_bo_list_validate(struct list_head *head)
313 struct radeon_bo_list *lobj;
314 struct radeon_bo *bo;
317 r = radeon_bo_list_reserve(head);
318 if (unlikely(r != 0)) {
321 list_for_each_entry(lobj, head, list) {
323 if (!bo->pin_count) {
325 radeon_ttm_placement_from_domain(bo,
328 radeon_ttm_placement_from_domain(bo,
331 r = ttm_bo_validate(&bo->tbo, &bo->placement,
336 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
337 lobj->tiling_flags = bo->tiling_flags;
342 void radeon_bo_list_fence(struct list_head *head, void *fence)
344 struct radeon_bo_list *lobj;
345 struct radeon_bo *bo;
346 struct radeon_fence *old_fence = NULL;
348 list_for_each_entry(lobj, head, list) {
350 spin_lock(&bo->tbo.lock);
351 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
352 bo->tbo.sync_obj = radeon_fence_ref(fence);
353 bo->tbo.sync_obj_arg = NULL;
354 spin_unlock(&bo->tbo.lock);
356 radeon_fence_unref(&old_fence);
361 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
362 struct vm_area_struct *vma)
364 return ttm_fbdev_mmap(vma, &bo->tbo);
367 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
369 struct radeon_device *rdev = bo->rdev;
370 struct radeon_surface_reg *reg;
371 struct radeon_bo *old_object;
375 BUG_ON(!atomic_read(&bo->tbo.reserved));
377 if (!bo->tiling_flags)
380 if (bo->surface_reg >= 0) {
381 reg = &rdev->surface_regs[bo->surface_reg];
387 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
389 reg = &rdev->surface_regs[i];
393 old_object = reg->bo;
394 if (old_object->pin_count == 0)
398 /* if we are all out */
399 if (i == RADEON_GEM_MAX_SURFACES) {
402 /* find someone with a surface reg and nuke their BO */
403 reg = &rdev->surface_regs[steal];
404 old_object = reg->bo;
405 /* blow away the mapping */
406 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
407 ttm_bo_unmap_virtual(&old_object->tbo);
408 old_object->surface_reg = -1;
416 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
417 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
418 bo->tbo.num_pages << PAGE_SHIFT);
422 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
424 struct radeon_device *rdev = bo->rdev;
425 struct radeon_surface_reg *reg;
427 if (bo->surface_reg == -1)
430 reg = &rdev->surface_regs[bo->surface_reg];
431 radeon_clear_surface_reg(rdev, bo->surface_reg);
434 bo->surface_reg = -1;
437 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
438 uint32_t tiling_flags, uint32_t pitch)
442 r = radeon_bo_reserve(bo, false);
443 if (unlikely(r != 0))
445 bo->tiling_flags = tiling_flags;
447 radeon_bo_unreserve(bo);
451 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
452 uint32_t *tiling_flags,
455 BUG_ON(!atomic_read(&bo->tbo.reserved));
457 *tiling_flags = bo->tiling_flags;
462 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
465 BUG_ON(!atomic_read(&bo->tbo.reserved));
467 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
471 radeon_bo_clear_surface_reg(bo);
475 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
479 if (bo->surface_reg >= 0)
480 radeon_bo_clear_surface_reg(bo);
484 if ((bo->surface_reg >= 0) && !has_moved)
487 return radeon_bo_get_surface_reg(bo);
490 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
491 struct ttm_mem_reg *mem)
493 struct radeon_bo *rbo;
494 if (!radeon_ttm_bo_is_radeon_bo(bo))
496 rbo = container_of(bo, struct radeon_bo, tbo);
497 radeon_bo_check_tiling(rbo, 0, 1);
500 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
502 struct radeon_bo *rbo;
503 if (!radeon_ttm_bo_is_radeon_bo(bo))
505 rbo = container_of(bo, struct radeon_bo, tbo);
506 radeon_bo_check_tiling(rbo, 0, 0);