2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
34 #include "radeon_drm.h"
38 int radeon_ttm_init(struct radeon_device *rdev);
39 void radeon_ttm_fini(struct radeon_device *rdev);
40 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
47 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
59 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
61 if (bo->destroy == &radeon_ttm_bo_destroy)
66 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
70 rbo->placement.fpfn = 0;
71 rbo->placement.lpfn = 0;
72 rbo->placement.placement = rbo->placements;
73 rbo->placement.busy_placement = rbo->placements;
74 if (domain & RADEON_GEM_DOMAIN_VRAM)
75 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
77 if (domain & RADEON_GEM_DOMAIN_GTT)
78 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
79 if (domain & RADEON_GEM_DOMAIN_CPU)
80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
83 rbo->placement.num_placement = c;
84 rbo->placement.num_busy_placement = c;
87 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
88 unsigned long size, bool kernel, u32 domain,
89 struct radeon_bo **bo_ptr)
92 enum ttm_bo_type type;
95 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
96 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
99 type = ttm_bo_type_kernel;
101 type = ttm_bo_type_device;
104 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
109 bo->surface_reg = -1;
110 INIT_LIST_HEAD(&bo->list);
112 radeon_ttm_placement_from_domain(bo, domain);
113 /* Kernel allocation are uninterruptible */
114 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
115 &bo->placement, 0, 0, !kernel, NULL, size,
116 &radeon_ttm_bo_destroy);
117 if (unlikely(r != 0)) {
118 if (r != -ERESTARTSYS)
120 "object_init failed for (%lu, 0x%08X)\n",
126 mutex_lock(&bo->rdev->gem.mutex);
127 list_add_tail(&bo->list, &rdev->gem.objects);
128 mutex_unlock(&bo->rdev->gem.mutex);
133 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
144 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
148 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
152 radeon_bo_check_tiling(bo, 0, 0);
156 void radeon_bo_kunmap(struct radeon_bo *bo)
158 if (bo->kptr == NULL)
161 radeon_bo_check_tiling(bo, 0, 0);
162 ttm_bo_kunmap(&bo->kmap);
165 void radeon_bo_unref(struct radeon_bo **bo)
167 struct ttm_buffer_object *tbo;
177 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
184 *gpu_addr = radeon_bo_gpu_offset(bo);
187 radeon_ttm_placement_from_domain(bo, domain);
188 if (domain == RADEON_GEM_DOMAIN_VRAM) {
189 /* force to pin into visible video ram */
190 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
192 for (i = 0; i < bo->placement.num_placement; i++)
193 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
194 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
195 if (likely(r == 0)) {
197 if (gpu_addr != NULL)
198 *gpu_addr = radeon_bo_gpu_offset(bo);
200 if (unlikely(r != 0))
201 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
205 int radeon_bo_unpin(struct radeon_bo *bo)
209 if (!bo->pin_count) {
210 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
216 for (i = 0; i < bo->placement.num_placement; i++)
217 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
218 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
219 if (unlikely(r != 0))
220 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
224 int radeon_bo_evict_vram(struct radeon_device *rdev)
226 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
227 if (0 && (rdev->flags & RADEON_IS_IGP)) {
228 if (rdev->mc.igp_sideport_enabled == false)
229 /* Useless to evict on IGP chips */
232 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
235 void radeon_bo_force_delete(struct radeon_device *rdev)
237 struct radeon_bo *bo, *n;
238 struct drm_gem_object *gobj;
240 if (list_empty(&rdev->gem.objects)) {
243 dev_err(rdev->dev, "Userspace still has active objects !\n");
244 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
245 mutex_lock(&rdev->ddev->struct_mutex);
247 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
248 gobj, bo, (unsigned long)gobj->size,
249 *((unsigned long *)&gobj->refcount));
250 mutex_lock(&bo->rdev->gem.mutex);
251 list_del_init(&bo->list);
252 mutex_unlock(&bo->rdev->gem.mutex);
253 radeon_bo_unref(&bo);
254 gobj->driver_private = NULL;
255 drm_gem_object_unreference(gobj);
256 mutex_unlock(&rdev->ddev->struct_mutex);
260 int radeon_bo_init(struct radeon_device *rdev)
262 /* Add an MTRR for the VRAM */
263 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
264 MTRR_TYPE_WRCOMB, 1);
265 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
266 rdev->mc.mc_vram_size >> 20,
267 (unsigned long long)rdev->mc.aper_size >> 20);
268 DRM_INFO("RAM width %dbits %cDR\n",
269 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
270 return radeon_ttm_init(rdev);
273 void radeon_bo_fini(struct radeon_device *rdev)
275 radeon_ttm_fini(rdev);
278 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
279 struct list_head *head)
282 list_add(&lobj->list, head);
284 list_add_tail(&lobj->list, head);
288 int radeon_bo_list_reserve(struct list_head *head)
290 struct radeon_bo_list *lobj;
293 list_for_each_entry(lobj, head, list){
294 r = radeon_bo_reserve(lobj->bo, false);
295 if (unlikely(r != 0))
301 void radeon_bo_list_unreserve(struct list_head *head)
303 struct radeon_bo_list *lobj;
305 list_for_each_entry(lobj, head, list) {
306 /* only unreserve object we successfully reserved */
307 if (radeon_bo_is_reserved(lobj->bo))
308 radeon_bo_unreserve(lobj->bo);
312 int radeon_bo_list_validate(struct list_head *head)
314 struct radeon_bo_list *lobj;
315 struct radeon_bo *bo;
318 r = radeon_bo_list_reserve(head);
319 if (unlikely(r != 0)) {
322 list_for_each_entry(lobj, head, list) {
324 if (!bo->pin_count) {
326 radeon_ttm_placement_from_domain(bo,
329 radeon_ttm_placement_from_domain(bo,
332 r = ttm_bo_validate(&bo->tbo, &bo->placement,
337 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
338 lobj->tiling_flags = bo->tiling_flags;
343 void radeon_bo_list_fence(struct list_head *head, void *fence)
345 struct radeon_bo_list *lobj;
346 struct radeon_bo *bo;
347 struct radeon_fence *old_fence = NULL;
349 list_for_each_entry(lobj, head, list) {
351 spin_lock(&bo->tbo.lock);
352 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
353 bo->tbo.sync_obj = radeon_fence_ref(fence);
354 bo->tbo.sync_obj_arg = NULL;
355 spin_unlock(&bo->tbo.lock);
357 radeon_fence_unref(&old_fence);
362 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
363 struct vm_area_struct *vma)
365 return ttm_fbdev_mmap(vma, &bo->tbo);
368 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
370 struct radeon_device *rdev = bo->rdev;
371 struct radeon_surface_reg *reg;
372 struct radeon_bo *old_object;
376 BUG_ON(!atomic_read(&bo->tbo.reserved));
378 if (!bo->tiling_flags)
381 if (bo->surface_reg >= 0) {
382 reg = &rdev->surface_regs[bo->surface_reg];
388 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
390 reg = &rdev->surface_regs[i];
394 old_object = reg->bo;
395 if (old_object->pin_count == 0)
399 /* if we are all out */
400 if (i == RADEON_GEM_MAX_SURFACES) {
403 /* find someone with a surface reg and nuke their BO */
404 reg = &rdev->surface_regs[steal];
405 old_object = reg->bo;
406 /* blow away the mapping */
407 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
408 ttm_bo_unmap_virtual(&old_object->tbo);
409 old_object->surface_reg = -1;
417 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
418 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
419 bo->tbo.num_pages << PAGE_SHIFT);
423 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
425 struct radeon_device *rdev = bo->rdev;
426 struct radeon_surface_reg *reg;
428 if (bo->surface_reg == -1)
431 reg = &rdev->surface_regs[bo->surface_reg];
432 radeon_clear_surface_reg(rdev, bo->surface_reg);
435 bo->surface_reg = -1;
438 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
439 uint32_t tiling_flags, uint32_t pitch)
443 r = radeon_bo_reserve(bo, false);
444 if (unlikely(r != 0))
446 bo->tiling_flags = tiling_flags;
448 radeon_bo_unreserve(bo);
452 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
453 uint32_t *tiling_flags,
456 BUG_ON(!atomic_read(&bo->tbo.reserved));
458 *tiling_flags = bo->tiling_flags;
463 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
466 BUG_ON(!atomic_read(&bo->tbo.reserved));
468 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
472 radeon_bo_clear_surface_reg(bo);
476 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
480 if (bo->surface_reg >= 0)
481 radeon_bo_clear_surface_reg(bo);
485 if ((bo->surface_reg >= 0) && !has_moved)
488 return radeon_bo_get_surface_reg(bo);
491 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
492 struct ttm_mem_reg *mem)
494 struct radeon_bo *rbo;
495 if (!radeon_ttm_bo_is_radeon_bo(bo))
497 rbo = container_of(bo, struct radeon_bo, tbo);
498 radeon_bo_check_tiling(rbo, 0, 1);
501 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
503 struct radeon_bo *rbo;
504 if (!radeon_ttm_bo_is_radeon_bo(bo))
506 rbo = container_of(bo, struct radeon_bo, tbo);
507 radeon_bo_check_tiling(rbo, 0, 0);