2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include "radeon_drm.h"
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
53 bo = container_of(tbo, struct radeon_bo, tbo);
54 mutex_lock(&bo->rdev->gem.mutex);
55 list_del_init(&bo->list);
56 mutex_unlock(&bo->rdev->gem.mutex);
57 radeon_bo_clear_surface_reg(bo);
61 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
63 if (bo->destroy == &radeon_ttm_bo_destroy)
68 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
72 rbo->placement.fpfn = 0;
73 rbo->placement.lpfn = 0;
74 rbo->placement.placement = rbo->placements;
75 rbo->placement.busy_placement = rbo->placements;
76 if (domain & RADEON_GEM_DOMAIN_VRAM)
77 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
79 if (domain & RADEON_GEM_DOMAIN_GTT)
80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
81 if (domain & RADEON_GEM_DOMAIN_CPU)
82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
84 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
85 rbo->placement.num_placement = c;
86 rbo->placement.num_busy_placement = c;
89 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
90 unsigned long size, int byte_align, bool kernel, u32 domain,
91 struct radeon_bo **bo_ptr)
94 enum ttm_bo_type type;
95 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
96 unsigned long max_size = 0;
99 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
100 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
103 type = ttm_bo_type_kernel;
105 type = ttm_bo_type_device;
109 /* maximun bo size is the minimun btw visible vram and gtt size */
110 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
111 if ((page_align << PAGE_SHIFT) >= max_size) {
112 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
113 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
118 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
123 bo->surface_reg = -1;
124 INIT_LIST_HEAD(&bo->list);
125 radeon_ttm_placement_from_domain(bo, domain);
126 /* Kernel allocation are uninterruptible */
127 mutex_lock(&rdev->vram_mutex);
128 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
129 &bo->placement, page_align, 0, !kernel, NULL, size,
130 &radeon_ttm_bo_destroy);
131 mutex_unlock(&rdev->vram_mutex);
132 if (unlikely(r != 0)) {
133 if (r != -ERESTARTSYS) {
134 if (domain == RADEON_GEM_DOMAIN_VRAM) {
135 domain |= RADEON_GEM_DOMAIN_GTT;
139 "object_init failed for (%lu, 0x%08X)\n",
146 mutex_lock(&bo->rdev->gem.mutex);
147 list_add_tail(&bo->list, &rdev->gem.objects);
148 mutex_unlock(&bo->rdev->gem.mutex);
150 trace_radeon_bo_create(bo);
154 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
165 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
169 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
173 radeon_bo_check_tiling(bo, 0, 0);
177 void radeon_bo_kunmap(struct radeon_bo *bo)
179 if (bo->kptr == NULL)
182 radeon_bo_check_tiling(bo, 0, 0);
183 ttm_bo_kunmap(&bo->kmap);
186 void radeon_bo_unref(struct radeon_bo **bo)
188 struct ttm_buffer_object *tbo;
189 struct radeon_device *rdev;
195 mutex_lock(&rdev->vram_mutex);
197 mutex_unlock(&rdev->vram_mutex);
202 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
209 *gpu_addr = radeon_bo_gpu_offset(bo);
212 radeon_ttm_placement_from_domain(bo, domain);
213 if (domain == RADEON_GEM_DOMAIN_VRAM) {
214 /* force to pin into visible video ram */
215 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
217 for (i = 0; i < bo->placement.num_placement; i++)
218 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
219 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
220 if (likely(r == 0)) {
222 if (gpu_addr != NULL)
223 *gpu_addr = radeon_bo_gpu_offset(bo);
225 if (unlikely(r != 0))
226 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
230 int radeon_bo_unpin(struct radeon_bo *bo)
234 if (!bo->pin_count) {
235 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
241 for (i = 0; i < bo->placement.num_placement; i++)
242 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
243 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
244 if (unlikely(r != 0))
245 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
249 int radeon_bo_evict_vram(struct radeon_device *rdev)
251 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
252 if (0 && (rdev->flags & RADEON_IS_IGP)) {
253 if (rdev->mc.igp_sideport_enabled == false)
254 /* Useless to evict on IGP chips */
257 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
260 void radeon_bo_force_delete(struct radeon_device *rdev)
262 struct radeon_bo *bo, *n;
263 struct drm_gem_object *gobj;
265 if (list_empty(&rdev->gem.objects)) {
268 dev_err(rdev->dev, "Userspace still has active objects !\n");
269 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
270 mutex_lock(&rdev->ddev->struct_mutex);
272 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
273 gobj, bo, (unsigned long)gobj->size,
274 *((unsigned long *)&gobj->refcount));
275 mutex_lock(&bo->rdev->gem.mutex);
276 list_del_init(&bo->list);
277 mutex_unlock(&bo->rdev->gem.mutex);
278 radeon_bo_unref(&bo);
279 gobj->driver_private = NULL;
280 drm_gem_object_unreference(gobj);
281 mutex_unlock(&rdev->ddev->struct_mutex);
285 int radeon_bo_init(struct radeon_device *rdev)
287 /* Add an MTRR for the VRAM */
288 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
289 MTRR_TYPE_WRCOMB, 1);
290 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
291 rdev->mc.mc_vram_size >> 20,
292 (unsigned long long)rdev->mc.aper_size >> 20);
293 DRM_INFO("RAM width %dbits %cDR\n",
294 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
295 return radeon_ttm_init(rdev);
298 void radeon_bo_fini(struct radeon_device *rdev)
300 radeon_ttm_fini(rdev);
303 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
304 struct list_head *head)
307 list_add(&lobj->tv.head, head);
309 list_add_tail(&lobj->tv.head, head);
313 int radeon_bo_list_validate(struct list_head *head)
315 struct radeon_bo_list *lobj;
316 struct radeon_bo *bo;
320 r = ttm_eu_reserve_buffers(head);
321 if (unlikely(r != 0)) {
324 list_for_each_entry(lobj, head, tv.head) {
326 if (!bo->pin_count) {
327 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
330 radeon_ttm_placement_from_domain(bo, domain);
331 r = ttm_bo_validate(&bo->tbo, &bo->placement,
334 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
335 domain |= RADEON_GEM_DOMAIN_GTT;
341 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
342 lobj->tiling_flags = bo->tiling_flags;
347 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
348 struct vm_area_struct *vma)
350 return ttm_fbdev_mmap(vma, &bo->tbo);
353 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
355 struct radeon_device *rdev = bo->rdev;
356 struct radeon_surface_reg *reg;
357 struct radeon_bo *old_object;
361 BUG_ON(!atomic_read(&bo->tbo.reserved));
363 if (!bo->tiling_flags)
366 if (bo->surface_reg >= 0) {
367 reg = &rdev->surface_regs[bo->surface_reg];
373 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
375 reg = &rdev->surface_regs[i];
379 old_object = reg->bo;
380 if (old_object->pin_count == 0)
384 /* if we are all out */
385 if (i == RADEON_GEM_MAX_SURFACES) {
388 /* find someone with a surface reg and nuke their BO */
389 reg = &rdev->surface_regs[steal];
390 old_object = reg->bo;
391 /* blow away the mapping */
392 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
393 ttm_bo_unmap_virtual(&old_object->tbo);
394 old_object->surface_reg = -1;
402 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
403 bo->tbo.mem.start << PAGE_SHIFT,
404 bo->tbo.num_pages << PAGE_SHIFT);
408 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
410 struct radeon_device *rdev = bo->rdev;
411 struct radeon_surface_reg *reg;
413 if (bo->surface_reg == -1)
416 reg = &rdev->surface_regs[bo->surface_reg];
417 radeon_clear_surface_reg(rdev, bo->surface_reg);
420 bo->surface_reg = -1;
423 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
424 uint32_t tiling_flags, uint32_t pitch)
428 r = radeon_bo_reserve(bo, false);
429 if (unlikely(r != 0))
431 bo->tiling_flags = tiling_flags;
433 radeon_bo_unreserve(bo);
437 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
438 uint32_t *tiling_flags,
441 BUG_ON(!atomic_read(&bo->tbo.reserved));
443 *tiling_flags = bo->tiling_flags;
448 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
451 BUG_ON(!atomic_read(&bo->tbo.reserved));
453 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
457 radeon_bo_clear_surface_reg(bo);
461 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
465 if (bo->surface_reg >= 0)
466 radeon_bo_clear_surface_reg(bo);
470 if ((bo->surface_reg >= 0) && !has_moved)
473 return radeon_bo_get_surface_reg(bo);
476 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
477 struct ttm_mem_reg *mem)
479 struct radeon_bo *rbo;
480 if (!radeon_ttm_bo_is_radeon_bo(bo))
482 rbo = container_of(bo, struct radeon_bo, tbo);
483 radeon_bo_check_tiling(rbo, 0, 1);
486 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
488 struct radeon_device *rdev;
489 struct radeon_bo *rbo;
490 unsigned long offset, size;
493 if (!radeon_ttm_bo_is_radeon_bo(bo))
495 rbo = container_of(bo, struct radeon_bo, tbo);
496 radeon_bo_check_tiling(rbo, 0, 0);
498 if (bo->mem.mem_type == TTM_PL_VRAM) {
499 size = bo->mem.num_pages << PAGE_SHIFT;
500 offset = bo->mem.start << PAGE_SHIFT;
501 if ((offset + size) > rdev->mc.visible_vram_size) {
502 /* hurrah the memory is not visible ! */
503 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
504 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
505 r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
506 if (unlikely(r != 0))
508 offset = bo->mem.start << PAGE_SHIFT;
509 /* this should not happen */
510 if ((offset + size) > rdev->mc.visible_vram_size)