2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
55 int found_instance = -1;
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
60 if (found_instance == instance)
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
102 if (rdev->pm.active_crtc_count > 1)
103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
143 struct radeon_bo *bo, *n;
145 if (list_empty(&rdev->gem.objects))
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 static void radeon_set_power_state(struct radeon_device *rdev)
167 bool misc_after = false;
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
201 radeon_sync_with_vblank(rdev);
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
208 radeon_pm_prepare(rdev);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
223 /* set memory clock */
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
236 radeon_pm_finish(rdev);
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 mutex_lock(&rdev->ddev->struct_mutex);
254 down_write(&rdev->pm.mclk_lock);
255 mutex_lock(&rdev->ring_lock);
257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
263 r = radeon_fence_wait_empty(rdev, i);
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
273 radeon_unmap_vram_bos(rdev);
275 if (rdev->irq.installed) {
276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
284 radeon_set_power_state(rdev);
286 if (rdev->irq.installed) {
287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
302 mutex_unlock(&rdev->ring_lock);
303 up_write(&rdev->pm.mclk_lock);
304 mutex_unlock(&rdev->ddev->struct_mutex);
307 static void radeon_pm_print_states(struct radeon_device *rdev)
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
330 clock_info->sclk * 10);
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
345 struct drm_device *ddev = dev_get_drvdata(dev);
346 struct radeon_device *rdev = ddev->dev_private;
347 int cp = rdev->pm.profile;
349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
352 (cp == PM_PROFILE_MID) ? "mid" :
353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
364 /* Can't set profile when the card is off */
365 if ((rdev->flags & RADEON_IS_PX) &&
366 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
369 mutex_lock(&rdev->pm.mutex);
370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
371 if (strncmp("default", buf, strlen("default")) == 0)
372 rdev->pm.profile = PM_PROFILE_DEFAULT;
373 else if (strncmp("auto", buf, strlen("auto")) == 0)
374 rdev->pm.profile = PM_PROFILE_AUTO;
375 else if (strncmp("low", buf, strlen("low")) == 0)
376 rdev->pm.profile = PM_PROFILE_LOW;
377 else if (strncmp("mid", buf, strlen("mid")) == 0)
378 rdev->pm.profile = PM_PROFILE_MID;
379 else if (strncmp("high", buf, strlen("high")) == 0)
380 rdev->pm.profile = PM_PROFILE_HIGH;
385 radeon_pm_update_profile(rdev);
386 radeon_pm_set_clocks(rdev);
391 mutex_unlock(&rdev->pm.mutex);
396 static ssize_t radeon_get_pm_method(struct device *dev,
397 struct device_attribute *attr,
400 struct drm_device *ddev = dev_get_drvdata(dev);
401 struct radeon_device *rdev = ddev->dev_private;
402 int pm = rdev->pm.pm_method;
404 return snprintf(buf, PAGE_SIZE, "%s\n",
405 (pm == PM_METHOD_DYNPM) ? "dynpm" :
406 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
409 static ssize_t radeon_set_pm_method(struct device *dev,
410 struct device_attribute *attr,
414 struct drm_device *ddev = dev_get_drvdata(dev);
415 struct radeon_device *rdev = ddev->dev_private;
417 /* Can't set method when the card is off */
418 if ((rdev->flags & RADEON_IS_PX) &&
419 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
424 /* we don't support the legacy modes with dpm */
425 if (rdev->pm.pm_method == PM_METHOD_DPM) {
430 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
431 mutex_lock(&rdev->pm.mutex);
432 rdev->pm.pm_method = PM_METHOD_DYNPM;
433 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
434 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
435 mutex_unlock(&rdev->pm.mutex);
436 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
437 mutex_lock(&rdev->pm.mutex);
439 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
440 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
441 rdev->pm.pm_method = PM_METHOD_PROFILE;
442 mutex_unlock(&rdev->pm.mutex);
443 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
448 radeon_pm_compute_clocks(rdev);
453 static ssize_t radeon_get_dpm_state(struct device *dev,
454 struct device_attribute *attr,
457 struct drm_device *ddev = dev_get_drvdata(dev);
458 struct radeon_device *rdev = ddev->dev_private;
459 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
461 if ((rdev->flags & RADEON_IS_PX) &&
462 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
463 return snprintf(buf, PAGE_SIZE, "off\n");
465 return snprintf(buf, PAGE_SIZE, "%s\n",
466 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
467 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
470 static ssize_t radeon_set_dpm_state(struct device *dev,
471 struct device_attribute *attr,
475 struct drm_device *ddev = dev_get_drvdata(dev);
476 struct radeon_device *rdev = ddev->dev_private;
478 /* Can't set dpm state when the card is off */
479 if ((rdev->flags & RADEON_IS_PX) &&
480 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
483 mutex_lock(&rdev->pm.mutex);
484 if (strncmp("battery", buf, strlen("battery")) == 0)
485 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
486 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
487 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
488 else if (strncmp("performance", buf, strlen("performance")) == 0)
489 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
491 mutex_unlock(&rdev->pm.mutex);
495 mutex_unlock(&rdev->pm.mutex);
496 radeon_pm_compute_clocks(rdev);
501 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
502 struct device_attribute *attr,
505 struct drm_device *ddev = dev_get_drvdata(dev);
506 struct radeon_device *rdev = ddev->dev_private;
507 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
509 if ((rdev->flags & RADEON_IS_PX) &&
510 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
511 return snprintf(buf, PAGE_SIZE, "off\n");
513 return snprintf(buf, PAGE_SIZE, "%s\n",
514 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
515 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
518 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
519 struct device_attribute *attr,
523 struct drm_device *ddev = dev_get_drvdata(dev);
524 struct radeon_device *rdev = ddev->dev_private;
525 enum radeon_dpm_forced_level level;
528 /* Can't force performance level when the card is off */
529 if ((rdev->flags & RADEON_IS_PX) &&
530 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
533 mutex_lock(&rdev->pm.mutex);
534 if (strncmp("low", buf, strlen("low")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_LOW;
536 } else if (strncmp("high", buf, strlen("high")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_HIGH;
538 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
539 level = RADEON_DPM_FORCED_LEVEL_AUTO;
544 if (rdev->asic->dpm.force_performance_level) {
545 if (rdev->pm.dpm.thermal_active) {
549 ret = radeon_dpm_force_performance_level(rdev, level);
554 mutex_unlock(&rdev->pm.mutex);
559 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
560 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
561 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
562 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
563 radeon_get_dpm_forced_performance_level,
564 radeon_set_dpm_forced_performance_level);
566 static ssize_t radeon_hwmon_show_temp(struct device *dev,
567 struct device_attribute *attr,
570 struct radeon_device *rdev = dev_get_drvdata(dev);
571 struct drm_device *ddev = rdev->ddev;
574 /* Can't get temperature when the card is off */
575 if ((rdev->flags & RADEON_IS_PX) &&
576 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
579 if (rdev->asic->pm.get_temperature)
580 temp = radeon_get_temperature(rdev);
584 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
587 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
588 struct device_attribute *attr,
591 struct radeon_device *rdev = dev_get_drvdata(dev);
592 int hyst = to_sensor_dev_attr(attr)->index;
596 temp = rdev->pm.dpm.thermal.min_temp;
598 temp = rdev->pm.dpm.thermal.max_temp;
600 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
603 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
604 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
605 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
607 static struct attribute *hwmon_attributes[] = {
608 &sensor_dev_attr_temp1_input.dev_attr.attr,
609 &sensor_dev_attr_temp1_crit.dev_attr.attr,
610 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
614 static umode_t hwmon_attributes_visible(struct kobject *kobj,
615 struct attribute *attr, int index)
617 struct device *dev = container_of(kobj, struct device, kobj);
618 struct radeon_device *rdev = dev_get_drvdata(dev);
620 /* Skip limit attributes if DPM is not enabled */
621 if (rdev->pm.pm_method != PM_METHOD_DPM &&
622 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
623 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
629 static const struct attribute_group hwmon_attrgroup = {
630 .attrs = hwmon_attributes,
631 .is_visible = hwmon_attributes_visible,
634 static const struct attribute_group *hwmon_groups[] = {
639 static int radeon_hwmon_init(struct radeon_device *rdev)
643 switch (rdev->pm.int_thermal_type) {
644 case THERMAL_TYPE_RV6XX:
645 case THERMAL_TYPE_RV770:
646 case THERMAL_TYPE_EVERGREEN:
647 case THERMAL_TYPE_NI:
648 case THERMAL_TYPE_SUMO:
649 case THERMAL_TYPE_SI:
650 case THERMAL_TYPE_CI:
651 case THERMAL_TYPE_KV:
652 if (rdev->asic->pm.get_temperature == NULL)
654 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
657 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
658 err = PTR_ERR(rdev->pm.int_hwmon_dev);
660 "Unable to register hwmon device: %d\n", err);
670 static void radeon_hwmon_fini(struct radeon_device *rdev)
672 if (rdev->pm.int_hwmon_dev)
673 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
676 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
678 struct radeon_device *rdev =
679 container_of(work, struct radeon_device,
680 pm.dpm.thermal.work);
681 /* switch to the thermal state */
682 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
684 if (!rdev->pm.dpm_enabled)
687 if (rdev->asic->pm.get_temperature) {
688 int temp = radeon_get_temperature(rdev);
690 if (temp < rdev->pm.dpm.thermal.min_temp)
691 /* switch back the user state */
692 dpm_state = rdev->pm.dpm.user_state;
694 if (rdev->pm.dpm.thermal.high_to_low)
695 /* switch back the user state */
696 dpm_state = rdev->pm.dpm.user_state;
698 mutex_lock(&rdev->pm.mutex);
699 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
700 rdev->pm.dpm.thermal_active = true;
702 rdev->pm.dpm.thermal_active = false;
703 rdev->pm.dpm.state = dpm_state;
704 mutex_unlock(&rdev->pm.mutex);
706 radeon_pm_compute_clocks(rdev);
709 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
710 enum radeon_pm_state_type dpm_state)
713 struct radeon_ps *ps;
715 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
718 /* check if the vblank period is too short to adjust the mclk */
719 if (single_display && rdev->asic->dpm.vblank_too_short) {
720 if (radeon_dpm_vblank_too_short(rdev))
721 single_display = false;
724 /* certain older asics have a separare 3D performance state,
725 * so try that first if the user selected performance
727 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
728 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
729 /* balanced states don't exist at the moment */
730 if (dpm_state == POWER_STATE_TYPE_BALANCED)
731 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
734 /* Pick the best power state based on current conditions */
735 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
736 ps = &rdev->pm.dpm.ps[i];
737 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
740 case POWER_STATE_TYPE_BATTERY:
741 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
742 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
749 case POWER_STATE_TYPE_BALANCED:
750 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
751 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
758 case POWER_STATE_TYPE_PERFORMANCE:
759 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
760 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
767 /* internal states */
768 case POWER_STATE_TYPE_INTERNAL_UVD:
769 if (rdev->pm.dpm.uvd_ps)
770 return rdev->pm.dpm.uvd_ps;
773 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
774 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
777 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
778 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
781 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
782 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
785 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
786 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
789 case POWER_STATE_TYPE_INTERNAL_BOOT:
790 return rdev->pm.dpm.boot_ps;
791 case POWER_STATE_TYPE_INTERNAL_THERMAL:
792 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
795 case POWER_STATE_TYPE_INTERNAL_ACPI:
796 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
799 case POWER_STATE_TYPE_INTERNAL_ULV:
800 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
803 case POWER_STATE_TYPE_INTERNAL_3DPERF:
804 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
811 /* use a fallback state if we didn't match */
813 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
814 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
816 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
817 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
818 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
819 if (rdev->pm.dpm.uvd_ps) {
820 return rdev->pm.dpm.uvd_ps;
822 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
825 case POWER_STATE_TYPE_INTERNAL_THERMAL:
826 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
828 case POWER_STATE_TYPE_INTERNAL_ACPI:
829 dpm_state = POWER_STATE_TYPE_BATTERY;
831 case POWER_STATE_TYPE_BATTERY:
832 case POWER_STATE_TYPE_BALANCED:
833 case POWER_STATE_TYPE_INTERNAL_3DPERF:
834 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
843 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
846 struct radeon_ps *ps;
847 enum radeon_pm_state_type dpm_state;
850 /* if dpm init failed */
851 if (!rdev->pm.dpm_enabled)
854 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
855 /* add other state override checks here */
856 if ((!rdev->pm.dpm.thermal_active) &&
857 (!rdev->pm.dpm.uvd_active))
858 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
860 dpm_state = rdev->pm.dpm.state;
862 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
864 rdev->pm.dpm.requested_ps = ps;
868 /* no need to reprogram if nothing changed unless we are on BTC+ */
869 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
870 /* vce just modifies an existing state so force a change */
871 if (ps->vce_active != rdev->pm.dpm.vce_active)
873 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
874 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
875 * all we need to do is update the display configuration.
877 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
878 /* update display watermarks based on new power state */
879 radeon_bandwidth_update(rdev);
880 /* update displays */
881 radeon_dpm_display_configuration_changed(rdev);
882 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
883 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
887 /* for BTC+ if the num crtcs hasn't changed and state is the same,
888 * nothing to do, if the num crtcs is > 1 and state is the same,
889 * update display configuration.
891 if (rdev->pm.dpm.new_active_crtcs ==
892 rdev->pm.dpm.current_active_crtcs) {
895 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
896 (rdev->pm.dpm.new_active_crtc_count > 1)) {
897 /* update display watermarks based on new power state */
898 radeon_bandwidth_update(rdev);
899 /* update displays */
900 radeon_dpm_display_configuration_changed(rdev);
901 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
902 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
910 if (radeon_dpm == 1) {
911 printk("switching from power state:\n");
912 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
913 printk("switching to power state:\n");
914 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
917 mutex_lock(&rdev->ddev->struct_mutex);
918 down_write(&rdev->pm.mclk_lock);
919 mutex_lock(&rdev->ring_lock);
921 /* update whether vce is active */
922 ps->vce_active = rdev->pm.dpm.vce_active;
924 ret = radeon_dpm_pre_set_power_state(rdev);
928 /* update display watermarks based on new power state */
929 radeon_bandwidth_update(rdev);
930 /* update displays */
931 radeon_dpm_display_configuration_changed(rdev);
933 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
934 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
936 /* wait for the rings to drain */
937 for (i = 0; i < RADEON_NUM_RINGS; i++) {
938 struct radeon_ring *ring = &rdev->ring[i];
940 radeon_fence_wait_empty(rdev, i);
943 /* program the new power state */
944 radeon_dpm_set_power_state(rdev);
946 /* update current power state */
947 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
949 radeon_dpm_post_set_power_state(rdev);
951 if (rdev->asic->dpm.force_performance_level) {
952 if (rdev->pm.dpm.thermal_active) {
953 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
954 /* force low perf level for thermal */
955 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
956 /* save the user's level */
957 rdev->pm.dpm.forced_level = level;
959 /* otherwise, user selected level */
960 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
965 mutex_unlock(&rdev->ring_lock);
966 up_write(&rdev->pm.mclk_lock);
967 mutex_unlock(&rdev->ddev->struct_mutex);
970 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
972 enum radeon_pm_state_type dpm_state;
974 if (rdev->asic->dpm.powergate_uvd) {
975 mutex_lock(&rdev->pm.mutex);
976 /* don't powergate anything if we
977 have active but pause streams */
978 enable |= rdev->pm.dpm.sd > 0;
979 enable |= rdev->pm.dpm.hd > 0;
980 /* enable/disable UVD */
981 radeon_dpm_powergate_uvd(rdev, !enable);
982 mutex_unlock(&rdev->pm.mutex);
985 mutex_lock(&rdev->pm.mutex);
986 rdev->pm.dpm.uvd_active = true;
987 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
988 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
989 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
990 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
991 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
992 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
993 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
994 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
996 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
997 rdev->pm.dpm.state = dpm_state;
998 mutex_unlock(&rdev->pm.mutex);
1000 mutex_lock(&rdev->pm.mutex);
1001 rdev->pm.dpm.uvd_active = false;
1002 mutex_unlock(&rdev->pm.mutex);
1005 radeon_pm_compute_clocks(rdev);
1009 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1012 mutex_lock(&rdev->pm.mutex);
1013 rdev->pm.dpm.vce_active = true;
1014 /* XXX select vce level based on ring/task */
1015 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1016 mutex_unlock(&rdev->pm.mutex);
1018 mutex_lock(&rdev->pm.mutex);
1019 rdev->pm.dpm.vce_active = false;
1020 mutex_unlock(&rdev->pm.mutex);
1023 radeon_pm_compute_clocks(rdev);
1026 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1028 mutex_lock(&rdev->pm.mutex);
1029 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1030 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1031 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1033 mutex_unlock(&rdev->pm.mutex);
1035 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1038 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1040 mutex_lock(&rdev->pm.mutex);
1042 radeon_dpm_disable(rdev);
1043 /* reset the power state */
1044 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1045 rdev->pm.dpm_enabled = false;
1046 mutex_unlock(&rdev->pm.mutex);
1049 void radeon_pm_suspend(struct radeon_device *rdev)
1051 if (rdev->pm.pm_method == PM_METHOD_DPM)
1052 radeon_pm_suspend_dpm(rdev);
1054 radeon_pm_suspend_old(rdev);
1057 static void radeon_pm_resume_old(struct radeon_device *rdev)
1059 /* set up the default clocks if the MC ucode is loaded */
1060 if ((rdev->family >= CHIP_BARTS) &&
1061 (rdev->family <= CHIP_CAYMAN) &&
1063 if (rdev->pm.default_vddc)
1064 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1065 SET_VOLTAGE_TYPE_ASIC_VDDC);
1066 if (rdev->pm.default_vddci)
1067 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1068 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1069 if (rdev->pm.default_sclk)
1070 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1071 if (rdev->pm.default_mclk)
1072 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1074 /* asic init will reset the default power state */
1075 mutex_lock(&rdev->pm.mutex);
1076 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1077 rdev->pm.current_clock_mode_index = 0;
1078 rdev->pm.current_sclk = rdev->pm.default_sclk;
1079 rdev->pm.current_mclk = rdev->pm.default_mclk;
1080 if (rdev->pm.power_state) {
1081 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1082 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1084 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1085 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1086 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1087 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1088 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1090 mutex_unlock(&rdev->pm.mutex);
1091 radeon_pm_compute_clocks(rdev);
1094 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1098 /* asic init will reset to the boot state */
1099 mutex_lock(&rdev->pm.mutex);
1100 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1101 radeon_dpm_setup_asic(rdev);
1102 ret = radeon_dpm_enable(rdev);
1103 mutex_unlock(&rdev->pm.mutex);
1105 goto dpm_resume_fail;
1106 rdev->pm.dpm_enabled = true;
1107 radeon_pm_compute_clocks(rdev);
1111 DRM_ERROR("radeon: dpm resume failed\n");
1112 if ((rdev->family >= CHIP_BARTS) &&
1113 (rdev->family <= CHIP_CAYMAN) &&
1115 if (rdev->pm.default_vddc)
1116 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1117 SET_VOLTAGE_TYPE_ASIC_VDDC);
1118 if (rdev->pm.default_vddci)
1119 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1120 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1121 if (rdev->pm.default_sclk)
1122 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1123 if (rdev->pm.default_mclk)
1124 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1128 void radeon_pm_resume(struct radeon_device *rdev)
1130 if (rdev->pm.pm_method == PM_METHOD_DPM)
1131 radeon_pm_resume_dpm(rdev);
1133 radeon_pm_resume_old(rdev);
1136 static int radeon_pm_init_old(struct radeon_device *rdev)
1140 rdev->pm.profile = PM_PROFILE_DEFAULT;
1141 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1142 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1143 rdev->pm.dynpm_can_upclock = true;
1144 rdev->pm.dynpm_can_downclock = true;
1145 rdev->pm.default_sclk = rdev->clock.default_sclk;
1146 rdev->pm.default_mclk = rdev->clock.default_mclk;
1147 rdev->pm.current_sclk = rdev->clock.default_sclk;
1148 rdev->pm.current_mclk = rdev->clock.default_mclk;
1149 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1152 if (rdev->is_atom_bios)
1153 radeon_atombios_get_power_modes(rdev);
1155 radeon_combios_get_power_modes(rdev);
1156 radeon_pm_print_states(rdev);
1157 radeon_pm_init_profile(rdev);
1158 /* set up the default clocks if the MC ucode is loaded */
1159 if ((rdev->family >= CHIP_BARTS) &&
1160 (rdev->family <= CHIP_CAYMAN) &&
1162 if (rdev->pm.default_vddc)
1163 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1164 SET_VOLTAGE_TYPE_ASIC_VDDC);
1165 if (rdev->pm.default_vddci)
1166 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1167 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1168 if (rdev->pm.default_sclk)
1169 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1170 if (rdev->pm.default_mclk)
1171 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1175 /* set up the internal thermal sensor if applicable */
1176 ret = radeon_hwmon_init(rdev);
1180 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1182 if (rdev->pm.num_power_states > 1) {
1183 /* where's the best place to put these? */
1184 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1186 DRM_ERROR("failed to create device file for power profile\n");
1187 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1189 DRM_ERROR("failed to create device file for power method\n");
1191 if (radeon_debugfs_pm_init(rdev)) {
1192 DRM_ERROR("Failed to register debugfs file for PM!\n");
1195 DRM_INFO("radeon: power management initialized\n");
1201 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1205 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1206 printk("== power state %d ==\n", i);
1207 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1211 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1215 /* default to balanced state */
1216 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1217 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1218 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1219 rdev->pm.default_sclk = rdev->clock.default_sclk;
1220 rdev->pm.default_mclk = rdev->clock.default_mclk;
1221 rdev->pm.current_sclk = rdev->clock.default_sclk;
1222 rdev->pm.current_mclk = rdev->clock.default_mclk;
1223 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1225 if (rdev->bios && rdev->is_atom_bios)
1226 radeon_atombios_get_power_modes(rdev);
1230 /* set up the internal thermal sensor if applicable */
1231 ret = radeon_hwmon_init(rdev);
1235 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1236 mutex_lock(&rdev->pm.mutex);
1237 radeon_dpm_init(rdev);
1238 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1239 if (radeon_dpm == 1)
1240 radeon_dpm_print_power_states(rdev);
1241 radeon_dpm_setup_asic(rdev);
1242 ret = radeon_dpm_enable(rdev);
1243 mutex_unlock(&rdev->pm.mutex);
1246 rdev->pm.dpm_enabled = true;
1248 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1250 DRM_ERROR("failed to create device file for dpm state\n");
1251 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1253 DRM_ERROR("failed to create device file for dpm state\n");
1254 /* XXX: these are noops for dpm but are here for backwards compat */
1255 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1257 DRM_ERROR("failed to create device file for power profile\n");
1258 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1260 DRM_ERROR("failed to create device file for power method\n");
1262 if (radeon_debugfs_pm_init(rdev)) {
1263 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1266 DRM_INFO("radeon: dpm initialized\n");
1271 rdev->pm.dpm_enabled = false;
1272 if ((rdev->family >= CHIP_BARTS) &&
1273 (rdev->family <= CHIP_CAYMAN) &&
1275 if (rdev->pm.default_vddc)
1276 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1277 SET_VOLTAGE_TYPE_ASIC_VDDC);
1278 if (rdev->pm.default_vddci)
1279 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1280 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1281 if (rdev->pm.default_sclk)
1282 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1283 if (rdev->pm.default_mclk)
1284 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1286 DRM_ERROR("radeon: dpm initialization failed\n");
1290 int radeon_pm_init(struct radeon_device *rdev)
1292 /* enable dpm on rv6xx+ */
1293 switch (rdev->family) {
1306 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1308 rdev->pm.pm_method = PM_METHOD_PROFILE;
1309 else if ((rdev->family >= CHIP_RV770) &&
1310 (!(rdev->flags & RADEON_IS_IGP)) &&
1312 rdev->pm.pm_method = PM_METHOD_PROFILE;
1313 else if (radeon_dpm == 1)
1314 rdev->pm.pm_method = PM_METHOD_DPM;
1316 rdev->pm.pm_method = PM_METHOD_PROFILE;
1340 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1342 rdev->pm.pm_method = PM_METHOD_PROFILE;
1343 else if ((rdev->family >= CHIP_RV770) &&
1344 (!(rdev->flags & RADEON_IS_IGP)) &&
1346 rdev->pm.pm_method = PM_METHOD_PROFILE;
1347 else if (radeon_dpm == 0)
1348 rdev->pm.pm_method = PM_METHOD_PROFILE;
1350 rdev->pm.pm_method = PM_METHOD_DPM;
1353 /* default to profile method */
1354 rdev->pm.pm_method = PM_METHOD_PROFILE;
1358 if (rdev->pm.pm_method == PM_METHOD_DPM)
1359 return radeon_pm_init_dpm(rdev);
1361 return radeon_pm_init_old(rdev);
1364 int radeon_pm_late_init(struct radeon_device *rdev)
1368 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1369 mutex_lock(&rdev->pm.mutex);
1370 ret = radeon_dpm_late_enable(rdev);
1371 mutex_unlock(&rdev->pm.mutex);
1376 static void radeon_pm_fini_old(struct radeon_device *rdev)
1378 if (rdev->pm.num_power_states > 1) {
1379 mutex_lock(&rdev->pm.mutex);
1380 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1381 rdev->pm.profile = PM_PROFILE_DEFAULT;
1382 radeon_pm_update_profile(rdev);
1383 radeon_pm_set_clocks(rdev);
1384 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1385 /* reset default clocks */
1386 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1387 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1388 radeon_pm_set_clocks(rdev);
1390 mutex_unlock(&rdev->pm.mutex);
1392 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1394 device_remove_file(rdev->dev, &dev_attr_power_profile);
1395 device_remove_file(rdev->dev, &dev_attr_power_method);
1398 radeon_hwmon_fini(rdev);
1400 if (rdev->pm.power_state)
1401 kfree(rdev->pm.power_state);
1404 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1406 if (rdev->pm.num_power_states > 1) {
1407 mutex_lock(&rdev->pm.mutex);
1408 radeon_dpm_disable(rdev);
1409 mutex_unlock(&rdev->pm.mutex);
1411 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1412 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1413 /* XXX backwards compat */
1414 device_remove_file(rdev->dev, &dev_attr_power_profile);
1415 device_remove_file(rdev->dev, &dev_attr_power_method);
1417 radeon_dpm_fini(rdev);
1419 radeon_hwmon_fini(rdev);
1421 if (rdev->pm.power_state)
1422 kfree(rdev->pm.power_state);
1425 void radeon_pm_fini(struct radeon_device *rdev)
1427 if (rdev->pm.pm_method == PM_METHOD_DPM)
1428 radeon_pm_fini_dpm(rdev);
1430 radeon_pm_fini_old(rdev);
1433 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1435 struct drm_device *ddev = rdev->ddev;
1436 struct drm_crtc *crtc;
1437 struct radeon_crtc *radeon_crtc;
1439 if (rdev->pm.num_power_states < 2)
1442 mutex_lock(&rdev->pm.mutex);
1444 rdev->pm.active_crtcs = 0;
1445 rdev->pm.active_crtc_count = 0;
1446 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1447 list_for_each_entry(crtc,
1448 &ddev->mode_config.crtc_list, head) {
1449 radeon_crtc = to_radeon_crtc(crtc);
1450 if (radeon_crtc->enabled) {
1451 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1452 rdev->pm.active_crtc_count++;
1457 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1458 radeon_pm_update_profile(rdev);
1459 radeon_pm_set_clocks(rdev);
1460 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1461 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1462 if (rdev->pm.active_crtc_count > 1) {
1463 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1464 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1466 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1467 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1468 radeon_pm_get_dynpm_state(rdev);
1469 radeon_pm_set_clocks(rdev);
1471 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1473 } else if (rdev->pm.active_crtc_count == 1) {
1474 /* TODO: Increase clocks if needed for current mode */
1476 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1477 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1478 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1479 radeon_pm_get_dynpm_state(rdev);
1480 radeon_pm_set_clocks(rdev);
1482 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1483 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1484 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1485 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1486 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1487 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1488 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1490 } else { /* count == 0 */
1491 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1492 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1494 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1495 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1496 radeon_pm_get_dynpm_state(rdev);
1497 radeon_pm_set_clocks(rdev);
1503 mutex_unlock(&rdev->pm.mutex);
1506 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1508 struct drm_device *ddev = rdev->ddev;
1509 struct drm_crtc *crtc;
1510 struct radeon_crtc *radeon_crtc;
1512 if (!rdev->pm.dpm_enabled)
1515 mutex_lock(&rdev->pm.mutex);
1517 /* update active crtc counts */
1518 rdev->pm.dpm.new_active_crtcs = 0;
1519 rdev->pm.dpm.new_active_crtc_count = 0;
1520 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1521 list_for_each_entry(crtc,
1522 &ddev->mode_config.crtc_list, head) {
1523 radeon_crtc = to_radeon_crtc(crtc);
1524 if (crtc->enabled) {
1525 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1526 rdev->pm.dpm.new_active_crtc_count++;
1531 /* update battery/ac status */
1532 if (power_supply_is_system_supplied() > 0)
1533 rdev->pm.dpm.ac_power = true;
1535 rdev->pm.dpm.ac_power = false;
1537 radeon_dpm_change_power_state_locked(rdev);
1539 mutex_unlock(&rdev->pm.mutex);
1543 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1545 if (rdev->pm.pm_method == PM_METHOD_DPM)
1546 radeon_pm_compute_clocks_dpm(rdev);
1548 radeon_pm_compute_clocks_old(rdev);
1551 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1553 int crtc, vpos, hpos, vbl_status;
1556 /* Iterate over all active crtc's. All crtc's must be in vblank,
1557 * otherwise return in_vbl == false.
1559 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1560 if (rdev->pm.active_crtcs & (1 << crtc)) {
1561 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1562 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1563 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1571 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1574 bool in_vbl = radeon_pm_in_vbl(rdev);
1576 if (in_vbl == false)
1577 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1578 finish ? "exit" : "entry");
1582 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1584 struct radeon_device *rdev;
1586 rdev = container_of(work, struct radeon_device,
1587 pm.dynpm_idle_work.work);
1589 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1590 mutex_lock(&rdev->pm.mutex);
1591 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1592 int not_processed = 0;
1595 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1596 struct radeon_ring *ring = &rdev->ring[i];
1599 not_processed += radeon_fence_count_emitted(rdev, i);
1600 if (not_processed >= 3)
1605 if (not_processed >= 3) { /* should upclock */
1606 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1607 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1608 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1609 rdev->pm.dynpm_can_upclock) {
1610 rdev->pm.dynpm_planned_action =
1611 DYNPM_ACTION_UPCLOCK;
1612 rdev->pm.dynpm_action_timeout = jiffies +
1613 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1615 } else if (not_processed == 0) { /* should downclock */
1616 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1617 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1618 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1619 rdev->pm.dynpm_can_downclock) {
1620 rdev->pm.dynpm_planned_action =
1621 DYNPM_ACTION_DOWNCLOCK;
1622 rdev->pm.dynpm_action_timeout = jiffies +
1623 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1627 /* Note, radeon_pm_set_clocks is called with static_switch set
1628 * to false since we want to wait for vbl to avoid flicker.
1630 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1631 jiffies > rdev->pm.dynpm_action_timeout) {
1632 radeon_pm_get_dynpm_state(rdev);
1633 radeon_pm_set_clocks(rdev);
1636 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1637 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1639 mutex_unlock(&rdev->pm.mutex);
1640 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1646 #if defined(CONFIG_DEBUG_FS)
1648 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1650 struct drm_info_node *node = (struct drm_info_node *) m->private;
1651 struct drm_device *dev = node->minor->dev;
1652 struct radeon_device *rdev = dev->dev_private;
1653 struct drm_device *ddev = rdev->ddev;
1655 if ((rdev->flags & RADEON_IS_PX) &&
1656 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1657 seq_printf(m, "PX asic powered off\n");
1658 } else if (rdev->pm.dpm_enabled) {
1659 mutex_lock(&rdev->pm.mutex);
1660 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1661 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1663 seq_printf(m, "Debugfs support not implemented for this asic\n");
1664 mutex_unlock(&rdev->pm.mutex);
1666 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1667 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1668 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1669 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1671 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1672 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1673 if (rdev->asic->pm.get_memory_clock)
1674 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1675 if (rdev->pm.current_vddc)
1676 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1677 if (rdev->asic->pm.get_pcie_lanes)
1678 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1684 static struct drm_info_list radeon_pm_info_list[] = {
1685 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1689 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1691 #if defined(CONFIG_DEBUG_FS)
1692 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));