drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34 #define RADEON_WAIT_IDLE_TIMEOUT 200
  35
  36 static const char *radeon_pm_state_type_name[5] = {
  37         "Default",
  38         "Powersave",
  39         "Battery",
  40         "Balanced",
  41         "Performance",
  42 };
  43
  44 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  45 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  46 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  48 static void radeon_pm_update_profile(struct radeon_device *rdev);
  49 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  50
  51 #define ACPI_AC_CLASS           "ac_adapter"
  52
  53 #ifdef CONFIG_ACPI
  54 static int radeon_acpi_event(struct notifier_block *nb,
  55                              unsigned long val,
  56                              void *data)
  57 {
  58         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  59         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  60
  61         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  62                 if (power_supply_is_system_supplied() > 0)
  63                         DRM_DEBUG("pm: AC\n");
  64                 else
  65                         DRM_DEBUG("pm: DC\n");
  66
  67                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  68                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  69                                 mutex_lock(&rdev->pm.mutex);
  70                                 radeon_pm_update_profile(rdev);
  71                                 radeon_pm_set_clocks(rdev);
  72                                 mutex_unlock(&rdev->pm.mutex);
  73                         }
  74                 }
  75         }
  76
  77         return NOTIFY_OK;
  78 }
  79 #endif
  80
  81 static void radeon_pm_update_profile(struct radeon_device *rdev)
  82 {
  83         switch (rdev->pm.profile) {
  84         case PM_PROFILE_DEFAULT:
  85                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  86                 break;
  87         case PM_PROFILE_AUTO:
  88                 if (power_supply_is_system_supplied() > 0) {
  89                         if (rdev->pm.active_crtc_count > 1)
  90                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  91                         else
  92                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  93                 } else {
  94                         if (rdev->pm.active_crtc_count > 1)
  95                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  96                         else
  97                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  98                 }
  99                 break;
 100         case PM_PROFILE_LOW:
 101                 if (rdev->pm.active_crtc_count > 1)
 102                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 103                 else
 104                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 105                 break;
 106         case PM_PROFILE_MID:
 107                 if (rdev->pm.active_crtc_count > 1)
 108                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 109                 else
 110                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 111                 break;
 112         case PM_PROFILE_HIGH:
 113                 if (rdev->pm.active_crtc_count > 1)
 114                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 115                 else
 116                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 117                 break;
 118         }
 119
 120         if (rdev->pm.active_crtc_count == 0) {
 121                 rdev->pm.requested_power_state_index =
 122                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 123                 rdev->pm.requested_clock_mode_index =
 124                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 125         } else {
 126                 rdev->pm.requested_power_state_index =
 127                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 128                 rdev->pm.requested_clock_mode_index =
 129                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 130         }
 131 }
 132
 133 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 134 {
 135         struct radeon_bo *bo, *n;
 136
 137         if (list_empty(&rdev->gem.objects))
 138                 return;
 139
 140         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 141                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 142                         ttm_bo_unmap_virtual(&bo->tbo);
 143         }
 144 }
 145
 146 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 147 {
 148         if (rdev->pm.active_crtcs) {
 149                 rdev->pm.vblank_sync = false;
 150                 wait_event_timeout(
 151                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 152                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 153         }
 154 }
 155
 156 static void radeon_set_power_state(struct radeon_device *rdev)
 157 {
 158         u32 sclk, mclk;
 159         bool misc_after = false;
 160
 161         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 162             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 163                 return;
 164
 165         if (radeon_gui_idle(rdev)) {
 166                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 167                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 168                 if (sclk > rdev->clock.default_sclk)
 169                         sclk = rdev->clock.default_sclk;
 170
 171                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 172                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 173                 if (mclk > rdev->clock.default_mclk)
 174                         mclk = rdev->clock.default_mclk;
 175
 176                 /* upvolt before raising clocks, downvolt after lowering clocks */
 177                 if (sclk < rdev->pm.current_sclk)
 178                         misc_after = true;
 179
 180                 radeon_sync_with_vblank(rdev);
 181
 182                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 183                         if (!radeon_pm_in_vbl(rdev))
 184                                 return;
 185                 }
 186
 187                 radeon_pm_prepare(rdev);
 188
 189                 if (!misc_after)
 190                         /* voltage, pcie lanes, etc.*/
 191                         radeon_pm_misc(rdev);
 192
 193                 /* set engine clock */
 194                 if (sclk != rdev->pm.current_sclk) {
 195                         radeon_pm_debug_check_in_vbl(rdev, false);
 196                         radeon_set_engine_clock(rdev, sclk);
 197                         radeon_pm_debug_check_in_vbl(rdev, true);
 198                         rdev->pm.current_sclk = sclk;
 199                         DRM_DEBUG("Setting: e: %d\n", sclk);
 200                 }
 201
 202                 /* set memory clock */
 203                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 204                         radeon_pm_debug_check_in_vbl(rdev, false);
 205                         radeon_set_memory_clock(rdev, mclk);
 206                         radeon_pm_debug_check_in_vbl(rdev, true);
 207                         rdev->pm.current_mclk = mclk;
 208                         DRM_DEBUG("Setting: m: %d\n", mclk);
 209                 }
 210
 211                 if (misc_after)
 212                         /* voltage, pcie lanes, etc.*/
 213                         radeon_pm_misc(rdev);
 214
 215                 radeon_pm_finish(rdev);
 216
 217                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 218                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 219         } else
 220                 DRM_DEBUG("pm: GUI not idle!!!\n");
 221 }
 222
 223 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 224 {
 225         int i;
 226
 227         /* no need to take locks, etc. if nothing's going to change */
 228         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 229             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 230                 return;
 231
 232         mutex_lock(&rdev->ddev->struct_mutex);
 233         mutex_lock(&rdev->vram_mutex);
 234         mutex_lock(&rdev->cp.mutex);
 235
 236         /* gui idle int has issues on older chips it seems */
 237         if (rdev->family >= CHIP_R600) {
 238                 if (rdev->irq.installed) {
 239                         /* wait for GPU idle */
 240                         rdev->pm.gui_idle = false;
 241                         rdev->irq.gui_idle = true;
 242                         radeon_irq_set(rdev);
 243                         wait_event_interruptible_timeout(
 244                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 245                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 246                         rdev->irq.gui_idle = false;
 247                         radeon_irq_set(rdev);
 248                 }
 249         } else {
 250                 if (rdev->cp.ready) {
 251                         struct radeon_fence *fence;
 252                         radeon_ring_alloc(rdev, 64);
 253                         radeon_fence_create(rdev, &fence);
 254                         radeon_fence_emit(rdev, fence);
 255                         radeon_ring_commit(rdev);
 256                         radeon_fence_wait(fence, false);
 257                         radeon_fence_unref(&fence);
 258                 }
 259         }
 260         radeon_unmap_vram_bos(rdev);
 261
 262         if (rdev->irq.installed) {
 263                 for (i = 0; i < rdev->num_crtc; i++) {
 264                         if (rdev->pm.active_crtcs & (1 << i)) {
 265                                 rdev->pm.req_vblank |= (1 << i);
 266                                 drm_vblank_get(rdev->ddev, i);
 267                         }
 268                 }
 269         }
 270
 271         radeon_set_power_state(rdev);
 272
 273         if (rdev->irq.installed) {
 274                 for (i = 0; i < rdev->num_crtc; i++) {
 275                         if (rdev->pm.req_vblank & (1 << i)) {
 276                                 rdev->pm.req_vblank &= ~(1 << i);
 277                                 drm_vblank_put(rdev->ddev, i);
 278                         }
 279                 }
 280         }
 281
 282         /* update display watermarks based on new power state */
 283         radeon_update_bandwidth_info(rdev);
 284         if (rdev->pm.active_crtc_count)
 285                 radeon_bandwidth_update(rdev);
 286
 287         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 288
 289         mutex_unlock(&rdev->cp.mutex);
 290         mutex_unlock(&rdev->vram_mutex);
 291         mutex_unlock(&rdev->ddev->struct_mutex);
 292 }
 293
 294 static void radeon_pm_print_states(struct radeon_device *rdev)
 295 {
 296         int i, j;
 297         struct radeon_power_state *power_state;
 298         struct radeon_pm_clock_info *clock_info;
 299
 300         DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
 301         for (i = 0; i < rdev->pm.num_power_states; i++) {
 302                 power_state = &rdev->pm.power_state[i];
 303                 DRM_DEBUG("State %d: %s\n", i,
 304                         radeon_pm_state_type_name[power_state->type]);
 305                 if (i == rdev->pm.default_power_state_index)
 306                         DRM_DEBUG("\tDefault");
 307                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 308                         DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 309                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 310                         DRM_DEBUG("\tSingle display only\n");
 311                 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 312                 for (j = 0; j < power_state->num_clock_modes; j++) {
 313                         clock_info = &(power_state->clock_info[j]);
 314                         if (rdev->flags & RADEON_IS_IGP)
 315                                 DRM_DEBUG("\t\t%d e: %d%s\n",
 316                                         j,
 317                                         clock_info->sclk * 10,
 318                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 319                         else
 320                                 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 321                                         j,
 322                                         clock_info->sclk * 10,
 323                                         clock_info->mclk * 10,
 324                                         clock_info->voltage.voltage,
 325                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 326                 }
 327         }
 328 }
 329
 330 static ssize_t radeon_get_pm_profile(struct device *dev,
 331                                      struct device_attribute *attr,
 332                                      char *buf)
 333 {
 334         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 335         struct radeon_device *rdev = ddev->dev_private;
 336         int cp = rdev->pm.profile;
 337
 338         return snprintf(buf, PAGE_SIZE, "%s\n",
 339                         (cp == PM_PROFILE_AUTO) ? "auto" :
 340                         (cp == PM_PROFILE_LOW) ? "low" :
 341                         (cp == PM_PROFILE_MID) ? "mid" :
 342                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 343 }
 344
 345 static ssize_t radeon_set_pm_profile(struct device *dev,
 346                                      struct device_attribute *attr,
 347                                      const char *buf,
 348                                      size_t count)
 349 {
 350         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 351         struct radeon_device *rdev = ddev->dev_private;
 352
 353         mutex_lock(&rdev->pm.mutex);
 354         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 355                 if (strncmp("default", buf, strlen("default")) == 0)
 356                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 357                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 358                         rdev->pm.profile = PM_PROFILE_AUTO;
 359                 else if (strncmp("low", buf, strlen("low")) == 0)
 360                         rdev->pm.profile = PM_PROFILE_LOW;
 361                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 362                         rdev->pm.profile = PM_PROFILE_MID;
 363                 else if (strncmp("high", buf, strlen("high")) == 0)
 364                         rdev->pm.profile = PM_PROFILE_HIGH;
 365                 else {
 366                         DRM_ERROR("invalid power profile!\n");
 367                         goto fail;
 368                 }
 369                 radeon_pm_update_profile(rdev);
 370                 radeon_pm_set_clocks(rdev);
 371         }
 372 fail:
 373         mutex_unlock(&rdev->pm.mutex);
 374
 375         return count;
 376 }
 377
 378 static ssize_t radeon_get_pm_method(struct device *dev,
 379                                     struct device_attribute *attr,
 380                                     char *buf)
 381 {
 382         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 383         struct radeon_device *rdev = ddev->dev_private;
 384         int pm = rdev->pm.pm_method;
 385
 386         return snprintf(buf, PAGE_SIZE, "%s\n",
 387                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 388 }
 389
 390 static ssize_t radeon_set_pm_method(struct device *dev,
 391                                     struct device_attribute *attr,
 392                                     const char *buf,
 393                                     size_t count)
 394 {
 395         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 396         struct radeon_device *rdev = ddev->dev_private;
 397
 398
 399         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 400                 mutex_lock(&rdev->pm.mutex);
 401                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 402                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 403                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 404                 mutex_unlock(&rdev->pm.mutex);
 405         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 406                 bool flush_wq = false;
 407
 408                 mutex_lock(&rdev->pm.mutex);
 409                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 410                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 411                         flush_wq = true;
 412                 }
 413                 /* disable dynpm */
 414                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 415                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 416                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 417                 mutex_unlock(&rdev->pm.mutex);
 418                 if (flush_wq)
 419                         flush_workqueue(rdev->wq);
 420         } else {
 421                 DRM_ERROR("invalid power method!\n");
 422                 goto fail;
 423         }
 424         radeon_pm_compute_clocks(rdev);
 425 fail:
 426         return count;
 427 }
 428
 429 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 430 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 431
 432 void radeon_pm_suspend(struct radeon_device *rdev)
 433 {
 434         bool flush_wq = false;
 435
 436         mutex_lock(&rdev->pm.mutex);
 437         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 438                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 439                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 440                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 441                 flush_wq = true;
 442         }
 443         mutex_unlock(&rdev->pm.mutex);
 444         if (flush_wq)
 445                 flush_workqueue(rdev->wq);
 446 }
 447
 448 void radeon_pm_resume(struct radeon_device *rdev)
 449 {
 450         /* asic init will reset the default power state */
 451         mutex_lock(&rdev->pm.mutex);
 452         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 453         rdev->pm.current_clock_mode_index = 0;
 454         rdev->pm.current_sclk = rdev->clock.default_sclk;
 455         rdev->pm.current_mclk = rdev->clock.default_mclk;
 456         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 457         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 458             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 459                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 460                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 461                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 462         }
 463         mutex_unlock(&rdev->pm.mutex);
 464         radeon_pm_compute_clocks(rdev);
 465 }
 466
 467 int radeon_pm_init(struct radeon_device *rdev)
 468 {
 469         int ret;
 470         /* default to profile method */
 471         rdev->pm.pm_method = PM_METHOD_PROFILE;
 472         rdev->pm.profile = PM_PROFILE_DEFAULT;
 473         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 474         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 475         rdev->pm.dynpm_can_upclock = true;
 476         rdev->pm.dynpm_can_downclock = true;
 477         rdev->pm.current_sclk = rdev->clock.default_sclk;
 478         rdev->pm.current_mclk = rdev->clock.default_mclk;
 479
 480         if (rdev->bios) {
 481                 if (rdev->is_atom_bios)
 482                         radeon_atombios_get_power_modes(rdev);
 483                 else
 484                         radeon_combios_get_power_modes(rdev);
 485                 radeon_pm_print_states(rdev);
 486                 radeon_pm_init_profile(rdev);
 487         }
 488
 489         if (rdev->pm.num_power_states > 1) {
 490                 /* where's the best place to put these? */
 491                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 492                 if (ret)
 493                         DRM_ERROR("failed to create device file for power profile\n");
 494                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 495                 if (ret)
 496                         DRM_ERROR("failed to create device file for power method\n");
 497
 498 #ifdef CONFIG_ACPI
 499                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 500                 register_acpi_notifier(&rdev->acpi_nb);
 501 #endif
 502                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 503
 504                 if (radeon_debugfs_pm_init(rdev)) {
 505                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 506                 }
 507
 508                 DRM_INFO("radeon: power management initialized\n");
 509         }
 510
 511         return 0;
 512 }
 513
 514 void radeon_pm_fini(struct radeon_device *rdev)
 515 {
 516         if (rdev->pm.num_power_states > 1) {
 517                 bool flush_wq = false;
 518
 519                 mutex_lock(&rdev->pm.mutex);
 520                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 521                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 522                         radeon_pm_update_profile(rdev);
 523                         radeon_pm_set_clocks(rdev);
 524                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 525                         /* cancel work */
 526                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 527                         flush_wq = true;
 528                         /* reset default clocks */
 529                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 530                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 531                         radeon_pm_set_clocks(rdev);
 532                 }
 533                 mutex_unlock(&rdev->pm.mutex);
 534                 if (flush_wq)
 535                         flush_workqueue(rdev->wq);
 536
 537                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 538                 device_remove_file(rdev->dev, &dev_attr_power_method);
 539 #ifdef CONFIG_ACPI
 540                 unregister_acpi_notifier(&rdev->acpi_nb);
 541 #endif
 542         }
 543
 544         if (rdev->pm.i2c_bus)
 545                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 546 }
 547
 548 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 549 {
 550         struct drm_device *ddev = rdev->ddev;
 551         struct drm_crtc *crtc;
 552         struct radeon_crtc *radeon_crtc;
 553
 554         if (rdev->pm.num_power_states < 2)
 555                 return;
 556
 557         mutex_lock(&rdev->pm.mutex);
 558
 559         rdev->pm.active_crtcs = 0;
 560         rdev->pm.active_crtc_count = 0;
 561         list_for_each_entry(crtc,
 562                 &ddev->mode_config.crtc_list, head) {
 563                 radeon_crtc = to_radeon_crtc(crtc);
 564                 if (radeon_crtc->enabled) {
 565                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 566                         rdev->pm.active_crtc_count++;
 567                 }
 568         }
 569
 570         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 571                 radeon_pm_update_profile(rdev);
 572                 radeon_pm_set_clocks(rdev);
 573         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 574                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 575                         if (rdev->pm.active_crtc_count > 1) {
 576                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 577                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 578
 579                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 580                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 581                                         radeon_pm_get_dynpm_state(rdev);
 582                                         radeon_pm_set_clocks(rdev);
 583
 584                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 585                                 }
 586                         } else if (rdev->pm.active_crtc_count == 1) {
 587                                 /* TODO: Increase clocks if needed for current mode */
 588
 589                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 590                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 591                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 592                                         radeon_pm_get_dynpm_state(rdev);
 593                                         radeon_pm_set_clocks(rdev);
 594
 595                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 596                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 597                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 598                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 599                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 600                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 601                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 602                                 }
 603                         } else { /* count == 0 */
 604                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 605                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 606
 607                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 608                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 609                                         radeon_pm_get_dynpm_state(rdev);
 610                                         radeon_pm_set_clocks(rdev);
 611                                 }
 612                         }
 613                 }
 614         }
 615
 616         mutex_unlock(&rdev->pm.mutex);
 617 }
 618
 619 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 620 {
 621         u32 stat_crtc = 0, vbl = 0, position = 0;
 622         bool in_vbl = true;
 623
 624         if (ASIC_IS_DCE4(rdev)) {
 625                 if (rdev->pm.active_crtcs & (1 << 0)) {
 626                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 627                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 628                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 629                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 630                 }
 631                 if (rdev->pm.active_crtcs & (1 << 1)) {
 632                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 633                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 634                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 635                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 636                 }
 637                 if (rdev->pm.active_crtcs & (1 << 2)) {
 638                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 639                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 640                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 641                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 642                 }
 643                 if (rdev->pm.active_crtcs & (1 << 3)) {
 644                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 645                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 646                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 647                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 648                 }
 649                 if (rdev->pm.active_crtcs & (1 << 4)) {
 650                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 651                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 652                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 653                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 654                 }
 655                 if (rdev->pm.active_crtcs & (1 << 5)) {
 656                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 657                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 658                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 659                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 660                 }
 661         } else if (ASIC_IS_AVIVO(rdev)) {
 662                 if (rdev->pm.active_crtcs & (1 << 0)) {
 663                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 664                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 665                 }
 666                 if (rdev->pm.active_crtcs & (1 << 1)) {
 667                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 668                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 669                 }
 670                 if (position < vbl && position > 1)
 671                         in_vbl = false;
 672         } else {
 673                 if (rdev->pm.active_crtcs & (1 << 0)) {
 674                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 675                         if (!(stat_crtc & 1))
 676                                 in_vbl = false;
 677                 }
 678                 if (rdev->pm.active_crtcs & (1 << 1)) {
 679                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 680                         if (!(stat_crtc & 1))
 681                                 in_vbl = false;
 682                 }
 683         }
 684
 685         if (position < vbl && position > 1)
 686                 in_vbl = false;
 687
 688         return in_vbl;
 689 }
 690
 691 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 692 {
 693         u32 stat_crtc = 0;
 694         bool in_vbl = radeon_pm_in_vbl(rdev);
 695
 696         if (in_vbl == false)
 697                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 698                          finish ? "exit" : "entry");
 699         return in_vbl;
 700 }
 701
 702 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 703 {
 704         struct radeon_device *rdev;
 705         int resched;
 706         rdev = container_of(work, struct radeon_device,
 707                                 pm.dynpm_idle_work.work);
 708
 709         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 710         mutex_lock(&rdev->pm.mutex);
 711         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 712                 unsigned long irq_flags;
 713                 int not_processed = 0;
 714
 715                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 716                 if (!list_empty(&rdev->fence_drv.emited)) {
 717                         struct list_head *ptr;
 718                         list_for_each(ptr, &rdev->fence_drv.emited) {
 719                                 /* count up to 3, that's enought info */
 720                                 if (++not_processed >= 3)
 721                                         break;
 722                         }
 723                 }
 724                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 725
 726                 if (not_processed >= 3) { /* should upclock */
 727                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 728                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 729                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 730                                    rdev->pm.dynpm_can_upclock) {
 731                                 rdev->pm.dynpm_planned_action =
 732                                         DYNPM_ACTION_UPCLOCK;
 733                                 rdev->pm.dynpm_action_timeout = jiffies +
 734                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 735                         }
 736                 } else if (not_processed == 0) { /* should downclock */
 737                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 738                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 739                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 740                                    rdev->pm.dynpm_can_downclock) {
 741                                 rdev->pm.dynpm_planned_action =
 742                                         DYNPM_ACTION_DOWNCLOCK;
 743                                 rdev->pm.dynpm_action_timeout = jiffies +
 744                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 745                         }
 746                 }
 747
 748                 /* Note, radeon_pm_set_clocks is called with static_switch set
 749                  * to false since we want to wait for vbl to avoid flicker.
 750                  */
 751                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 752                     jiffies > rdev->pm.dynpm_action_timeout) {
 753                         radeon_pm_get_dynpm_state(rdev);
 754                         radeon_pm_set_clocks(rdev);
 755                 }
 756
 757                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 758                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 759         }
 760         mutex_unlock(&rdev->pm.mutex);
 761         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 762 }
 763
 764 /*
 765  * Debugfs info
 766  */
 767 #if defined(CONFIG_DEBUG_FS)
 768
 769 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 770 {
 771         struct drm_info_node *node = (struct drm_info_node *) m->private;
 772         struct drm_device *dev = node->minor->dev;
 773         struct radeon_device *rdev = dev->dev_private;
 774
 775         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 776         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 777         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 778         if (rdev->asic->get_memory_clock)
 779                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 780         if (rdev->pm.current_vddc)
 781                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 782         if (rdev->asic->get_pcie_lanes)
 783                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 784
 785         return 0;
 786 }
 787
 788 static struct drm_info_list radeon_pm_info_list[] = {
 789         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 790 };
 791 #endif
 792
 793 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 794 {
 795 #if defined(CONFIG_DEBUG_FS)
 796         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 797 #else
 798         return 0;
 799 #endif
 800 }