2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
55 int found_instance = -1;
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
60 if (found_instance == instance)
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
80 static void radeon_pm_update_profile(struct radeon_device *rdev)
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
93 if (rdev->pm.active_crtc_count > 1)
94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
134 struct radeon_bo *bo, *n;
136 if (list_empty(&rdev->gem.objects))
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 static void radeon_set_power_state(struct radeon_device *rdev)
158 bool misc_after = false;
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
192 radeon_sync_with_vblank(rdev);
194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
195 if (!radeon_pm_in_vbl(rdev))
199 radeon_pm_prepare(rdev);
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
214 /* set memory clock */
215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
227 radeon_pm_finish(rdev);
229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
244 mutex_lock(&rdev->ddev->struct_mutex);
245 down_write(&rdev->pm.mclk_lock);
246 mutex_lock(&rdev->ring_lock);
248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
254 r = radeon_fence_wait_empty_locked(rdev, i);
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
264 radeon_unmap_vram_bos(rdev);
266 if (rdev->irq.installed) {
267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
275 radeon_set_power_state(rdev);
277 if (rdev->irq.installed) {
278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
293 mutex_unlock(&rdev->ring_lock);
294 up_write(&rdev->pm.mclk_lock);
295 mutex_unlock(&rdev->ddev->struct_mutex);
298 static void radeon_pm_print_states(struct radeon_device *rdev)
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
310 DRM_DEBUG_DRIVER("\tDefault");
311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
321 clock_info->sclk * 10);
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
332 static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
338 int cp = rdev->pm.profile;
340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
343 (cp == PM_PROFILE_MID) ? "mid" :
344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
347 static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
355 mutex_lock(&rdev->pm.mutex);
356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
377 mutex_unlock(&rdev->pm.mutex);
382 static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
388 int pm = rdev->pm.pm_method;
390 return snprintf(buf, PAGE_SIZE, "%s\n",
391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
395 static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
410 mutex_lock(&rdev->pm.mutex);
411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
414 mutex_unlock(&rdev->pm.mutex);
415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
420 rdev->pm.pm_method = PM_METHOD_PROFILE;
421 mutex_unlock(&rdev->pm.mutex);
422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
427 radeon_pm_compute_clocks(rdev);
432 static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
445 static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
461 mutex_unlock(&rdev->pm.mutex);
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
471 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
472 struct device_attribute *attr,
475 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
476 struct radeon_device *rdev = ddev->dev_private;
477 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
479 return snprintf(buf, PAGE_SIZE, "%s\n",
480 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
481 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
484 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
485 struct device_attribute *attr,
489 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
490 struct radeon_device *rdev = ddev->dev_private;
491 enum radeon_dpm_forced_level level;
494 mutex_lock(&rdev->pm.mutex);
495 if (strncmp("low", buf, strlen("low")) == 0) {
496 level = RADEON_DPM_FORCED_LEVEL_LOW;
497 } else if (strncmp("high", buf, strlen("high")) == 0) {
498 level = RADEON_DPM_FORCED_LEVEL_HIGH;
499 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
500 level = RADEON_DPM_FORCED_LEVEL_AUTO;
502 mutex_unlock(&rdev->pm.mutex);
506 if (rdev->asic->dpm.force_performance_level) {
507 ret = radeon_dpm_force_performance_level(rdev, level);
511 mutex_unlock(&rdev->pm.mutex);
516 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
517 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
518 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
519 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
520 radeon_get_dpm_forced_performance_level,
521 radeon_set_dpm_forced_performance_level);
523 static ssize_t radeon_hwmon_show_temp(struct device *dev,
524 struct device_attribute *attr,
527 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
528 struct radeon_device *rdev = ddev->dev_private;
531 if (rdev->asic->pm.get_temperature)
532 temp = radeon_get_temperature(rdev);
536 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
539 static ssize_t radeon_hwmon_show_name(struct device *dev,
540 struct device_attribute *attr,
543 return sprintf(buf, "radeon\n");
546 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
547 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
549 static struct attribute *hwmon_attributes[] = {
550 &sensor_dev_attr_temp1_input.dev_attr.attr,
551 &sensor_dev_attr_name.dev_attr.attr,
555 static const struct attribute_group hwmon_attrgroup = {
556 .attrs = hwmon_attributes,
559 static int radeon_hwmon_init(struct radeon_device *rdev)
563 rdev->pm.int_hwmon_dev = NULL;
565 switch (rdev->pm.int_thermal_type) {
566 case THERMAL_TYPE_RV6XX:
567 case THERMAL_TYPE_RV770:
568 case THERMAL_TYPE_EVERGREEN:
569 case THERMAL_TYPE_NI:
570 case THERMAL_TYPE_SUMO:
571 case THERMAL_TYPE_SI:
572 case THERMAL_TYPE_CI:
573 case THERMAL_TYPE_KV:
574 if (rdev->asic->pm.get_temperature == NULL)
576 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
577 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
578 err = PTR_ERR(rdev->pm.int_hwmon_dev);
580 "Unable to register hwmon device: %d\n", err);
583 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
584 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
588 "Unable to create hwmon sysfs file: %d\n", err);
589 hwmon_device_unregister(rdev->dev);
599 static void radeon_hwmon_fini(struct radeon_device *rdev)
601 if (rdev->pm.int_hwmon_dev) {
602 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
603 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
607 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
609 struct radeon_device *rdev =
610 container_of(work, struct radeon_device,
611 pm.dpm.thermal.work);
612 /* switch to the thermal state */
613 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
615 if (!rdev->pm.dpm_enabled)
618 if (rdev->asic->pm.get_temperature) {
619 int temp = radeon_get_temperature(rdev);
621 if (temp < rdev->pm.dpm.thermal.min_temp)
622 /* switch back the user state */
623 dpm_state = rdev->pm.dpm.user_state;
625 if (rdev->pm.dpm.thermal.high_to_low)
626 /* switch back the user state */
627 dpm_state = rdev->pm.dpm.user_state;
629 mutex_lock(&rdev->pm.mutex);
630 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
631 rdev->pm.dpm.thermal_active = true;
633 rdev->pm.dpm.thermal_active = false;
634 rdev->pm.dpm.state = dpm_state;
635 mutex_unlock(&rdev->pm.mutex);
637 radeon_pm_compute_clocks(rdev);
640 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
641 enum radeon_pm_state_type dpm_state)
644 struct radeon_ps *ps;
646 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
649 /* check if the vblank period is too short to adjust the mclk */
650 if (single_display && rdev->asic->dpm.vblank_too_short) {
651 if (radeon_dpm_vblank_too_short(rdev))
652 single_display = false;
655 /* certain older asics have a separare 3D performance state,
656 * so try that first if the user selected performance
658 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
659 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
660 /* balanced states don't exist at the moment */
661 if (dpm_state == POWER_STATE_TYPE_BALANCED)
662 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
665 /* Pick the best power state based on current conditions */
666 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
667 ps = &rdev->pm.dpm.ps[i];
668 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
671 case POWER_STATE_TYPE_BATTERY:
672 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
673 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
680 case POWER_STATE_TYPE_BALANCED:
681 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
682 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
689 case POWER_STATE_TYPE_PERFORMANCE:
690 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
691 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
698 /* internal states */
699 case POWER_STATE_TYPE_INTERNAL_UVD:
700 if (rdev->pm.dpm.uvd_ps)
701 return rdev->pm.dpm.uvd_ps;
704 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
705 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
708 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
709 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
712 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
713 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
716 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
717 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
720 case POWER_STATE_TYPE_INTERNAL_BOOT:
721 return rdev->pm.dpm.boot_ps;
722 case POWER_STATE_TYPE_INTERNAL_THERMAL:
723 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
726 case POWER_STATE_TYPE_INTERNAL_ACPI:
727 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
730 case POWER_STATE_TYPE_INTERNAL_ULV:
731 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
734 case POWER_STATE_TYPE_INTERNAL_3DPERF:
735 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
742 /* use a fallback state if we didn't match */
744 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
745 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
747 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
748 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
749 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
750 if (rdev->pm.dpm.uvd_ps) {
751 return rdev->pm.dpm.uvd_ps;
753 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
756 case POWER_STATE_TYPE_INTERNAL_THERMAL:
757 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
759 case POWER_STATE_TYPE_INTERNAL_ACPI:
760 dpm_state = POWER_STATE_TYPE_BATTERY;
762 case POWER_STATE_TYPE_BATTERY:
763 case POWER_STATE_TYPE_BALANCED:
764 case POWER_STATE_TYPE_INTERNAL_3DPERF:
765 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
774 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
777 struct radeon_ps *ps;
778 enum radeon_pm_state_type dpm_state;
781 /* if dpm init failed */
782 if (!rdev->pm.dpm_enabled)
785 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
786 /* add other state override checks here */
787 if ((!rdev->pm.dpm.thermal_active) &&
788 (!rdev->pm.dpm.uvd_active))
789 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
791 dpm_state = rdev->pm.dpm.state;
793 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
795 rdev->pm.dpm.requested_ps = ps;
799 /* no need to reprogram if nothing changed unless we are on BTC+ */
800 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
801 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
802 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
803 * all we need to do is update the display configuration.
805 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
806 /* update display watermarks based on new power state */
807 radeon_bandwidth_update(rdev);
808 /* update displays */
809 radeon_dpm_display_configuration_changed(rdev);
810 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
811 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
815 /* for BTC+ if the num crtcs hasn't changed and state is the same,
816 * nothing to do, if the num crtcs is > 1 and state is the same,
817 * update display configuration.
819 if (rdev->pm.dpm.new_active_crtcs ==
820 rdev->pm.dpm.current_active_crtcs) {
823 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
824 (rdev->pm.dpm.new_active_crtc_count > 1)) {
825 /* update display watermarks based on new power state */
826 radeon_bandwidth_update(rdev);
827 /* update displays */
828 radeon_dpm_display_configuration_changed(rdev);
829 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
830 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
837 printk("switching from power state:\n");
838 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
839 printk("switching to power state:\n");
840 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
842 mutex_lock(&rdev->ddev->struct_mutex);
843 down_write(&rdev->pm.mclk_lock);
844 mutex_lock(&rdev->ring_lock);
846 ret = radeon_dpm_pre_set_power_state(rdev);
850 /* update display watermarks based on new power state */
851 radeon_bandwidth_update(rdev);
852 /* update displays */
853 radeon_dpm_display_configuration_changed(rdev);
855 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
856 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
858 /* wait for the rings to drain */
859 for (i = 0; i < RADEON_NUM_RINGS; i++) {
860 struct radeon_ring *ring = &rdev->ring[i];
862 radeon_fence_wait_empty_locked(rdev, i);
865 /* program the new power state */
866 radeon_dpm_set_power_state(rdev);
868 /* update current power state */
869 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
871 radeon_dpm_post_set_power_state(rdev);
873 /* force low perf level for thermal */
874 if (rdev->pm.dpm.thermal_active &&
875 rdev->asic->dpm.force_performance_level) {
876 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
880 mutex_unlock(&rdev->ring_lock);
881 up_write(&rdev->pm.mclk_lock);
882 mutex_unlock(&rdev->ddev->struct_mutex);
885 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
887 enum radeon_pm_state_type dpm_state;
889 if (rdev->asic->dpm.powergate_uvd) {
890 mutex_lock(&rdev->pm.mutex);
891 /* enable/disable UVD */
892 radeon_dpm_powergate_uvd(rdev, !enable);
893 mutex_unlock(&rdev->pm.mutex);
896 mutex_lock(&rdev->pm.mutex);
897 rdev->pm.dpm.uvd_active = true;
898 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
899 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
900 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
901 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
902 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
903 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
904 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
905 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
907 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
908 rdev->pm.dpm.state = dpm_state;
909 mutex_unlock(&rdev->pm.mutex);
911 mutex_lock(&rdev->pm.mutex);
912 rdev->pm.dpm.uvd_active = false;
913 mutex_unlock(&rdev->pm.mutex);
916 radeon_pm_compute_clocks(rdev);
920 static void radeon_pm_suspend_old(struct radeon_device *rdev)
922 mutex_lock(&rdev->pm.mutex);
923 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
924 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
925 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
927 mutex_unlock(&rdev->pm.mutex);
929 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
932 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
934 mutex_lock(&rdev->pm.mutex);
936 radeon_dpm_disable(rdev);
937 /* reset the power state */
938 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
939 rdev->pm.dpm_enabled = false;
940 mutex_unlock(&rdev->pm.mutex);
943 void radeon_pm_suspend(struct radeon_device *rdev)
945 if (rdev->pm.pm_method == PM_METHOD_DPM)
946 radeon_pm_suspend_dpm(rdev);
948 radeon_pm_suspend_old(rdev);
951 static void radeon_pm_resume_old(struct radeon_device *rdev)
953 /* set up the default clocks if the MC ucode is loaded */
954 if ((rdev->family >= CHIP_BARTS) &&
955 (rdev->family <= CHIP_HAINAN) &&
957 if (rdev->pm.default_vddc)
958 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
959 SET_VOLTAGE_TYPE_ASIC_VDDC);
960 if (rdev->pm.default_vddci)
961 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
962 SET_VOLTAGE_TYPE_ASIC_VDDCI);
963 if (rdev->pm.default_sclk)
964 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
965 if (rdev->pm.default_mclk)
966 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
968 /* asic init will reset the default power state */
969 mutex_lock(&rdev->pm.mutex);
970 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
971 rdev->pm.current_clock_mode_index = 0;
972 rdev->pm.current_sclk = rdev->pm.default_sclk;
973 rdev->pm.current_mclk = rdev->pm.default_mclk;
974 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
975 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
976 if (rdev->pm.pm_method == PM_METHOD_DYNPM
977 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
978 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
979 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
980 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
982 mutex_unlock(&rdev->pm.mutex);
983 radeon_pm_compute_clocks(rdev);
986 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
990 /* asic init will reset to the boot state */
991 mutex_lock(&rdev->pm.mutex);
992 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
993 radeon_dpm_setup_asic(rdev);
994 ret = radeon_dpm_enable(rdev);
995 mutex_unlock(&rdev->pm.mutex);
997 DRM_ERROR("radeon: dpm resume failed\n");
998 if ((rdev->family >= CHIP_BARTS) &&
999 (rdev->family <= CHIP_HAINAN) &&
1001 if (rdev->pm.default_vddc)
1002 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1003 SET_VOLTAGE_TYPE_ASIC_VDDC);
1004 if (rdev->pm.default_vddci)
1005 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1006 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1007 if (rdev->pm.default_sclk)
1008 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1009 if (rdev->pm.default_mclk)
1010 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1013 rdev->pm.dpm_enabled = true;
1014 radeon_pm_compute_clocks(rdev);
1018 void radeon_pm_resume(struct radeon_device *rdev)
1020 if (rdev->pm.pm_method == PM_METHOD_DPM)
1021 radeon_pm_resume_dpm(rdev);
1023 radeon_pm_resume_old(rdev);
1026 static int radeon_pm_init_old(struct radeon_device *rdev)
1030 rdev->pm.profile = PM_PROFILE_DEFAULT;
1031 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1032 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1033 rdev->pm.dynpm_can_upclock = true;
1034 rdev->pm.dynpm_can_downclock = true;
1035 rdev->pm.default_sclk = rdev->clock.default_sclk;
1036 rdev->pm.default_mclk = rdev->clock.default_mclk;
1037 rdev->pm.current_sclk = rdev->clock.default_sclk;
1038 rdev->pm.current_mclk = rdev->clock.default_mclk;
1039 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1042 if (rdev->is_atom_bios)
1043 radeon_atombios_get_power_modes(rdev);
1045 radeon_combios_get_power_modes(rdev);
1046 radeon_pm_print_states(rdev);
1047 radeon_pm_init_profile(rdev);
1048 /* set up the default clocks if the MC ucode is loaded */
1049 if ((rdev->family >= CHIP_BARTS) &&
1050 (rdev->family <= CHIP_HAINAN) &&
1052 if (rdev->pm.default_vddc)
1053 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1054 SET_VOLTAGE_TYPE_ASIC_VDDC);
1055 if (rdev->pm.default_vddci)
1056 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1057 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1058 if (rdev->pm.default_sclk)
1059 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1060 if (rdev->pm.default_mclk)
1061 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1065 /* set up the internal thermal sensor if applicable */
1066 ret = radeon_hwmon_init(rdev);
1070 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1072 if (rdev->pm.num_power_states > 1) {
1073 /* where's the best place to put these? */
1074 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1076 DRM_ERROR("failed to create device file for power profile\n");
1077 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1079 DRM_ERROR("failed to create device file for power method\n");
1081 if (radeon_debugfs_pm_init(rdev)) {
1082 DRM_ERROR("Failed to register debugfs file for PM!\n");
1085 DRM_INFO("radeon: power management initialized\n");
1091 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1095 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1096 printk("== power state %d ==\n", i);
1097 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1101 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1105 /* default to performance state */
1106 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1107 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1108 rdev->pm.default_sclk = rdev->clock.default_sclk;
1109 rdev->pm.default_mclk = rdev->clock.default_mclk;
1110 rdev->pm.current_sclk = rdev->clock.default_sclk;
1111 rdev->pm.current_mclk = rdev->clock.default_mclk;
1112 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1114 if (rdev->bios && rdev->is_atom_bios)
1115 radeon_atombios_get_power_modes(rdev);
1119 /* set up the internal thermal sensor if applicable */
1120 ret = radeon_hwmon_init(rdev);
1124 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1125 mutex_lock(&rdev->pm.mutex);
1126 radeon_dpm_init(rdev);
1127 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1128 radeon_dpm_print_power_states(rdev);
1129 radeon_dpm_setup_asic(rdev);
1130 ret = radeon_dpm_enable(rdev);
1131 mutex_unlock(&rdev->pm.mutex);
1133 rdev->pm.dpm_enabled = false;
1134 if ((rdev->family >= CHIP_BARTS) &&
1135 (rdev->family <= CHIP_HAINAN) &&
1137 if (rdev->pm.default_vddc)
1138 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1139 SET_VOLTAGE_TYPE_ASIC_VDDC);
1140 if (rdev->pm.default_vddci)
1141 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1142 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1143 if (rdev->pm.default_sclk)
1144 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1145 if (rdev->pm.default_mclk)
1146 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1148 DRM_ERROR("radeon: dpm initialization failed\n");
1151 rdev->pm.dpm_enabled = true;
1152 radeon_pm_compute_clocks(rdev);
1154 if (rdev->pm.num_power_states > 1) {
1155 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1157 DRM_ERROR("failed to create device file for dpm state\n");
1158 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1160 DRM_ERROR("failed to create device file for dpm state\n");
1161 /* XXX: these are noops for dpm but are here for backwards compat */
1162 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1164 DRM_ERROR("failed to create device file for power profile\n");
1165 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1167 DRM_ERROR("failed to create device file for power method\n");
1169 if (radeon_debugfs_pm_init(rdev)) {
1170 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1173 DRM_INFO("radeon: dpm initialized\n");
1179 int radeon_pm_init(struct radeon_device *rdev)
1181 /* enable dpm on rv6xx+ */
1182 switch (rdev->family) {
1215 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1217 rdev->pm.pm_method = PM_METHOD_PROFILE;
1218 else if ((rdev->family >= CHIP_RV770) &&
1219 (!(rdev->flags & RADEON_IS_IGP)) &&
1221 rdev->pm.pm_method = PM_METHOD_PROFILE;
1222 else if (radeon_dpm == 1)
1223 rdev->pm.pm_method = PM_METHOD_DPM;
1225 rdev->pm.pm_method = PM_METHOD_PROFILE;
1228 /* default to profile method */
1229 rdev->pm.pm_method = PM_METHOD_PROFILE;
1233 if (rdev->pm.pm_method == PM_METHOD_DPM)
1234 return radeon_pm_init_dpm(rdev);
1236 return radeon_pm_init_old(rdev);
1239 static void radeon_pm_fini_old(struct radeon_device *rdev)
1241 if (rdev->pm.num_power_states > 1) {
1242 mutex_lock(&rdev->pm.mutex);
1243 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1244 rdev->pm.profile = PM_PROFILE_DEFAULT;
1245 radeon_pm_update_profile(rdev);
1246 radeon_pm_set_clocks(rdev);
1247 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1248 /* reset default clocks */
1249 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1250 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1251 radeon_pm_set_clocks(rdev);
1253 mutex_unlock(&rdev->pm.mutex);
1255 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1257 device_remove_file(rdev->dev, &dev_attr_power_profile);
1258 device_remove_file(rdev->dev, &dev_attr_power_method);
1261 if (rdev->pm.power_state)
1262 kfree(rdev->pm.power_state);
1264 radeon_hwmon_fini(rdev);
1267 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1269 if (rdev->pm.num_power_states > 1) {
1270 mutex_lock(&rdev->pm.mutex);
1271 radeon_dpm_disable(rdev);
1272 mutex_unlock(&rdev->pm.mutex);
1274 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1275 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1276 /* XXX backwards compat */
1277 device_remove_file(rdev->dev, &dev_attr_power_profile);
1278 device_remove_file(rdev->dev, &dev_attr_power_method);
1280 radeon_dpm_fini(rdev);
1282 if (rdev->pm.power_state)
1283 kfree(rdev->pm.power_state);
1285 radeon_hwmon_fini(rdev);
1288 void radeon_pm_fini(struct radeon_device *rdev)
1290 if (rdev->pm.pm_method == PM_METHOD_DPM)
1291 radeon_pm_fini_dpm(rdev);
1293 radeon_pm_fini_old(rdev);
1296 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1298 struct drm_device *ddev = rdev->ddev;
1299 struct drm_crtc *crtc;
1300 struct radeon_crtc *radeon_crtc;
1302 if (rdev->pm.num_power_states < 2)
1305 mutex_lock(&rdev->pm.mutex);
1307 rdev->pm.active_crtcs = 0;
1308 rdev->pm.active_crtc_count = 0;
1309 list_for_each_entry(crtc,
1310 &ddev->mode_config.crtc_list, head) {
1311 radeon_crtc = to_radeon_crtc(crtc);
1312 if (radeon_crtc->enabled) {
1313 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1314 rdev->pm.active_crtc_count++;
1318 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1319 radeon_pm_update_profile(rdev);
1320 radeon_pm_set_clocks(rdev);
1321 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1322 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1323 if (rdev->pm.active_crtc_count > 1) {
1324 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1325 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1327 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1328 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1329 radeon_pm_get_dynpm_state(rdev);
1330 radeon_pm_set_clocks(rdev);
1332 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1334 } else if (rdev->pm.active_crtc_count == 1) {
1335 /* TODO: Increase clocks if needed for current mode */
1337 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1338 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1339 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1340 radeon_pm_get_dynpm_state(rdev);
1341 radeon_pm_set_clocks(rdev);
1343 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1344 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1345 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1346 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1347 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1348 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1349 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1351 } else { /* count == 0 */
1352 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1353 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1355 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1356 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1357 radeon_pm_get_dynpm_state(rdev);
1358 radeon_pm_set_clocks(rdev);
1364 mutex_unlock(&rdev->pm.mutex);
1367 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1369 struct drm_device *ddev = rdev->ddev;
1370 struct drm_crtc *crtc;
1371 struct radeon_crtc *radeon_crtc;
1373 mutex_lock(&rdev->pm.mutex);
1375 /* update active crtc counts */
1376 rdev->pm.dpm.new_active_crtcs = 0;
1377 rdev->pm.dpm.new_active_crtc_count = 0;
1378 list_for_each_entry(crtc,
1379 &ddev->mode_config.crtc_list, head) {
1380 radeon_crtc = to_radeon_crtc(crtc);
1381 if (crtc->enabled) {
1382 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1383 rdev->pm.dpm.new_active_crtc_count++;
1387 /* update battery/ac status */
1388 if (power_supply_is_system_supplied() > 0)
1389 rdev->pm.dpm.ac_power = true;
1391 rdev->pm.dpm.ac_power = false;
1393 radeon_dpm_change_power_state_locked(rdev);
1395 mutex_unlock(&rdev->pm.mutex);
1399 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1401 if (rdev->pm.pm_method == PM_METHOD_DPM)
1402 radeon_pm_compute_clocks_dpm(rdev);
1404 radeon_pm_compute_clocks_old(rdev);
1407 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1409 int crtc, vpos, hpos, vbl_status;
1412 /* Iterate over all active crtc's. All crtc's must be in vblank,
1413 * otherwise return in_vbl == false.
1415 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1416 if (rdev->pm.active_crtcs & (1 << crtc)) {
1417 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1418 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1419 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1427 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1430 bool in_vbl = radeon_pm_in_vbl(rdev);
1432 if (in_vbl == false)
1433 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1434 finish ? "exit" : "entry");
1438 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1440 struct radeon_device *rdev;
1442 rdev = container_of(work, struct radeon_device,
1443 pm.dynpm_idle_work.work);
1445 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1446 mutex_lock(&rdev->pm.mutex);
1447 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1448 int not_processed = 0;
1451 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1452 struct radeon_ring *ring = &rdev->ring[i];
1455 not_processed += radeon_fence_count_emitted(rdev, i);
1456 if (not_processed >= 3)
1461 if (not_processed >= 3) { /* should upclock */
1462 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1463 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1464 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1465 rdev->pm.dynpm_can_upclock) {
1466 rdev->pm.dynpm_planned_action =
1467 DYNPM_ACTION_UPCLOCK;
1468 rdev->pm.dynpm_action_timeout = jiffies +
1469 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1471 } else if (not_processed == 0) { /* should downclock */
1472 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1473 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1474 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1475 rdev->pm.dynpm_can_downclock) {
1476 rdev->pm.dynpm_planned_action =
1477 DYNPM_ACTION_DOWNCLOCK;
1478 rdev->pm.dynpm_action_timeout = jiffies +
1479 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1483 /* Note, radeon_pm_set_clocks is called with static_switch set
1484 * to false since we want to wait for vbl to avoid flicker.
1486 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1487 jiffies > rdev->pm.dynpm_action_timeout) {
1488 radeon_pm_get_dynpm_state(rdev);
1489 radeon_pm_set_clocks(rdev);
1492 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1493 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1495 mutex_unlock(&rdev->pm.mutex);
1496 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1502 #if defined(CONFIG_DEBUG_FS)
1504 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1506 struct drm_info_node *node = (struct drm_info_node *) m->private;
1507 struct drm_device *dev = node->minor->dev;
1508 struct radeon_device *rdev = dev->dev_private;
1510 if (rdev->pm.dpm_enabled) {
1511 mutex_lock(&rdev->pm.mutex);
1512 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1513 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1515 seq_printf(m, "Debugfs support not implemented for this asic\n");
1516 mutex_unlock(&rdev->pm.mutex);
1518 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1519 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1520 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1521 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1523 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1524 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1525 if (rdev->asic->pm.get_memory_clock)
1526 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1527 if (rdev->pm.current_vddc)
1528 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1529 if (rdev->asic->pm.get_pcie_lanes)
1530 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1536 static struct drm_info_list radeon_pm_info_list[] = {
1537 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1541 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1543 #if defined(CONFIG_DEBUG_FS)
1544 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));