drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #define RADEON_IDLE_LOOP_MS 100
  34 #define RADEON_RECLOCK_DELAY_MS 200
  35 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  36 #define RADEON_WAIT_IDLE_TIMEOUT 200
  37
  38 static const char *radeon_pm_state_type_name[5] = {
  39         "Default",
  40         "Powersave",
  41         "Battery",
  42         "Balanced",
  43         "Performance",
  44 };
  45
  46 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  47 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  48 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  50 static void radeon_pm_update_profile(struct radeon_device *rdev);
  51 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  52
  53 #define ACPI_AC_CLASS           "ac_adapter"
  54
  55 #ifdef CONFIG_ACPI
  56 static int radeon_acpi_event(struct notifier_block *nb,
  57                              unsigned long val,
  58                              void *data)
  59 {
  60         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  61         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  62
  63         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  64                 if (power_supply_is_system_supplied() > 0)
  65                         DRM_DEBUG("pm: AC\n");
  66                 else
  67                         DRM_DEBUG("pm: DC\n");
  68
  69                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  70                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  71                                 mutex_lock(&rdev->pm.mutex);
  72                                 radeon_pm_update_profile(rdev);
  73                                 radeon_pm_set_clocks(rdev);
  74                                 mutex_unlock(&rdev->pm.mutex);
  75                         }
  76                 }
  77         }
  78
  79         return NOTIFY_OK;
  80 }
  81 #endif
  82
  83 static void radeon_pm_update_profile(struct radeon_device *rdev)
  84 {
  85         switch (rdev->pm.profile) {
  86         case PM_PROFILE_DEFAULT:
  87                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  88                 break;
  89         case PM_PROFILE_AUTO:
  90                 if (power_supply_is_system_supplied() > 0) {
  91                         if (rdev->pm.active_crtc_count > 1)
  92                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  93                         else
  94                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  95                 } else {
  96                         if (rdev->pm.active_crtc_count > 1)
  97                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  98                         else
  99                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 100                 }
 101                 break;
 102         case PM_PROFILE_LOW:
 103                 if (rdev->pm.active_crtc_count > 1)
 104                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 105                 else
 106                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 107                 break;
 108         case PM_PROFILE_MID:
 109                 if (rdev->pm.active_crtc_count > 1)
 110                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 111                 else
 112                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 113                 break;
 114         case PM_PROFILE_HIGH:
 115                 if (rdev->pm.active_crtc_count > 1)
 116                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 117                 else
 118                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 119                 break;
 120         }
 121
 122         if (rdev->pm.active_crtc_count == 0) {
 123                 rdev->pm.requested_power_state_index =
 124                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 125                 rdev->pm.requested_clock_mode_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 127         } else {
 128                 rdev->pm.requested_power_state_index =
 129                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 130                 rdev->pm.requested_clock_mode_index =
 131                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 132         }
 133 }
 134
 135 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 136 {
 137         struct radeon_bo *bo, *n;
 138
 139         if (list_empty(&rdev->gem.objects))
 140                 return;
 141
 142         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 143                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 144                         ttm_bo_unmap_virtual(&bo->tbo);
 145         }
 146 }
 147
 148 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 149 {
 150         if (rdev->pm.active_crtcs) {
 151                 rdev->pm.vblank_sync = false;
 152                 wait_event_timeout(
 153                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 154                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 155         }
 156 }
 157
 158 static void radeon_set_power_state(struct radeon_device *rdev)
 159 {
 160         u32 sclk, mclk;
 161         bool misc_after = false;
 162
 163         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 164             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 165                 return;
 166
 167         if (radeon_gui_idle(rdev)) {
 168                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 169                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 170                 if (sclk > rdev->clock.default_sclk)
 171                         sclk = rdev->clock.default_sclk;
 172
 173                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 174                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 175                 if (mclk > rdev->clock.default_mclk)
 176                         mclk = rdev->clock.default_mclk;
 177
 178                 /* upvolt before raising clocks, downvolt after lowering clocks */
 179                 if (sclk < rdev->pm.current_sclk)
 180                         misc_after = true;
 181
 182                 radeon_sync_with_vblank(rdev);
 183
 184                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 185                         if (!radeon_pm_in_vbl(rdev))
 186                                 return;
 187                 }
 188
 189                 radeon_pm_prepare(rdev);
 190
 191                 if (!misc_after)
 192                         /* voltage, pcie lanes, etc.*/
 193                         radeon_pm_misc(rdev);
 194
 195                 /* set engine clock */
 196                 if (sclk != rdev->pm.current_sclk) {
 197                         radeon_pm_debug_check_in_vbl(rdev, false);
 198                         radeon_set_engine_clock(rdev, sclk);
 199                         radeon_pm_debug_check_in_vbl(rdev, true);
 200                         rdev->pm.current_sclk = sclk;
 201                         DRM_DEBUG("Setting: e: %d\n", sclk);
 202                 }
 203
 204                 /* set memory clock */
 205                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 206                         radeon_pm_debug_check_in_vbl(rdev, false);
 207                         radeon_set_memory_clock(rdev, mclk);
 208                         radeon_pm_debug_check_in_vbl(rdev, true);
 209                         rdev->pm.current_mclk = mclk;
 210                         DRM_DEBUG("Setting: m: %d\n", mclk);
 211                 }
 212
 213                 if (misc_after)
 214                         /* voltage, pcie lanes, etc.*/
 215                         radeon_pm_misc(rdev);
 216
 217                 radeon_pm_finish(rdev);
 218
 219                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 220                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 221         } else
 222                 DRM_DEBUG("pm: GUI not idle!!!\n");
 223 }
 224
 225 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 226 {
 227         int i;
 228
 229         mutex_lock(&rdev->ddev->struct_mutex);
 230         mutex_lock(&rdev->vram_mutex);
 231         mutex_lock(&rdev->cp.mutex);
 232
 233         /* gui idle int has issues on older chips it seems */
 234         if (rdev->family >= CHIP_R600) {
 235                 if (rdev->irq.installed) {
 236                         /* wait for GPU idle */
 237                         rdev->pm.gui_idle = false;
 238                         rdev->irq.gui_idle = true;
 239                         radeon_irq_set(rdev);
 240                         wait_event_interruptible_timeout(
 241                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 242                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 243                         rdev->irq.gui_idle = false;
 244                         radeon_irq_set(rdev);
 245                 }
 246         } else {
 247                 if (rdev->cp.ready) {
 248                         struct radeon_fence *fence;
 249                         radeon_ring_alloc(rdev, 64);
 250                         radeon_fence_create(rdev, &fence);
 251                         radeon_fence_emit(rdev, fence);
 252                         radeon_ring_commit(rdev);
 253                         radeon_fence_wait(fence, false);
 254                         radeon_fence_unref(&fence);
 255                 }
 256         }
 257         radeon_unmap_vram_bos(rdev);
 258
 259         if (rdev->irq.installed) {
 260                 for (i = 0; i < rdev->num_crtc; i++) {
 261                         if (rdev->pm.active_crtcs & (1 << i)) {
 262                                 rdev->pm.req_vblank |= (1 << i);
 263                                 drm_vblank_get(rdev->ddev, i);
 264                         }
 265                 }
 266         }
 267
 268         radeon_set_power_state(rdev);
 269
 270         if (rdev->irq.installed) {
 271                 for (i = 0; i < rdev->num_crtc; i++) {
 272                         if (rdev->pm.req_vblank & (1 << i)) {
 273                                 rdev->pm.req_vblank &= ~(1 << i);
 274                                 drm_vblank_put(rdev->ddev, i);
 275                         }
 276                 }
 277         }
 278
 279         /* update display watermarks based on new power state */
 280         radeon_update_bandwidth_info(rdev);
 281         if (rdev->pm.active_crtc_count)
 282                 radeon_bandwidth_update(rdev);
 283
 284         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 285
 286         mutex_unlock(&rdev->cp.mutex);
 287         mutex_unlock(&rdev->vram_mutex);
 288         mutex_unlock(&rdev->ddev->struct_mutex);
 289 }
 290
 291 static void radeon_pm_print_states(struct radeon_device *rdev)
 292 {
 293         int i, j;
 294         struct radeon_power_state *power_state;
 295         struct radeon_pm_clock_info *clock_info;
 296
 297         DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
 298         for (i = 0; i < rdev->pm.num_power_states; i++) {
 299                 power_state = &rdev->pm.power_state[i];
 300                 DRM_DEBUG("State %d: %s\n", i,
 301                         radeon_pm_state_type_name[power_state->type]);
 302                 if (i == rdev->pm.default_power_state_index)
 303                         DRM_DEBUG("\tDefault");
 304                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 305                         DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 306                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 307                         DRM_DEBUG("\tSingle display only\n");
 308                 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 309                 for (j = 0; j < power_state->num_clock_modes; j++) {
 310                         clock_info = &(power_state->clock_info[j]);
 311                         if (rdev->flags & RADEON_IS_IGP)
 312                                 DRM_DEBUG("\t\t%d e: %d%s\n",
 313                                         j,
 314                                         clock_info->sclk * 10,
 315                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 316                         else
 317                                 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 318                                         j,
 319                                         clock_info->sclk * 10,
 320                                         clock_info->mclk * 10,
 321                                         clock_info->voltage.voltage,
 322                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 323                 }
 324         }
 325 }
 326
 327 static ssize_t radeon_get_pm_profile(struct device *dev,
 328                                      struct device_attribute *attr,
 329                                      char *buf)
 330 {
 331         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 332         struct radeon_device *rdev = ddev->dev_private;
 333         int cp = rdev->pm.profile;
 334
 335         return snprintf(buf, PAGE_SIZE, "%s\n",
 336                         (cp == PM_PROFILE_AUTO) ? "auto" :
 337                         (cp == PM_PROFILE_LOW) ? "low" :
 338                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 339 }
 340
 341 static ssize_t radeon_set_pm_profile(struct device *dev,
 342                                      struct device_attribute *attr,
 343                                      const char *buf,
 344                                      size_t count)
 345 {
 346         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 347         struct radeon_device *rdev = ddev->dev_private;
 348
 349         mutex_lock(&rdev->pm.mutex);
 350         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 351                 if (strncmp("default", buf, strlen("default")) == 0)
 352                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 353                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 354                         rdev->pm.profile = PM_PROFILE_AUTO;
 355                 else if (strncmp("low", buf, strlen("low")) == 0)
 356                         rdev->pm.profile = PM_PROFILE_LOW;
 357                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 358                         rdev->pm.profile = PM_PROFILE_MID;
 359                 else if (strncmp("high", buf, strlen("high")) == 0)
 360                         rdev->pm.profile = PM_PROFILE_HIGH;
 361                 else {
 362                         DRM_ERROR("invalid power profile!\n");
 363                         goto fail;
 364                 }
 365                 radeon_pm_update_profile(rdev);
 366                 radeon_pm_set_clocks(rdev);
 367         }
 368 fail:
 369         mutex_unlock(&rdev->pm.mutex);
 370
 371         return count;
 372 }
 373
 374 static ssize_t radeon_get_pm_method(struct device *dev,
 375                                     struct device_attribute *attr,
 376                                     char *buf)
 377 {
 378         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 379         struct radeon_device *rdev = ddev->dev_private;
 380         int pm = rdev->pm.pm_method;
 381
 382         return snprintf(buf, PAGE_SIZE, "%s\n",
 383                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 384 }
 385
 386 static ssize_t radeon_set_pm_method(struct device *dev,
 387                                     struct device_attribute *attr,
 388                                     const char *buf,
 389                                     size_t count)
 390 {
 391         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 392         struct radeon_device *rdev = ddev->dev_private;
 393
 394
 395         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 396                 mutex_lock(&rdev->pm.mutex);
 397                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 398                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 399                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 400                 mutex_unlock(&rdev->pm.mutex);
 401         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 402                 bool flush_wq = false;
 403
 404                 mutex_lock(&rdev->pm.mutex);
 405                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 406                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 407                         flush_wq = true;
 408                 }
 409                 /* disable dynpm */
 410                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 411                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 412                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 413                 mutex_unlock(&rdev->pm.mutex);
 414                 if (flush_wq)
 415                         flush_workqueue(rdev->wq);
 416         } else {
 417                 DRM_ERROR("invalid power method!\n");
 418                 goto fail;
 419         }
 420         radeon_pm_compute_clocks(rdev);
 421 fail:
 422         return count;
 423 }
 424
 425 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 426 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 427
 428 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 429                                       struct device_attribute *attr,
 430                                       char *buf)
 431 {
 432         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 433         struct radeon_device *rdev = ddev->dev_private;
 434         u32 temp;
 435
 436         switch (rdev->pm.int_thermal_type) {
 437         case THERMAL_TYPE_RV6XX:
 438                 temp = rv6xx_get_temp(rdev);
 439                 break;
 440         case THERMAL_TYPE_RV770:
 441                 temp = rv770_get_temp(rdev);
 442                 break;
 443         case THERMAL_TYPE_EVERGREEN:
 444                 temp = evergreen_get_temp(rdev);
 445                 break;
 446         default:
 447                 temp = 0;
 448                 break;
 449         }
 450
 451         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 452 }
 453
 454 static ssize_t radeon_hwmon_show_name(struct device *dev,
 455                                       struct device_attribute *attr,
 456                                       char *buf)
 457 {
 458         return sprintf(buf, "radeon\n");
 459 }
 460
 461 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 462 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 463
 464 static struct attribute *hwmon_attributes[] = {
 465         &sensor_dev_attr_temp1_input.dev_attr.attr,
 466         &sensor_dev_attr_name.dev_attr.attr,
 467         NULL
 468 };
 469
 470 static const struct attribute_group hwmon_attrgroup = {
 471         .attrs = hwmon_attributes,
 472 };
 473
 474 static void radeon_hwmon_init(struct radeon_device *rdev)
 475 {
 476         int err;
 477
 478         rdev->pm.int_hwmon_dev = NULL;
 479
 480         switch (rdev->pm.int_thermal_type) {
 481         case THERMAL_TYPE_RV6XX:
 482         case THERMAL_TYPE_RV770:
 483         case THERMAL_TYPE_EVERGREEN:
 484                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 485                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 486                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 487                                          &hwmon_attrgroup);
 488                 if (err)
 489                         DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err);
 490                 break;
 491         default:
 492                 break;
 493         }
 494 }
 495
 496 static void radeon_hwmon_fini(struct radeon_device *rdev)
 497 {
 498         if (rdev->pm.int_hwmon_dev) {
 499                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 500                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 501         }
 502 }
 503
 504 void radeon_pm_suspend(struct radeon_device *rdev)
 505 {
 506         bool flush_wq = false;
 507
 508         mutex_lock(&rdev->pm.mutex);
 509         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 510                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 511                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 512                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 513                 flush_wq = true;
 514         }
 515         mutex_unlock(&rdev->pm.mutex);
 516         if (flush_wq)
 517                 flush_workqueue(rdev->wq);
 518 }
 519
 520 void radeon_pm_resume(struct radeon_device *rdev)
 521 {
 522         /* asic init will reset the default power state */
 523         mutex_lock(&rdev->pm.mutex);
 524         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 525         rdev->pm.current_clock_mode_index = 0;
 526         rdev->pm.current_sclk = rdev->clock.default_sclk;
 527         rdev->pm.current_mclk = rdev->clock.default_mclk;
 528         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 529         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 530             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 531                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 532                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 533                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 534         }
 535         mutex_unlock(&rdev->pm.mutex);
 536         radeon_pm_compute_clocks(rdev);
 537 }
 538
 539 int radeon_pm_init(struct radeon_device *rdev)
 540 {
 541         int ret;
 542         /* default to profile method */
 543         rdev->pm.pm_method = PM_METHOD_PROFILE;
 544         rdev->pm.profile = PM_PROFILE_DEFAULT;
 545         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 546         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 547         rdev->pm.dynpm_can_upclock = true;
 548         rdev->pm.dynpm_can_downclock = true;
 549         rdev->pm.current_sclk = rdev->clock.default_sclk;
 550         rdev->pm.current_mclk = rdev->clock.default_mclk;
 551         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 552
 553         if (rdev->bios) {
 554                 if (rdev->is_atom_bios)
 555                         radeon_atombios_get_power_modes(rdev);
 556                 else
 557                         radeon_combios_get_power_modes(rdev);
 558                 radeon_pm_print_states(rdev);
 559                 radeon_pm_init_profile(rdev);
 560         }
 561
 562         /* set up the internal thermal sensor if applicable */
 563         radeon_hwmon_init(rdev);
 564         if (rdev->pm.num_power_states > 1) {
 565                 /* where's the best place to put these? */
 566                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 567                 if (ret)
 568                         DRM_ERROR("failed to create device file for power profile\n");
 569                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 570                 if (ret)
 571                         DRM_ERROR("failed to create device file for power method\n");
 572
 573 #ifdef CONFIG_ACPI
 574                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 575                 register_acpi_notifier(&rdev->acpi_nb);
 576 #endif
 577                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 578
 579                 if (radeon_debugfs_pm_init(rdev)) {
 580                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 581                 }
 582
 583                 DRM_INFO("radeon: power management initialized\n");
 584         }
 585
 586         return 0;
 587 }
 588
 589 void radeon_pm_fini(struct radeon_device *rdev)
 590 {
 591         if (rdev->pm.num_power_states > 1) {
 592                 bool flush_wq = false;
 593
 594                 mutex_lock(&rdev->pm.mutex);
 595                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 596                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 597                         radeon_pm_update_profile(rdev);
 598                         radeon_pm_set_clocks(rdev);
 599                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 600                         /* cancel work */
 601                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 602                         flush_wq = true;
 603                         /* reset default clocks */
 604                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 605                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 606                         radeon_pm_set_clocks(rdev);
 607                 }
 608                 mutex_unlock(&rdev->pm.mutex);
 609                 if (flush_wq)
 610                         flush_workqueue(rdev->wq);
 611
 612                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 613                 device_remove_file(rdev->dev, &dev_attr_power_method);
 614 #ifdef CONFIG_ACPI
 615                 unregister_acpi_notifier(&rdev->acpi_nb);
 616 #endif
 617         }
 618
 619         radeon_hwmon_fini(rdev);
 620         if (rdev->pm.i2c_bus)
 621                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 622 }
 623
 624 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 625 {
 626         struct drm_device *ddev = rdev->ddev;
 627         struct drm_crtc *crtc;
 628         struct radeon_crtc *radeon_crtc;
 629
 630         if (rdev->pm.num_power_states < 2)
 631                 return;
 632
 633         mutex_lock(&rdev->pm.mutex);
 634
 635         rdev->pm.active_crtcs = 0;
 636         rdev->pm.active_crtc_count = 0;
 637         list_for_each_entry(crtc,
 638                 &ddev->mode_config.crtc_list, head) {
 639                 radeon_crtc = to_radeon_crtc(crtc);
 640                 if (radeon_crtc->enabled) {
 641                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 642                         rdev->pm.active_crtc_count++;
 643                 }
 644         }
 645
 646         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 647                 radeon_pm_update_profile(rdev);
 648                 radeon_pm_set_clocks(rdev);
 649         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 650                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 651                         if (rdev->pm.active_crtc_count > 1) {
 652                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 653                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 654
 655                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 656                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 657                                         radeon_pm_get_dynpm_state(rdev);
 658                                         radeon_pm_set_clocks(rdev);
 659
 660                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 661                                 }
 662                         } else if (rdev->pm.active_crtc_count == 1) {
 663                                 /* TODO: Increase clocks if needed for current mode */
 664
 665                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 666                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 667                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 668                                         radeon_pm_get_dynpm_state(rdev);
 669                                         radeon_pm_set_clocks(rdev);
 670
 671                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 672                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 673                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 674                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 675                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 676                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 677                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 678                                 }
 679                         } else { /* count == 0 */
 680                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 681                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 682
 683                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 684                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 685                                         radeon_pm_get_dynpm_state(rdev);
 686                                         radeon_pm_set_clocks(rdev);
 687                                 }
 688                         }
 689                 }
 690         }
 691
 692         mutex_unlock(&rdev->pm.mutex);
 693 }
 694
 695 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 696 {
 697         u32 stat_crtc = 0, vbl = 0, position = 0;
 698         bool in_vbl = true;
 699
 700         if (ASIC_IS_DCE4(rdev)) {
 701                 if (rdev->pm.active_crtcs & (1 << 0)) {
 702                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 703                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 704                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 705                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 706                 }
 707                 if (rdev->pm.active_crtcs & (1 << 1)) {
 708                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 709                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 710                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 711                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 712                 }
 713                 if (rdev->pm.active_crtcs & (1 << 2)) {
 714                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 715                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 716                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 717                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 718                 }
 719                 if (rdev->pm.active_crtcs & (1 << 3)) {
 720                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 721                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 722                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 723                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 724                 }
 725                 if (rdev->pm.active_crtcs & (1 << 4)) {
 726                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 727                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 728                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 729                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 730                 }
 731                 if (rdev->pm.active_crtcs & (1 << 5)) {
 732                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 733                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 734                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 735                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 736                 }
 737         } else if (ASIC_IS_AVIVO(rdev)) {
 738                 if (rdev->pm.active_crtcs & (1 << 0)) {
 739                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 740                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 741                 }
 742                 if (rdev->pm.active_crtcs & (1 << 1)) {
 743                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 744                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 745                 }
 746                 if (position < vbl && position > 1)
 747                         in_vbl = false;
 748         } else {
 749                 if (rdev->pm.active_crtcs & (1 << 0)) {
 750                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 751                         if (!(stat_crtc & 1))
 752                                 in_vbl = false;
 753                 }
 754                 if (rdev->pm.active_crtcs & (1 << 1)) {
 755                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 756                         if (!(stat_crtc & 1))
 757                                 in_vbl = false;
 758                 }
 759         }
 760
 761         if (position < vbl && position > 1)
 762                 in_vbl = false;
 763
 764         return in_vbl;
 765 }
 766
 767 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 768 {
 769         u32 stat_crtc = 0;
 770         bool in_vbl = radeon_pm_in_vbl(rdev);
 771
 772         if (in_vbl == false)
 773                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 774                          finish ? "exit" : "entry");
 775         return in_vbl;
 776 }
 777
 778 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 779 {
 780         struct radeon_device *rdev;
 781         int resched;
 782         rdev = container_of(work, struct radeon_device,
 783                                 pm.dynpm_idle_work.work);
 784
 785         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 786         mutex_lock(&rdev->pm.mutex);
 787         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 788                 unsigned long irq_flags;
 789                 int not_processed = 0;
 790
 791                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 792                 if (!list_empty(&rdev->fence_drv.emited)) {
 793                         struct list_head *ptr;
 794                         list_for_each(ptr, &rdev->fence_drv.emited) {
 795                                 /* count up to 3, that's enought info */
 796                                 if (++not_processed >= 3)
 797                                         break;
 798                         }
 799                 }
 800                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 801
 802                 if (not_processed >= 3) { /* should upclock */
 803                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 804                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 805                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 806                                    rdev->pm.dynpm_can_upclock) {
 807                                 rdev->pm.dynpm_planned_action =
 808                                         DYNPM_ACTION_UPCLOCK;
 809                                 rdev->pm.dynpm_action_timeout = jiffies +
 810                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 811                         }
 812                 } else if (not_processed == 0) { /* should downclock */
 813                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 814                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 815                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 816                                    rdev->pm.dynpm_can_downclock) {
 817                                 rdev->pm.dynpm_planned_action =
 818                                         DYNPM_ACTION_DOWNCLOCK;
 819                                 rdev->pm.dynpm_action_timeout = jiffies +
 820                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 821                         }
 822                 }
 823
 824                 /* Note, radeon_pm_set_clocks is called with static_switch set
 825                  * to false since we want to wait for vbl to avoid flicker.
 826                  */
 827                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 828                     jiffies > rdev->pm.dynpm_action_timeout) {
 829                         radeon_pm_get_dynpm_state(rdev);
 830                         radeon_pm_set_clocks(rdev);
 831                 }
 832
 833                 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 834                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 835         }
 836         mutex_unlock(&rdev->pm.mutex);
 837         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 838 }
 839
 840 /*
 841  * Debugfs info
 842  */
 843 #if defined(CONFIG_DEBUG_FS)
 844
 845 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 846 {
 847         struct drm_info_node *node = (struct drm_info_node *) m->private;
 848         struct drm_device *dev = node->minor->dev;
 849         struct radeon_device *rdev = dev->dev_private;
 850
 851         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 852         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 853         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 854         if (rdev->asic->get_memory_clock)
 855                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 856         if (rdev->pm.current_vddc)
 857                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 858         if (rdev->asic->get_pcie_lanes)
 859                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 860
 861         return 0;
 862 }
 863
 864 static struct drm_info_list radeon_pm_info_list[] = {
 865         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 866 };
 867 #endif
 868
 869 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 870 {
 871 #if defined(CONFIG_DEBUG_FS)
 872         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 873 #else
 874         return 0;
 875 #endif
 876 }