2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_drm.h"
31 #include "radeon_reg.h"
35 int radeon_debugfs_ib_init(struct radeon_device *rdev);
40 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
42 struct radeon_fence *fence;
43 struct radeon_ib *nib;
47 r = radeon_fence_create(rdev, &fence);
49 dev_err(rdev->dev, "failed to create fence for new IB\n");
52 mutex_lock(&rdev->ib_pool.mutex);
53 for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
54 i &= (RADEON_IB_POOL_SIZE - 1);
55 if (rdev->ib_pool.ibs[i].free) {
56 nib = &rdev->ib_pool.ibs[i];
61 /* This should never happen, it means we allocated all
62 * IB and haven't scheduled one yet, return EBUSY to
63 * userspace hoping that on ioctl recall we get better
66 dev_err(rdev->dev, "no free indirect buffer !\n");
67 mutex_unlock(&rdev->ib_pool.mutex);
68 radeon_fence_unref(&fence);
71 rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
74 mutex_unlock(&rdev->ib_pool.mutex);
75 r = radeon_fence_wait(nib->fence, false);
77 dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
78 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
79 mutex_lock(&rdev->ib_pool.mutex);
81 mutex_unlock(&rdev->ib_pool.mutex);
82 radeon_fence_unref(&fence);
85 mutex_lock(&rdev->ib_pool.mutex);
87 radeon_fence_unref(&nib->fence);
90 mutex_unlock(&rdev->ib_pool.mutex);
95 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
97 struct radeon_ib *tmp = *ib;
103 if (!tmp->fence->emited)
104 radeon_fence_unref(&tmp->fence);
105 mutex_lock(&rdev->ib_pool.mutex);
107 mutex_unlock(&rdev->ib_pool.mutex);
110 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
114 if (!ib->length_dw || !rdev->cp.ready) {
115 /* TODO: Nothings in the ib we should report. */
116 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
120 /* 64 dwords should be enough for fence too */
121 r = radeon_ring_lock(rdev, 64);
123 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
126 radeon_ring_ib_execute(rdev, ib);
127 radeon_fence_emit(rdev, ib->fence);
128 mutex_lock(&rdev->ib_pool.mutex);
129 /* once scheduled IB is considered free and protected by the fence */
131 mutex_unlock(&rdev->ib_pool.mutex);
132 radeon_ring_unlock_commit(rdev);
136 int radeon_ib_pool_init(struct radeon_device *rdev)
143 if (rdev->ib_pool.robj)
145 /* Allocate 1M object buffer */
146 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
147 true, RADEON_GEM_DOMAIN_GTT,
148 &rdev->ib_pool.robj);
150 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
153 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
154 if (unlikely(r != 0))
156 r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
158 radeon_bo_unreserve(rdev->ib_pool.robj);
159 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
162 r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
163 radeon_bo_unreserve(rdev->ib_pool.robj);
165 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
168 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
171 offset = i * 64 * 1024;
172 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
173 rdev->ib_pool.ibs[i].ptr = ptr + offset;
174 rdev->ib_pool.ibs[i].idx = i;
175 rdev->ib_pool.ibs[i].length_dw = 0;
176 rdev->ib_pool.ibs[i].free = true;
178 rdev->ib_pool.head_id = 0;
179 rdev->ib_pool.ready = true;
180 DRM_INFO("radeon: ib pool ready.\n");
181 if (radeon_debugfs_ib_init(rdev)) {
182 DRM_ERROR("Failed to register debugfs file for IB !\n");
187 void radeon_ib_pool_fini(struct radeon_device *rdev)
191 if (!rdev->ib_pool.ready) {
194 mutex_lock(&rdev->ib_pool.mutex);
195 if (rdev->ib_pool.robj) {
196 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
197 if (likely(r == 0)) {
198 radeon_bo_kunmap(rdev->ib_pool.robj);
199 radeon_bo_unpin(rdev->ib_pool.robj);
200 radeon_bo_unreserve(rdev->ib_pool.robj);
202 radeon_bo_unref(&rdev->ib_pool.robj);
203 rdev->ib_pool.robj = NULL;
205 mutex_unlock(&rdev->ib_pool.mutex);
212 void radeon_ring_free_size(struct radeon_device *rdev)
214 if (rdev->family >= CHIP_R600)
215 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
217 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
218 /* This works because ring_size is a power of 2 */
219 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
220 rdev->cp.ring_free_dw -= rdev->cp.wptr;
221 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
222 if (!rdev->cp.ring_free_dw) {
223 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
227 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
231 /* Align requested size with padding so unlock_commit can
233 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
234 mutex_lock(&rdev->cp.mutex);
235 while (ndw > (rdev->cp.ring_free_dw - 1)) {
236 radeon_ring_free_size(rdev);
237 if (ndw < rdev->cp.ring_free_dw) {
240 r = radeon_fence_wait_next(rdev);
242 mutex_unlock(&rdev->cp.mutex);
246 rdev->cp.count_dw = ndw;
247 rdev->cp.wptr_old = rdev->cp.wptr;
251 void radeon_ring_unlock_commit(struct radeon_device *rdev)
253 unsigned count_dw_pad;
256 /* We pad to match fetch size */
257 count_dw_pad = (rdev->cp.align_mask + 1) -
258 (rdev->cp.wptr & rdev->cp.align_mask);
259 for (i = 0; i < count_dw_pad; i++) {
260 radeon_ring_write(rdev, 2 << 30);
263 radeon_cp_commit(rdev);
264 mutex_unlock(&rdev->cp.mutex);
267 void radeon_ring_unlock_undo(struct radeon_device *rdev)
269 rdev->cp.wptr = rdev->cp.wptr_old;
270 mutex_unlock(&rdev->cp.mutex);
273 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
277 rdev->cp.ring_size = ring_size;
278 /* Allocate ring buffer */
279 if (rdev->cp.ring_obj == NULL) {
280 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
281 RADEON_GEM_DOMAIN_GTT,
284 dev_err(rdev->dev, "(%d) ring create failed\n", r);
287 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
288 if (unlikely(r != 0))
290 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
293 radeon_bo_unreserve(rdev->cp.ring_obj);
294 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
297 r = radeon_bo_kmap(rdev->cp.ring_obj,
298 (void **)&rdev->cp.ring);
299 radeon_bo_unreserve(rdev->cp.ring_obj);
301 dev_err(rdev->dev, "(%d) ring map failed\n", r);
305 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
306 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
310 void radeon_ring_fini(struct radeon_device *rdev)
314 mutex_lock(&rdev->cp.mutex);
315 if (rdev->cp.ring_obj) {
316 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
317 if (likely(r == 0)) {
318 radeon_bo_kunmap(rdev->cp.ring_obj);
319 radeon_bo_unpin(rdev->cp.ring_obj);
320 radeon_bo_unreserve(rdev->cp.ring_obj);
322 radeon_bo_unref(&rdev->cp.ring_obj);
323 rdev->cp.ring = NULL;
324 rdev->cp.ring_obj = NULL;
326 mutex_unlock(&rdev->cp.mutex);
333 #if defined(CONFIG_DEBUG_FS)
334 static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
336 struct drm_info_node *node = (struct drm_info_node *) m->private;
337 struct radeon_ib *ib = node->info_ent->data;
343 seq_printf(m, "IB %04u\n", ib->idx);
344 seq_printf(m, "IB fence %p\n", ib->fence);
345 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
346 for (i = 0; i < ib->length_dw; i++) {
347 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
352 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
353 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
356 int radeon_debugfs_ib_init(struct radeon_device *rdev)
358 #if defined(CONFIG_DEBUG_FS)
361 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
362 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
363 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
364 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
365 radeon_debugfs_ib_list[i].driver_features = 0;
366 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
368 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
369 RADEON_IB_POOL_SIZE);