2 * Copyright 2009 VMware, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Michel Dänzer
25 #include <drm/radeon_drm.h>
26 #include "radeon_reg.h"
30 /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
31 void radeon_test_moves(struct radeon_device *rdev)
33 struct radeon_bo *vram_obj = NULL;
34 struct radeon_bo **gtt_obj = NULL;
35 struct radeon_fence *fence = NULL;
36 uint64_t gtt_addr, vram_addr;
43 * (Total GTT - IB pool - writeback page - ring buffers) / test size
45 n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
46 for (i = 0; i < RADEON_NUM_RINGS; ++i)
47 n -= rdev->ring[i].ring_size;
49 n -= RADEON_GPU_PAGE_SIZE;
50 if (rdev->ih.ring_obj)
51 n -= rdev->ih.ring_size;
54 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
56 DRM_ERROR("Failed to allocate %d pointers\n", n);
61 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
64 DRM_ERROR("Failed to create VRAM object\n");
67 r = radeon_bo_reserve(vram_obj, false);
70 r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
72 DRM_ERROR("Failed to pin VRAM object\n");
75 for (i = 0; i < n; i++) {
76 void *gtt_map, *vram_map;
77 void **gtt_start, **gtt_end;
78 void **vram_start, **vram_end;
80 r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
81 RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i);
83 DRM_ERROR("Failed to create GTT object %d\n", i);
87 r = radeon_bo_reserve(gtt_obj[i], false);
90 r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr);
92 DRM_ERROR("Failed to pin GTT object %d\n", i);
96 r = radeon_bo_kmap(gtt_obj[i], >t_map);
98 DRM_ERROR("Failed to map GTT object %d\n", i);
102 for (gtt_start = gtt_map, gtt_end = gtt_map + size;
105 *gtt_start = gtt_start;
107 radeon_bo_kunmap(gtt_obj[i]);
109 r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
111 DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i);
115 r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);
117 DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
121 r = radeon_fence_wait(fence, false);
123 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
127 radeon_fence_unref(&fence);
129 r = radeon_bo_kmap(vram_obj, &vram_map);
131 DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
135 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
136 vram_start = vram_map, vram_end = vram_map + size;
137 vram_start < vram_end;
138 gtt_start++, vram_start++) {
139 if (*vram_start != gtt_start) {
140 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
141 "expected 0x%p (GTT/VRAM offset "
142 "0x%16llx/0x%16llx)\n",
143 i, *vram_start, gtt_start,
145 (gtt_addr - rdev->mc.gtt_start +
146 (void*)gtt_start - gtt_map),
148 (vram_addr - rdev->mc.vram_start +
149 (void*)gtt_start - gtt_map));
150 radeon_bo_kunmap(vram_obj);
153 *vram_start = vram_start;
156 radeon_bo_kunmap(vram_obj);
158 r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
160 DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i);
164 r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence);
166 DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
170 r = radeon_fence_wait(fence, false);
172 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
176 radeon_fence_unref(&fence);
178 r = radeon_bo_kmap(gtt_obj[i], >t_map);
180 DRM_ERROR("Failed to map GTT object after copy %d\n", i);
184 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
185 vram_start = vram_map, vram_end = vram_map + size;
187 gtt_start++, vram_start++) {
188 if (*gtt_start != vram_start) {
189 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
190 "expected 0x%p (VRAM/GTT offset "
191 "0x%16llx/0x%16llx)\n",
192 i, *gtt_start, vram_start,
194 (vram_addr - rdev->mc.vram_start +
195 (void*)vram_start - vram_map),
197 (gtt_addr - rdev->mc.gtt_start +
198 (void*)vram_start - vram_map));
199 radeon_bo_kunmap(gtt_obj[i]);
204 radeon_bo_kunmap(gtt_obj[i]);
206 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
207 gtt_addr - rdev->mc.gtt_start);
212 if (radeon_bo_is_reserved(vram_obj)) {
213 radeon_bo_unpin(vram_obj);
214 radeon_bo_unreserve(vram_obj);
216 radeon_bo_unref(&vram_obj);
219 for (i = 0; i < n; i++) {
221 if (radeon_bo_is_reserved(gtt_obj[i])) {
222 radeon_bo_unpin(gtt_obj[i]);
223 radeon_bo_unreserve(gtt_obj[i]);
225 radeon_bo_unref(>t_obj[i]);
231 radeon_fence_unref(&fence);
234 printk(KERN_WARNING "Error while testing BO move.\n");
238 void radeon_test_ring_sync(struct radeon_device *rdev,
239 struct radeon_ring *ringA,
240 struct radeon_ring *ringB)
242 struct radeon_fence *fence1 = NULL, *fence2 = NULL;
243 struct radeon_semaphore *semaphore = NULL;
244 int ridxA = radeon_ring_index(rdev, ringA);
245 int ridxB = radeon_ring_index(rdev, ringB);
248 r = radeon_fence_create(rdev, &fence1, ridxA);
250 DRM_ERROR("Failed to create sync fence 1\n");
253 r = radeon_fence_create(rdev, &fence2, ridxA);
255 DRM_ERROR("Failed to create sync fence 2\n");
259 r = radeon_semaphore_create(rdev, &semaphore);
261 DRM_ERROR("Failed to create semaphore\n");
265 r = radeon_ring_lock(rdev, ringA, 64);
267 DRM_ERROR("Failed to lock ring A %d\n", ridxA);
270 radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
271 radeon_fence_emit(rdev, fence1);
272 radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
273 radeon_fence_emit(rdev, fence2);
274 radeon_ring_unlock_commit(rdev, ringA);
278 if (radeon_fence_signaled(fence1)) {
279 DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
283 r = radeon_ring_lock(rdev, ringB, 64);
285 DRM_ERROR("Failed to lock ring B %p\n", ringB);
288 radeon_semaphore_emit_signal(rdev, ridxB, semaphore);
289 radeon_ring_unlock_commit(rdev, ringB);
291 r = radeon_fence_wait(fence1, false);
293 DRM_ERROR("Failed to wait for sync fence 1\n");
299 if (radeon_fence_signaled(fence2)) {
300 DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
304 r = radeon_ring_lock(rdev, ringB, 64);
306 DRM_ERROR("Failed to lock ring B %p\n", ringB);
309 radeon_semaphore_emit_signal(rdev, ridxB, semaphore);
310 radeon_ring_unlock_commit(rdev, ringB);
312 r = radeon_fence_wait(fence2, false);
314 DRM_ERROR("Failed to wait for sync fence 1\n");
320 radeon_semaphore_free(rdev, semaphore, NULL);
323 radeon_fence_unref(&fence1);
326 radeon_fence_unref(&fence2);
329 printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
332 void radeon_test_ring_sync2(struct radeon_device *rdev,
333 struct radeon_ring *ringA,
334 struct radeon_ring *ringB,
335 struct radeon_ring *ringC)
337 struct radeon_fence *fenceA = NULL, *fenceB = NULL;
338 struct radeon_semaphore *semaphore = NULL;
339 int ridxA = radeon_ring_index(rdev, ringA);
340 int ridxB = radeon_ring_index(rdev, ringB);
341 int ridxC = radeon_ring_index(rdev, ringC);
345 r = radeon_fence_create(rdev, &fenceA, ridxA);
347 DRM_ERROR("Failed to create sync fence 1\n");
350 r = radeon_fence_create(rdev, &fenceB, ridxB);
352 DRM_ERROR("Failed to create sync fence 2\n");
356 r = radeon_semaphore_create(rdev, &semaphore);
358 DRM_ERROR("Failed to create semaphore\n");
362 r = radeon_ring_lock(rdev, ringA, 64);
364 DRM_ERROR("Failed to lock ring A %d\n", ridxA);
367 radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
368 radeon_fence_emit(rdev, fenceA);
369 radeon_ring_unlock_commit(rdev, ringA);
371 r = radeon_ring_lock(rdev, ringB, 64);
373 DRM_ERROR("Failed to lock ring B %d\n", ridxB);
376 radeon_semaphore_emit_wait(rdev, ridxB, semaphore);
377 radeon_fence_emit(rdev, fenceB);
378 radeon_ring_unlock_commit(rdev, ringB);
382 if (radeon_fence_signaled(fenceA)) {
383 DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
386 if (radeon_fence_signaled(fenceB)) {
387 DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
391 r = radeon_ring_lock(rdev, ringC, 64);
393 DRM_ERROR("Failed to lock ring B %p\n", ringC);
396 radeon_semaphore_emit_signal(rdev, ridxC, semaphore);
397 radeon_ring_unlock_commit(rdev, ringC);
399 for (i = 0; i < 30; ++i) {
401 sigA = radeon_fence_signaled(fenceA);
402 sigB = radeon_fence_signaled(fenceB);
407 if (!sigA && !sigB) {
408 DRM_ERROR("Neither fence A nor B has been signaled\n");
410 } else if (sigA && sigB) {
411 DRM_ERROR("Both fence A and B has been signaled\n");
415 DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
417 r = radeon_ring_lock(rdev, ringC, 64);
419 DRM_ERROR("Failed to lock ring B %p\n", ringC);
422 radeon_semaphore_emit_signal(rdev, ridxC, semaphore);
423 radeon_ring_unlock_commit(rdev, ringC);
427 r = radeon_fence_wait(fenceA, false);
429 DRM_ERROR("Failed to wait for sync fence A\n");
432 r = radeon_fence_wait(fenceB, false);
434 DRM_ERROR("Failed to wait for sync fence B\n");
440 radeon_semaphore_free(rdev, semaphore, NULL);
443 radeon_fence_unref(&fenceA);
446 radeon_fence_unref(&fenceB);
449 printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
452 void radeon_test_syncing(struct radeon_device *rdev)
456 for (i = 1; i < RADEON_NUM_RINGS; ++i) {
457 struct radeon_ring *ringA = &rdev->ring[i];
461 for (j = 0; j < i; ++j) {
462 struct radeon_ring *ringB = &rdev->ring[j];
466 DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
467 radeon_test_ring_sync(rdev, ringA, ringB);
469 DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
470 radeon_test_ring_sync(rdev, ringB, ringA);
472 for (k = 0; k < j; ++k) {
473 struct radeon_ring *ringC = &rdev->ring[k];
477 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
478 radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
480 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
481 radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
483 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
484 radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
486 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
487 radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
489 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
490 radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
492 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
493 radeon_test_ring_sync2(rdev, ringC, ringB, ringA);