2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
38 #include <drm/radeon_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include "radeon_reg.h"
44 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
46 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
48 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
50 struct radeon_mman *mman;
51 struct radeon_device *rdev;
53 mman = container_of(bdev, struct radeon_mman, bdev);
54 rdev = container_of(mman, struct radeon_device, mman);
62 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
64 return ttm_mem_global_init(ref->object);
67 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
69 ttm_mem_global_release(ref->object);
72 static int radeon_ttm_global_init(struct radeon_device *rdev)
74 struct drm_global_reference *global_ref;
77 rdev->mman.mem_global_referenced = false;
78 global_ref = &rdev->mman.mem_global_ref;
79 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
80 global_ref->size = sizeof(struct ttm_mem_global);
81 global_ref->init = &radeon_ttm_mem_global_init;
82 global_ref->release = &radeon_ttm_mem_global_release;
83 r = drm_global_item_ref(global_ref);
85 DRM_ERROR("Failed setting up TTM memory accounting "
90 rdev->mman.bo_global_ref.mem_glob =
91 rdev->mman.mem_global_ref.object;
92 global_ref = &rdev->mman.bo_global_ref.ref;
93 global_ref->global_type = DRM_GLOBAL_TTM_BO;
94 global_ref->size = sizeof(struct ttm_bo_global);
95 global_ref->init = &ttm_bo_global_init;
96 global_ref->release = &ttm_bo_global_release;
97 r = drm_global_item_ref(global_ref);
99 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
100 drm_global_item_unref(&rdev->mman.mem_global_ref);
104 rdev->mman.mem_global_referenced = true;
108 static void radeon_ttm_global_fini(struct radeon_device *rdev)
110 if (rdev->mman.mem_global_referenced) {
111 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
112 drm_global_item_unref(&rdev->mman.mem_global_ref);
113 rdev->mman.mem_global_referenced = false;
117 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
122 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
123 struct ttm_mem_type_manager *man)
125 struct radeon_device *rdev;
127 rdev = radeon_get_rdev(bdev);
132 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
133 man->available_caching = TTM_PL_MASK_CACHING;
134 man->default_caching = TTM_PL_FLAG_CACHED;
137 man->func = &ttm_bo_manager_func;
138 man->gpu_offset = rdev->mc.gtt_start;
139 man->available_caching = TTM_PL_MASK_CACHING;
140 man->default_caching = TTM_PL_FLAG_CACHED;
141 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
143 if (rdev->flags & RADEON_IS_AGP) {
144 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
145 DRM_ERROR("AGP is not enabled for memory type %u\n",
149 if (!rdev->ddev->agp->cant_use_aperture)
150 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
151 man->available_caching = TTM_PL_FLAG_UNCACHED |
153 man->default_caching = TTM_PL_FLAG_WC;
158 /* "On-card" video ram */
159 man->func = &ttm_bo_manager_func;
160 man->gpu_offset = rdev->mc.vram_start;
161 man->flags = TTM_MEMTYPE_FLAG_FIXED |
162 TTM_MEMTYPE_FLAG_MAPPABLE;
163 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
164 man->default_caching = TTM_PL_FLAG_WC;
167 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
173 static void radeon_evict_flags(struct ttm_buffer_object *bo,
174 struct ttm_placement *placement)
176 struct radeon_bo *rbo;
177 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
179 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
182 placement->placement = &placements;
183 placement->busy_placement = &placements;
184 placement->num_placement = 1;
185 placement->num_busy_placement = 1;
188 rbo = container_of(bo, struct radeon_bo, tbo);
189 switch (bo->mem.mem_type) {
191 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
192 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
194 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
198 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
200 *placement = rbo->placement;
203 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
208 static void radeon_move_null(struct ttm_buffer_object *bo,
209 struct ttm_mem_reg *new_mem)
211 struct ttm_mem_reg *old_mem = &bo->mem;
213 BUG_ON(old_mem->mm_node != NULL);
215 new_mem->mm_node = NULL;
218 static int radeon_move_blit(struct ttm_buffer_object *bo,
219 bool evict, int no_wait_reserve, bool no_wait_gpu,
220 struct ttm_mem_reg *new_mem,
221 struct ttm_mem_reg *old_mem)
223 struct radeon_device *rdev;
224 uint64_t old_start, new_start;
225 struct radeon_fence *fence, *old_fence;
226 struct radeon_semaphore *sem = NULL;
229 rdev = radeon_get_rdev(bo->bdev);
230 r = radeon_fence_create(rdev, &fence, radeon_copy_ring_index(rdev));
234 old_start = old_mem->start << PAGE_SHIFT;
235 new_start = new_mem->start << PAGE_SHIFT;
237 switch (old_mem->mem_type) {
239 old_start += rdev->mc.vram_start;
242 old_start += rdev->mc.gtt_start;
245 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
246 radeon_fence_unref(&fence);
249 switch (new_mem->mem_type) {
251 new_start += rdev->mc.vram_start;
254 new_start += rdev->mc.gtt_start;
257 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
258 radeon_fence_unref(&fence);
261 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready) {
262 DRM_ERROR("Trying to move memory with ring turned off.\n");
263 radeon_fence_unref(&fence);
267 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
269 /* sync other rings */
270 old_fence = bo->sync_obj;
271 if (old_fence && old_fence->ring != fence->ring
272 && !radeon_fence_signaled(old_fence)) {
273 bool sync_to_ring[RADEON_NUM_RINGS] = { };
274 sync_to_ring[old_fence->ring] = true;
276 r = radeon_semaphore_create(rdev, &sem);
278 radeon_fence_unref(&fence);
282 r = radeon_semaphore_sync_rings(rdev, sem,
283 sync_to_ring, fence->ring);
285 radeon_semaphore_free(rdev, sem, NULL);
286 radeon_fence_unref(&fence);
291 r = radeon_copy(rdev, old_start, new_start,
292 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
294 /* FIXME: handle copy error */
295 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
296 evict, no_wait_reserve, no_wait_gpu, new_mem);
297 radeon_semaphore_free(rdev, sem, fence);
298 radeon_fence_unref(&fence);
302 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
303 bool evict, bool interruptible,
304 bool no_wait_reserve, bool no_wait_gpu,
305 struct ttm_mem_reg *new_mem)
307 struct radeon_device *rdev;
308 struct ttm_mem_reg *old_mem = &bo->mem;
309 struct ttm_mem_reg tmp_mem;
311 struct ttm_placement placement;
314 rdev = radeon_get_rdev(bo->bdev);
316 tmp_mem.mm_node = NULL;
319 placement.num_placement = 1;
320 placement.placement = &placements;
321 placement.num_busy_placement = 1;
322 placement.busy_placement = &placements;
323 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
324 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
325 interruptible, no_wait_reserve, no_wait_gpu);
330 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
335 r = ttm_tt_bind(bo->ttm, &tmp_mem);
339 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
343 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
345 ttm_bo_mem_put(bo, &tmp_mem);
349 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
350 bool evict, bool interruptible,
351 bool no_wait_reserve, bool no_wait_gpu,
352 struct ttm_mem_reg *new_mem)
354 struct radeon_device *rdev;
355 struct ttm_mem_reg *old_mem = &bo->mem;
356 struct ttm_mem_reg tmp_mem;
357 struct ttm_placement placement;
361 rdev = radeon_get_rdev(bo->bdev);
363 tmp_mem.mm_node = NULL;
366 placement.num_placement = 1;
367 placement.placement = &placements;
368 placement.num_busy_placement = 1;
369 placement.busy_placement = &placements;
370 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
371 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
375 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
379 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
384 ttm_bo_mem_put(bo, &tmp_mem);
388 static int radeon_bo_move(struct ttm_buffer_object *bo,
389 bool evict, bool interruptible,
390 bool no_wait_reserve, bool no_wait_gpu,
391 struct ttm_mem_reg *new_mem)
393 struct radeon_device *rdev;
394 struct ttm_mem_reg *old_mem = &bo->mem;
397 rdev = radeon_get_rdev(bo->bdev);
398 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
399 radeon_move_null(bo, new_mem);
402 if ((old_mem->mem_type == TTM_PL_TT &&
403 new_mem->mem_type == TTM_PL_SYSTEM) ||
404 (old_mem->mem_type == TTM_PL_SYSTEM &&
405 new_mem->mem_type == TTM_PL_TT)) {
407 radeon_move_null(bo, new_mem);
410 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
411 rdev->asic->copy.copy == NULL) {
416 if (old_mem->mem_type == TTM_PL_VRAM &&
417 new_mem->mem_type == TTM_PL_SYSTEM) {
418 r = radeon_move_vram_ram(bo, evict, interruptible,
419 no_wait_reserve, no_wait_gpu, new_mem);
420 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
421 new_mem->mem_type == TTM_PL_VRAM) {
422 r = radeon_move_ram_vram(bo, evict, interruptible,
423 no_wait_reserve, no_wait_gpu, new_mem);
425 r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
430 r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
435 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
437 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
438 struct radeon_device *rdev = radeon_get_rdev(bdev);
440 mem->bus.addr = NULL;
442 mem->bus.size = mem->num_pages << PAGE_SHIFT;
444 mem->bus.is_iomem = false;
445 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
447 switch (mem->mem_type) {
453 if (rdev->flags & RADEON_IS_AGP) {
454 /* RADEON_IS_AGP is set only if AGP is active */
455 mem->bus.offset = mem->start << PAGE_SHIFT;
456 mem->bus.base = rdev->mc.agp_base;
457 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
462 mem->bus.offset = mem->start << PAGE_SHIFT;
463 /* check if it's visible */
464 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
466 mem->bus.base = rdev->mc.aper_base;
467 mem->bus.is_iomem = true;
470 * Alpha: use bus.addr to hold the ioremap() return,
471 * so we can modify bus.base below.
473 if (mem->placement & TTM_PL_FLAG_WC)
475 ioremap_wc(mem->bus.base + mem->bus.offset,
479 ioremap_nocache(mem->bus.base + mem->bus.offset,
483 * Alpha: Use just the bus offset plus
484 * the hose/domain memory base for bus.base.
485 * It then can be used to build PTEs for VRAM
486 * access, as done in ttm_bo_vm_fault().
488 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
489 rdev->ddev->hose->dense_mem_base;
498 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
502 static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
503 bool lazy, bool interruptible)
505 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
508 static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
513 static void radeon_sync_obj_unref(void **sync_obj)
515 radeon_fence_unref((struct radeon_fence **)sync_obj);
518 static void *radeon_sync_obj_ref(void *sync_obj)
520 return radeon_fence_ref((struct radeon_fence *)sync_obj);
523 static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
525 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
529 * TTM backend functions.
531 struct radeon_ttm_tt {
532 struct ttm_dma_tt ttm;
533 struct radeon_device *rdev;
537 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
538 struct ttm_mem_reg *bo_mem)
540 struct radeon_ttm_tt *gtt = (void*)ttm;
543 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
544 if (!ttm->num_pages) {
545 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
546 ttm->num_pages, bo_mem, ttm);
548 r = radeon_gart_bind(gtt->rdev, gtt->offset,
549 ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
551 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
552 ttm->num_pages, (unsigned)gtt->offset);
558 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
560 struct radeon_ttm_tt *gtt = (void *)ttm;
562 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
566 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
568 struct radeon_ttm_tt *gtt = (void *)ttm;
570 ttm_dma_tt_fini(>t->ttm);
574 static struct ttm_backend_func radeon_backend_func = {
575 .bind = &radeon_ttm_backend_bind,
576 .unbind = &radeon_ttm_backend_unbind,
577 .destroy = &radeon_ttm_backend_destroy,
580 struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
581 unsigned long size, uint32_t page_flags,
582 struct page *dummy_read_page)
584 struct radeon_device *rdev;
585 struct radeon_ttm_tt *gtt;
587 rdev = radeon_get_rdev(bdev);
589 if (rdev->flags & RADEON_IS_AGP) {
590 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
591 size, page_flags, dummy_read_page);
595 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
599 gtt->ttm.ttm.func = &radeon_backend_func;
601 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
605 return >t->ttm.ttm;
608 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
610 struct radeon_device *rdev;
611 struct radeon_ttm_tt *gtt = (void *)ttm;
614 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
616 if (ttm->state != tt_unpopulated)
619 if (slave && ttm->sg) {
620 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
621 gtt->ttm.dma_address, ttm->num_pages);
622 ttm->state = tt_unbound;
626 rdev = radeon_get_rdev(ttm->bdev);
628 if (rdev->flags & RADEON_IS_AGP) {
629 return ttm_agp_tt_populate(ttm);
633 #ifdef CONFIG_SWIOTLB
634 if (swiotlb_nr_tbl()) {
635 return ttm_dma_populate(>t->ttm, rdev->dev);
639 r = ttm_pool_populate(ttm);
644 for (i = 0; i < ttm->num_pages; i++) {
645 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
647 PCI_DMA_BIDIRECTIONAL);
648 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
650 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
651 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
652 gtt->ttm.dma_address[i] = 0;
654 ttm_pool_unpopulate(ttm);
661 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
663 struct radeon_device *rdev;
664 struct radeon_ttm_tt *gtt = (void *)ttm;
666 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
671 rdev = radeon_get_rdev(ttm->bdev);
673 if (rdev->flags & RADEON_IS_AGP) {
674 ttm_agp_tt_unpopulate(ttm);
679 #ifdef CONFIG_SWIOTLB
680 if (swiotlb_nr_tbl()) {
681 ttm_dma_unpopulate(>t->ttm, rdev->dev);
686 for (i = 0; i < ttm->num_pages; i++) {
687 if (gtt->ttm.dma_address[i]) {
688 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
689 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
693 ttm_pool_unpopulate(ttm);
696 static struct ttm_bo_driver radeon_bo_driver = {
697 .ttm_tt_create = &radeon_ttm_tt_create,
698 .ttm_tt_populate = &radeon_ttm_tt_populate,
699 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
700 .invalidate_caches = &radeon_invalidate_caches,
701 .init_mem_type = &radeon_init_mem_type,
702 .evict_flags = &radeon_evict_flags,
703 .move = &radeon_bo_move,
704 .verify_access = &radeon_verify_access,
705 .sync_obj_signaled = &radeon_sync_obj_signaled,
706 .sync_obj_wait = &radeon_sync_obj_wait,
707 .sync_obj_flush = &radeon_sync_obj_flush,
708 .sync_obj_unref = &radeon_sync_obj_unref,
709 .sync_obj_ref = &radeon_sync_obj_ref,
710 .move_notify = &radeon_bo_move_notify,
711 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
712 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
713 .io_mem_free = &radeon_ttm_io_mem_free,
716 int radeon_ttm_init(struct radeon_device *rdev)
720 r = radeon_ttm_global_init(rdev);
724 /* No others user of address space so set it to 0 */
725 r = ttm_bo_device_init(&rdev->mman.bdev,
726 rdev->mman.bo_global_ref.ref.object,
727 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
730 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
733 rdev->mman.initialized = true;
734 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
735 rdev->mc.real_vram_size >> PAGE_SHIFT);
737 DRM_ERROR("Failed initializing VRAM heap.\n");
740 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
741 RADEON_GEM_DOMAIN_VRAM,
742 NULL, &rdev->stollen_vga_memory);
746 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
749 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
750 radeon_bo_unreserve(rdev->stollen_vga_memory);
752 radeon_bo_unref(&rdev->stollen_vga_memory);
755 DRM_INFO("radeon: %uM of VRAM memory ready\n",
756 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
757 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
758 rdev->mc.gtt_size >> PAGE_SHIFT);
760 DRM_ERROR("Failed initializing GTT heap.\n");
763 DRM_INFO("radeon: %uM of GTT memory ready.\n",
764 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
765 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
766 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
769 r = radeon_ttm_debugfs_init(rdev);
771 DRM_ERROR("Failed to init debugfs\n");
777 void radeon_ttm_fini(struct radeon_device *rdev)
781 if (!rdev->mman.initialized)
783 if (rdev->stollen_vga_memory) {
784 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
786 radeon_bo_unpin(rdev->stollen_vga_memory);
787 radeon_bo_unreserve(rdev->stollen_vga_memory);
789 radeon_bo_unref(&rdev->stollen_vga_memory);
791 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
792 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
793 ttm_bo_device_release(&rdev->mman.bdev);
794 radeon_gart_fini(rdev);
795 radeon_ttm_global_fini(rdev);
796 rdev->mman.initialized = false;
797 DRM_INFO("radeon: ttm finalized\n");
800 /* this should only be called at bootup or when userspace
802 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
804 struct ttm_mem_type_manager *man;
806 if (!rdev->mman.initialized)
809 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
810 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
811 man->size = size >> PAGE_SHIFT;
814 static struct vm_operations_struct radeon_ttm_vm_ops;
815 static const struct vm_operations_struct *ttm_vm_ops = NULL;
817 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
819 struct ttm_buffer_object *bo;
820 struct radeon_device *rdev;
823 bo = (struct ttm_buffer_object *)vma->vm_private_data;
825 return VM_FAULT_NOPAGE;
827 rdev = radeon_get_rdev(bo->bdev);
828 mutex_lock(&rdev->vram_mutex);
829 r = ttm_vm_ops->fault(vma, vmf);
830 mutex_unlock(&rdev->vram_mutex);
834 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
836 struct drm_file *file_priv;
837 struct radeon_device *rdev;
840 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
841 return drm_mmap(filp, vma);
844 file_priv = filp->private_data;
845 rdev = file_priv->minor->dev->dev_private;
849 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
850 if (unlikely(r != 0)) {
853 if (unlikely(ttm_vm_ops == NULL)) {
854 ttm_vm_ops = vma->vm_ops;
855 radeon_ttm_vm_ops = *ttm_vm_ops;
856 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
858 vma->vm_ops = &radeon_ttm_vm_ops;
863 #define RADEON_DEBUGFS_MEM_TYPES 2
865 #if defined(CONFIG_DEBUG_FS)
866 static int radeon_mm_dump_table(struct seq_file *m, void *data)
868 struct drm_info_node *node = (struct drm_info_node *)m->private;
869 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
870 struct drm_device *dev = node->minor->dev;
871 struct radeon_device *rdev = dev->dev_private;
873 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
875 spin_lock(&glob->lru_lock);
876 ret = drm_mm_dump_table(m, mm);
877 spin_unlock(&glob->lru_lock);
882 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
884 #if defined(CONFIG_DEBUG_FS)
885 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2];
886 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32];
889 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
891 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
893 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
894 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
895 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
896 radeon_mem_types_list[i].driver_features = 0;
898 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
900 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
903 /* Add ttm page pool to debugfs */
904 sprintf(radeon_mem_types_names[i], "ttm_page_pool");
905 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
906 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
907 radeon_mem_types_list[i].driver_features = 0;
908 radeon_mem_types_list[i++].data = NULL;
909 #ifdef CONFIG_SWIOTLB
910 if (swiotlb_nr_tbl()) {
911 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool");
912 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
913 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs;
914 radeon_mem_types_list[i].driver_features = 0;
915 radeon_mem_types_list[i++].data = NULL;
918 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);