2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
39 /* 1 second timeout */
40 #define UVD_IDLE_TIMEOUT_MS 1000
43 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
44 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
45 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
46 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
47 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
49 MODULE_FIRMWARE(FIRMWARE_RV710);
50 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
51 MODULE_FIRMWARE(FIRMWARE_SUMO);
52 MODULE_FIRMWARE(FIRMWARE_TAHITI);
53 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
55 static void radeon_uvd_idle_work_handler(struct work_struct *work);
57 int radeon_uvd_init(struct radeon_device *rdev)
59 unsigned long bo_size;
63 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
65 switch (rdev->family) {
69 fw_name = FIRMWARE_RV710;
77 fw_name = FIRMWARE_CYPRESS;
87 fw_name = FIRMWARE_SUMO;
94 fw_name = FIRMWARE_TAHITI;
100 fw_name = FIRMWARE_BONAIRE;
107 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
114 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
115 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
116 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
117 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
119 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
123 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
125 radeon_bo_unref(&rdev->uvd.vcpu_bo);
126 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
130 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
131 &rdev->uvd.gpu_addr);
133 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
134 radeon_bo_unref(&rdev->uvd.vcpu_bo);
135 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
139 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
141 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
145 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
147 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
148 atomic_set(&rdev->uvd.handles[i], 0);
149 rdev->uvd.filp[i] = NULL;
150 rdev->uvd.img_size[i] = 0;
156 void radeon_uvd_fini(struct radeon_device *rdev)
160 if (rdev->uvd.vcpu_bo == NULL)
163 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
165 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
166 radeon_bo_unpin(rdev->uvd.vcpu_bo);
167 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
170 radeon_bo_unref(&rdev->uvd.vcpu_bo);
172 release_firmware(rdev->uvd_fw);
175 int radeon_uvd_suspend(struct radeon_device *rdev)
181 if (rdev->uvd.vcpu_bo == NULL)
184 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
185 if (atomic_read(&rdev->uvd.handles[i]))
188 if (i == RADEON_MAX_UVD_HANDLES)
191 size = radeon_bo_size(rdev->uvd.vcpu_bo);
192 size -= rdev->uvd_fw->size;
194 ptr = rdev->uvd.cpu_addr;
195 ptr += rdev->uvd_fw->size;
197 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
198 memcpy(rdev->uvd.saved_bo, ptr, size);
203 int radeon_uvd_resume(struct radeon_device *rdev)
208 if (rdev->uvd.vcpu_bo == NULL)
211 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
213 size = radeon_bo_size(rdev->uvd.vcpu_bo);
214 size -= rdev->uvd_fw->size;
216 ptr = rdev->uvd.cpu_addr;
217 ptr += rdev->uvd_fw->size;
219 if (rdev->uvd.saved_bo != NULL) {
220 memcpy(ptr, rdev->uvd.saved_bo, size);
221 kfree(rdev->uvd.saved_bo);
222 rdev->uvd.saved_bo = NULL;
224 memset(ptr, 0, size);
229 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
231 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
232 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
235 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
238 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
239 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
240 if (handle != 0 && rdev->uvd.filp[i] == filp) {
241 struct radeon_fence *fence;
243 r = radeon_uvd_get_destroy_msg(rdev,
244 R600_RING_TYPE_UVD_INDEX, handle, &fence);
246 DRM_ERROR("Error destroying UVD (%d)!\n", r);
250 radeon_fence_wait(fence, false);
251 radeon_fence_unref(&fence);
253 rdev->uvd.filp[i] = NULL;
254 atomic_set(&rdev->uvd.handles[i], 0);
259 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
261 unsigned stream_type = msg[4];
262 unsigned width = msg[6];
263 unsigned height = msg[7];
264 unsigned dpb_size = msg[9];
265 unsigned pitch = msg[28];
267 unsigned width_in_mb = width / 16;
268 unsigned height_in_mb = ALIGN(height / 16, 2);
270 unsigned image_size, tmp, min_dpb_size;
272 image_size = width * height;
273 image_size += image_size / 2;
274 image_size = ALIGN(image_size, 1024);
276 switch (stream_type) {
279 /* reference picture buffer */
280 min_dpb_size = image_size * 17;
282 /* macroblock context buffer */
283 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
285 /* IT surface buffer */
286 min_dpb_size += width_in_mb * height_in_mb * 32;
291 /* reference picture buffer */
292 min_dpb_size = image_size * 3;
295 min_dpb_size += width_in_mb * height_in_mb * 128;
297 /* IT surface buffer */
298 min_dpb_size += width_in_mb * 64;
300 /* DB surface buffer */
301 min_dpb_size += width_in_mb * 128;
304 tmp = max(width_in_mb, height_in_mb);
305 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
310 /* reference picture buffer */
311 min_dpb_size = image_size * 3;
316 /* reference picture buffer */
317 min_dpb_size = image_size * 3;
320 min_dpb_size += width_in_mb * height_in_mb * 64;
322 /* IT surface buffer */
323 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
327 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
332 DRM_ERROR("Invalid UVD decoding target pitch!\n");
336 if (dpb_size < min_dpb_size) {
337 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
338 dpb_size, min_dpb_size);
342 buf_sizes[0x1] = dpb_size;
343 buf_sizes[0x2] = image_size;
347 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
348 unsigned offset, unsigned buf_sizes[])
350 int32_t *msg, msg_type, handle;
351 unsigned img_size = 0;
357 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
361 if (bo->tbo.sync_obj) {
362 r = radeon_fence_wait(bo->tbo.sync_obj, false);
364 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
369 r = radeon_bo_kmap(bo, &ptr);
371 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
381 DRM_ERROR("Invalid UVD handle!\n");
386 /* it's a decode msg, calc buffer sizes */
387 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
388 /* calc image size (width * height) */
389 img_size = msg[6] * msg[7];
390 radeon_bo_kunmap(bo);
394 } else if (msg_type == 2) {
395 /* it's a destroy msg, free the handle */
396 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
397 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
398 radeon_bo_kunmap(bo);
401 /* it's a create msg, calc image size (width * height) */
402 img_size = msg[7] * msg[8];
403 radeon_bo_kunmap(bo);
406 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
410 /* it's a create msg, no special handling needed */
413 /* create or decode, validate the handle */
414 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
415 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
419 /* handle not found try to alloc a new one */
420 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
421 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
422 p->rdev->uvd.filp[i] = p->filp;
423 p->rdev->uvd.img_size[i] = img_size;
428 DRM_ERROR("No more free UVD handles!\n");
432 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
433 int data0, int data1,
434 unsigned buf_sizes[], bool *has_msg_cmd)
436 struct radeon_cs_chunk *relocs_chunk;
437 struct radeon_cs_reloc *reloc;
438 unsigned idx, cmd, offset;
442 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
443 offset = radeon_get_ib_value(p, data0);
444 idx = radeon_get_ib_value(p, data1);
445 if (idx >= relocs_chunk->length_dw) {
446 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
447 idx, relocs_chunk->length_dw);
451 reloc = p->relocs_ptr[(idx / 4)];
452 start = reloc->lobj.gpu_offset;
453 end = start + radeon_bo_size(reloc->robj);
456 p->ib.ptr[data0] = start & 0xFFFFFFFF;
457 p->ib.ptr[data1] = start >> 32;
459 cmd = radeon_get_ib_value(p, p->idx) >> 1;
462 if ((end - start) < buf_sizes[cmd]) {
463 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
464 (unsigned)(end - start), buf_sizes[cmd]);
468 } else if (cmd != 0x100) {
469 DRM_ERROR("invalid UVD command %X!\n", cmd);
473 if ((start >> 28) != (end >> 28)) {
474 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
479 /* TODO: is this still necessary on NI+ ? */
480 if ((cmd == 0 || cmd == 0x3) &&
481 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
482 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
489 DRM_ERROR("More than one message in a UVD-IB!\n");
493 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
496 } else if (!*has_msg_cmd) {
497 DRM_ERROR("Message needed before other commands are send!\n");
504 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
505 struct radeon_cs_packet *pkt,
506 int *data0, int *data1,
507 unsigned buf_sizes[],
513 for (i = 0; i <= pkt->count; ++i) {
514 switch (pkt->reg + i*4) {
515 case UVD_GPCOM_VCPU_DATA0:
518 case UVD_GPCOM_VCPU_DATA1:
521 case UVD_GPCOM_VCPU_CMD:
522 r = radeon_uvd_cs_reloc(p, *data0, *data1,
523 buf_sizes, has_msg_cmd);
527 case UVD_ENGINE_CNTL:
530 DRM_ERROR("Invalid reg 0x%X!\n",
539 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
541 struct radeon_cs_packet pkt;
542 int r, data0 = 0, data1 = 0;
544 /* does the IB has a msg command */
545 bool has_msg_cmd = false;
547 /* minimum buffer sizes */
548 unsigned buf_sizes[] = {
550 [0x00000001] = 32 * 1024 * 1024,
551 [0x00000002] = 2048 * 1152 * 3,
555 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
556 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
557 p->chunks[p->chunk_ib_idx].length_dw);
561 if (p->chunk_relocs_idx == -1) {
562 DRM_ERROR("No relocation chunk !\n");
568 r = radeon_cs_packet_parse(p, &pkt, p->idx);
572 case RADEON_PACKET_TYPE0:
573 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
574 buf_sizes, &has_msg_cmd);
578 case RADEON_PACKET_TYPE2:
579 p->idx += pkt.count + 2;
582 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
585 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
588 DRM_ERROR("UVD-IBs need a msg command!\n");
595 static int radeon_uvd_send_msg(struct radeon_device *rdev,
596 int ring, struct radeon_bo *bo,
597 struct radeon_fence **fence)
599 struct ttm_validate_buffer tv;
600 struct ww_acquire_ctx ticket;
601 struct list_head head;
606 memset(&tv, 0, sizeof(tv));
609 INIT_LIST_HEAD(&head);
610 list_add(&tv.head, &head);
612 r = ttm_eu_reserve_buffers(&ticket, &head);
616 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
617 radeon_uvd_force_into_uvd_segment(bo);
619 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
623 r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
627 addr = radeon_bo_gpu_offset(bo);
628 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
630 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
631 ib.ptr[3] = addr >> 32;
632 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
634 for (i = 6; i < 16; ++i)
635 ib.ptr[i] = PACKET2(0);
638 r = radeon_ib_schedule(rdev, &ib, NULL);
641 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
644 *fence = radeon_fence_ref(ib.fence);
646 radeon_ib_free(rdev, &ib);
647 radeon_bo_unref(&bo);
651 ttm_eu_backoff_reservation(&ticket, &head);
655 /* multiple fence commands without any stream commands in between can
656 crash the vcpu so just try to emmit a dummy create/destroy msg to
658 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
659 uint32_t handle, struct radeon_fence **fence)
661 struct radeon_bo *bo;
665 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
666 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
670 r = radeon_bo_reserve(bo, false);
672 radeon_bo_unref(&bo);
676 r = radeon_bo_kmap(bo, (void **)&msg);
678 radeon_bo_unreserve(bo);
679 radeon_bo_unref(&bo);
683 /* stitch together an UVD create msg */
684 msg[0] = cpu_to_le32(0x00000de4);
685 msg[1] = cpu_to_le32(0x00000000);
686 msg[2] = cpu_to_le32(handle);
687 msg[3] = cpu_to_le32(0x00000000);
688 msg[4] = cpu_to_le32(0x00000000);
689 msg[5] = cpu_to_le32(0x00000000);
690 msg[6] = cpu_to_le32(0x00000000);
691 msg[7] = cpu_to_le32(0x00000780);
692 msg[8] = cpu_to_le32(0x00000440);
693 msg[9] = cpu_to_le32(0x00000000);
694 msg[10] = cpu_to_le32(0x01b37000);
695 for (i = 11; i < 1024; ++i)
696 msg[i] = cpu_to_le32(0x0);
698 radeon_bo_kunmap(bo);
699 radeon_bo_unreserve(bo);
701 return radeon_uvd_send_msg(rdev, ring, bo, fence);
704 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
705 uint32_t handle, struct radeon_fence **fence)
707 struct radeon_bo *bo;
711 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
712 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
716 r = radeon_bo_reserve(bo, false);
718 radeon_bo_unref(&bo);
722 r = radeon_bo_kmap(bo, (void **)&msg);
724 radeon_bo_unreserve(bo);
725 radeon_bo_unref(&bo);
729 /* stitch together an UVD destroy msg */
730 msg[0] = cpu_to_le32(0x00000de4);
731 msg[1] = cpu_to_le32(0x00000002);
732 msg[2] = cpu_to_le32(handle);
733 msg[3] = cpu_to_le32(0x00000000);
734 for (i = 4; i < 1024; ++i)
735 msg[i] = cpu_to_le32(0x0);
737 radeon_bo_kunmap(bo);
738 radeon_bo_unreserve(bo);
740 return radeon_uvd_send_msg(rdev, ring, bo, fence);
744 * radeon_uvd_count_handles - count number of open streams
746 * @rdev: radeon_device pointer
747 * @sd: number of SD streams
748 * @hd: number of HD streams
750 * Count the number of open SD/HD streams as a hint for power mangement
752 static void radeon_uvd_count_handles(struct radeon_device *rdev,
753 unsigned *sd, unsigned *hd)
760 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
761 if (!atomic_read(&rdev->uvd.handles[i]))
764 if (rdev->uvd.img_size[i] >= 720*576)
771 static void radeon_uvd_idle_work_handler(struct work_struct *work)
773 struct radeon_device *rdev =
774 container_of(work, struct radeon_device, uvd.idle_work.work);
776 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
777 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
778 radeon_dpm_enable_uvd(rdev, false);
780 radeon_set_uvd_clocks(rdev, 0, 0);
783 schedule_delayed_work(&rdev->uvd.idle_work,
784 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
788 void radeon_uvd_note_usage(struct radeon_device *rdev)
790 bool streams_changed = false;
791 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
792 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
793 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
795 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
796 unsigned hd = 0, sd = 0;
797 radeon_uvd_count_handles(rdev, &sd, &hd);
798 if ((rdev->pm.dpm.sd != sd) ||
799 (rdev->pm.dpm.hd != hd)) {
800 rdev->pm.dpm.sd = sd;
801 rdev->pm.dpm.hd = hd;
802 /* disable this for now */
803 /*streams_changed = true;*/
807 if (set_clocks || streams_changed) {
808 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
809 radeon_dpm_enable_uvd(rdev, true);
811 radeon_set_uvd_clocks(rdev, 53300, 40000);
816 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
817 unsigned target_freq,
821 unsigned post_div = vco_freq / target_freq;
823 /* adjust to post divider minimum value */
824 if (post_div < pd_min)
827 /* we alway need a frequency less than or equal the target */
828 if ((vco_freq / post_div) > target_freq)
831 /* post dividers above a certain value must be even */
832 if (post_div > pd_even && post_div % 2)
839 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
841 * @rdev: radeon_device pointer
844 * @vco_min: minimum VCO frequency
845 * @vco_max: maximum VCO frequency
846 * @fb_factor: factor to multiply vco freq with
847 * @fb_mask: limit and bitmask for feedback divider
848 * @pd_min: post divider minimum
849 * @pd_max: post divider maximum
850 * @pd_even: post divider must be even above this value
851 * @optimal_fb_div: resulting feedback divider
852 * @optimal_vclk_div: resulting vclk post divider
853 * @optimal_dclk_div: resulting dclk post divider
855 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
856 * Returns zero on success -EINVAL on error.
858 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
859 unsigned vclk, unsigned dclk,
860 unsigned vco_min, unsigned vco_max,
861 unsigned fb_factor, unsigned fb_mask,
862 unsigned pd_min, unsigned pd_max,
864 unsigned *optimal_fb_div,
865 unsigned *optimal_vclk_div,
866 unsigned *optimal_dclk_div)
868 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
870 /* start off with something large */
871 unsigned optimal_score = ~0;
873 /* loop through vco from low to high */
874 vco_min = max(max(vco_min, vclk), dclk);
875 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
877 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
878 unsigned vclk_div, dclk_div, score;
880 do_div(fb_div, ref_freq);
882 /* fb div out of range ? */
883 if (fb_div > fb_mask)
884 break; /* it can oly get worse */
888 /* calc vclk divider with current vco freq */
889 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
891 if (vclk_div > pd_max)
892 break; /* vco is too big, it has to stop */
894 /* calc dclk divider with current vco freq */
895 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
897 if (vclk_div > pd_max)
898 break; /* vco is too big, it has to stop */
900 /* calc score with current vco freq */
901 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
903 /* determine if this vco setting is better than current optimal settings */
904 if (score < optimal_score) {
905 *optimal_fb_div = fb_div;
906 *optimal_vclk_div = vclk_div;
907 *optimal_dclk_div = dclk_div;
908 optimal_score = score;
909 if (optimal_score == 0)
910 break; /* it can't get better than this */
914 /* did we found a valid setup ? */
915 if (optimal_score == ~0)
921 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
922 unsigned cg_upll_func_cntl)
926 /* make sure UPLL_CTLREQ is deasserted */
927 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
931 /* assert UPLL_CTLREQ */
932 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
934 /* wait for CTLACK and CTLACK2 to get asserted */
935 for (i = 0; i < 100; ++i) {
936 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
937 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
942 /* deassert UPLL_CTLREQ */
943 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
946 DRM_ERROR("Timeout setting UVD clocks!\n");