2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
62 return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device *rdev)
89 if (!rdev->vm_manager.enabled) {
90 r = radeon_asic_vm_init(rdev);
94 rdev->vm_manager.enabled = true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
110 if (!rdev->vm_manager.enabled)
113 for (i = 0; i < RADEON_NUM_VM; ++i)
114 radeon_fence_unref(&rdev->vm_manager.active[i]);
115 radeon_asic_vm_fini(rdev);
116 rdev->vm_manager.enabled = false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
129 struct radeon_vm *vm,
130 struct list_head *head)
132 struct radeon_cs_reloc *list;
133 unsigned i, idx, size;
135 size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_cs_reloc);
136 list = kmalloc(size, GFP_KERNEL);
140 /* add the vm page table to the list */
142 list[0].robj = vm->page_directory;
143 list[0].domain = RADEON_GEM_DOMAIN_VRAM;
144 list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM;
145 list[0].tv.bo = &vm->page_directory->tbo;
146 list[0].tiling_flags = 0;
148 list_add(&list[0].tv.head, head);
150 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
151 if (!vm->page_tables[i].bo)
154 list[idx].gobj = NULL;
155 list[idx].robj = vm->page_tables[i].bo;
156 list[idx].domain = RADEON_GEM_DOMAIN_VRAM;
157 list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM;
158 list[idx].tv.bo = &list[idx].robj->tbo;
159 list[idx].tiling_flags = 0;
160 list[idx].handle = 0;
161 list_add(&list[idx++].tv.head, head);
168 * radeon_vm_grab_id - allocate the next free VMID
170 * @rdev: radeon_device pointer
171 * @vm: vm to allocate id for
172 * @ring: ring we want to submit job to
174 * Allocate an id for the vm (cayman+).
175 * Returns the fence we need to sync to (if any).
177 * Global and local mutex must be locked!
179 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
180 struct radeon_vm *vm, int ring)
182 struct radeon_fence *best[RADEON_NUM_RINGS] = {};
183 unsigned choices[2] = {};
186 /* check if the id is still valid */
187 if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
190 /* we definately need to flush */
191 radeon_fence_unref(&vm->last_flush);
193 /* skip over VMID 0, since it is the system VM */
194 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
195 struct radeon_fence *fence = rdev->vm_manager.active[i];
198 /* found a free one */
200 trace_radeon_vm_grab_id(vm->id, ring);
204 if (radeon_fence_is_earlier(fence, best[fence->ring])) {
205 best[fence->ring] = fence;
206 choices[fence->ring == ring ? 0 : 1] = i;
210 for (i = 0; i < 2; ++i) {
213 trace_radeon_vm_grab_id(vm->id, ring);
214 return rdev->vm_manager.active[choices[i]];
218 /* should never happen */
224 * radeon_vm_flush - hardware flush the vm
226 * @rdev: radeon_device pointer
227 * @vm: vm we want to flush
228 * @ring: ring to use for flush
230 * Flush the vm (cayman+).
232 * Global and local mutex must be locked!
234 void radeon_vm_flush(struct radeon_device *rdev,
235 struct radeon_vm *vm,
238 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
240 /* if we can't remember our last VM flush then flush now! */
241 /* XXX figure out why we have to flush all the time */
242 if (!vm->last_flush || true || pd_addr != vm->pd_gpu_addr) {
243 vm->pd_gpu_addr = pd_addr;
244 radeon_ring_vm_flush(rdev, ring, vm);
249 * radeon_vm_fence - remember fence for vm
251 * @rdev: radeon_device pointer
252 * @vm: vm we want to fence
253 * @fence: fence to remember
255 * Fence the vm (cayman+).
256 * Set the fence used to protect page table and id.
258 * Global and local mutex must be locked!
260 void radeon_vm_fence(struct radeon_device *rdev,
261 struct radeon_vm *vm,
262 struct radeon_fence *fence)
264 radeon_fence_unref(&vm->fence);
265 vm->fence = radeon_fence_ref(fence);
267 radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
268 rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
270 radeon_fence_unref(&vm->last_id_use);
271 vm->last_id_use = radeon_fence_ref(fence);
273 /* we just flushed the VM, remember that */
275 vm->last_flush = radeon_fence_ref(fence);
279 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
282 * @bo: requested buffer object
284 * Find @bo inside the requested vm (cayman+).
285 * Search inside the @bos vm list for the requested vm
286 * Returns the found bo_va or NULL if none is found
288 * Object has to be reserved!
290 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
291 struct radeon_bo *bo)
293 struct radeon_bo_va *bo_va;
295 list_for_each_entry(bo_va, &bo->va, bo_list) {
296 if (bo_va->vm == vm) {
304 * radeon_vm_bo_add - add a bo to a specific vm
306 * @rdev: radeon_device pointer
308 * @bo: radeon buffer object
310 * Add @bo into the requested vm (cayman+).
311 * Add @bo to the list of bos associated with the vm
312 * Returns newly added bo_va or NULL for failure
314 * Object has to be reserved!
316 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
317 struct radeon_vm *vm,
318 struct radeon_bo *bo)
320 struct radeon_bo_va *bo_va;
322 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
331 bo_va->valid = false;
332 bo_va->ref_count = 1;
333 INIT_LIST_HEAD(&bo_va->bo_list);
334 INIT_LIST_HEAD(&bo_va->vm_list);
336 mutex_lock(&vm->mutex);
337 list_add(&bo_va->vm_list, &vm->va);
338 list_add_tail(&bo_va->bo_list, &bo->va);
339 mutex_unlock(&vm->mutex);
345 * radeon_vm_clear_bo - initially clear the page dir/table
347 * @rdev: radeon_device pointer
350 static int radeon_vm_clear_bo(struct radeon_device *rdev,
351 struct radeon_bo *bo)
353 struct ttm_validate_buffer tv;
354 struct ww_acquire_ctx ticket;
355 struct list_head head;
361 memset(&tv, 0, sizeof(tv));
364 INIT_LIST_HEAD(&head);
365 list_add(&tv.head, &head);
367 r = ttm_eu_reserve_buffers(&ticket, &head);
371 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
375 addr = radeon_bo_gpu_offset(bo);
376 entries = radeon_bo_size(bo) / 8;
378 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib,
379 NULL, entries * 2 + 64);
385 radeon_asic_vm_set_page(rdev, &ib, addr, 0, entries, 0, 0);
387 r = radeon_ib_schedule(rdev, &ib, NULL);
391 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
392 radeon_ib_free(rdev, &ib);
397 ttm_eu_backoff_reservation(&ticket, &head);
402 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
404 * @rdev: radeon_device pointer
405 * @bo_va: bo_va to store the address
406 * @soffset: requested offset of the buffer in the VM address space
407 * @flags: attributes of pages (read/write/valid/etc.)
409 * Set offset of @bo_va (cayman+).
410 * Validate and set the offset requested within the vm address space.
411 * Returns 0 for success, error for failure.
413 * Object has to be reserved!
415 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
416 struct radeon_bo_va *bo_va,
420 uint64_t size = radeon_bo_size(bo_va->bo);
421 uint64_t eoffset, last_offset = 0;
422 struct radeon_vm *vm = bo_va->vm;
423 struct radeon_bo_va *tmp;
424 struct list_head *head;
425 unsigned last_pfn, pt_idx;
429 /* make sure object fit at this offset */
430 eoffset = soffset + size;
431 if (soffset >= eoffset) {
435 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
436 if (last_pfn > rdev->vm_manager.max_pfn) {
437 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
438 last_pfn, rdev->vm_manager.max_pfn);
443 eoffset = last_pfn = 0;
446 mutex_lock(&vm->mutex);
449 list_for_each_entry(tmp, &vm->va, vm_list) {
451 /* skip over currently modified bo */
455 if (soffset >= last_offset && eoffset <= tmp->soffset) {
456 /* bo can be added before this one */
459 if (eoffset > tmp->soffset && soffset < tmp->eoffset) {
460 /* bo and tmp overlap, invalid offset */
461 dev_err(rdev->dev, "bo %p va 0x%08X conflict with (bo %p 0x%08X 0x%08X)\n",
462 bo_va->bo, (unsigned)bo_va->soffset, tmp->bo,
463 (unsigned)tmp->soffset, (unsigned)tmp->eoffset);
464 mutex_unlock(&vm->mutex);
467 last_offset = tmp->eoffset;
468 head = &tmp->vm_list;
471 bo_va->soffset = soffset;
472 bo_va->eoffset = eoffset;
473 bo_va->flags = flags;
474 bo_va->valid = false;
475 list_move(&bo_va->vm_list, head);
477 soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
478 eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
480 if (eoffset > vm->max_pde_used)
481 vm->max_pde_used = eoffset;
483 radeon_bo_unreserve(bo_va->bo);
485 /* walk over the address space and allocate the page tables */
486 for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
487 struct radeon_bo *pt;
489 if (vm->page_tables[pt_idx].bo)
492 /* drop mutex to allocate and clear page table */
493 mutex_unlock(&vm->mutex);
495 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
496 RADEON_GPU_PAGE_SIZE, false,
497 RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
501 r = radeon_vm_clear_bo(rdev, pt);
503 radeon_bo_unref(&pt);
504 radeon_bo_reserve(bo_va->bo, false);
508 /* aquire mutex again */
509 mutex_lock(&vm->mutex);
510 if (vm->page_tables[pt_idx].bo) {
511 /* someone else allocated the pt in the meantime */
512 mutex_unlock(&vm->mutex);
513 radeon_bo_unref(&pt);
514 mutex_lock(&vm->mutex);
518 vm->page_tables[pt_idx].addr = 0;
519 vm->page_tables[pt_idx].bo = pt;
522 mutex_unlock(&vm->mutex);
523 return radeon_bo_reserve(bo_va->bo, false);
527 * radeon_vm_map_gart - get the physical address of a gart page
529 * @rdev: radeon_device pointer
530 * @addr: the unmapped addr
532 * Look up the physical address of the page that the pte resolves
534 * Returns the physical address of the page.
536 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
540 /* page table offset */
541 result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
543 /* in case cpu page size != gpu page size*/
544 result |= addr & (~PAGE_MASK);
550 * radeon_vm_page_flags - translate page flags to what the hw uses
552 * @flags: flags comming from userspace
554 * Translate the flags the userspace ABI uses to hw flags.
556 static uint32_t radeon_vm_page_flags(uint32_t flags)
558 uint32_t hw_flags = 0;
559 hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
560 hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
561 hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
562 if (flags & RADEON_VM_PAGE_SYSTEM) {
563 hw_flags |= R600_PTE_SYSTEM;
564 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
570 * radeon_vm_update_pdes - make sure that page directory is valid
572 * @rdev: radeon_device pointer
574 * @start: start of GPU address range
575 * @end: end of GPU address range
577 * Allocates new page tables if necessary
578 * and updates the page directory (cayman+).
579 * Returns 0 for success, error for failure.
581 * Global and local mutex must be locked!
583 int radeon_vm_update_page_directory(struct radeon_device *rdev,
584 struct radeon_vm *vm)
586 static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
588 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
589 uint64_t last_pde = ~0, last_pt = ~0;
590 unsigned count = 0, pt_idx, ndw;
597 /* assume the worst case */
598 ndw += vm->max_pde_used * 12;
600 /* update too big for an IB */
604 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
609 /* walk over the address space and update the page directory */
610 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
611 struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
617 pt = radeon_bo_gpu_offset(bo);
618 if (vm->page_tables[pt_idx].addr == pt)
620 vm->page_tables[pt_idx].addr = pt;
622 pde = pd_addr + pt_idx * 8;
623 if (((last_pde + 8 * count) != pde) ||
624 ((last_pt + incr * count) != pt)) {
627 radeon_asic_vm_set_page(rdev, &ib, last_pde,
628 last_pt, count, incr,
641 radeon_asic_vm_set_page(rdev, &ib, last_pde, last_pt, count,
642 incr, R600_PTE_VALID);
644 if (ib.length_dw != 0) {
645 radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
646 r = radeon_ib_schedule(rdev, &ib, NULL);
648 radeon_ib_free(rdev, &ib);
651 radeon_fence_unref(&vm->fence);
652 vm->fence = radeon_fence_ref(ib.fence);
653 radeon_fence_unref(&vm->last_flush);
655 radeon_ib_free(rdev, &ib);
661 * radeon_vm_update_ptes - make sure that page tables are valid
663 * @rdev: radeon_device pointer
665 * @start: start of GPU address range
666 * @end: end of GPU address range
667 * @dst: destination address to map to
668 * @flags: mapping flags
670 * Update the page tables in the range @start - @end (cayman+).
672 * Global and local mutex must be locked!
674 static void radeon_vm_update_ptes(struct radeon_device *rdev,
675 struct radeon_vm *vm,
676 struct radeon_ib *ib,
677 uint64_t start, uint64_t end,
678 uint64_t dst, uint32_t flags)
680 static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
682 uint64_t last_pte = ~0, last_dst = ~0;
686 start = start / RADEON_GPU_PAGE_SIZE;
687 end = end / RADEON_GPU_PAGE_SIZE;
689 /* walk over the address space and update the page tables */
690 for (addr = start; addr < end; ) {
691 uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
695 if ((addr & ~mask) == (end & ~mask))
698 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
700 pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo);
701 pte += (addr & mask) * 8;
703 if ((last_pte + 8 * count) != pte) {
706 radeon_asic_vm_set_page(rdev, ib, last_pte,
708 RADEON_GPU_PAGE_SIZE,
720 dst += nptes * RADEON_GPU_PAGE_SIZE;
724 radeon_asic_vm_set_page(rdev, ib, last_pte,
726 RADEON_GPU_PAGE_SIZE, flags);
731 * radeon_vm_bo_update - map a bo into the vm page table
733 * @rdev: radeon_device pointer
735 * @bo: radeon buffer object
738 * Fill in the page table entries for @bo (cayman+).
739 * Returns 0 for success, -EINVAL for failure.
741 * Object have to be reserved and mutex must be locked!
743 int radeon_vm_bo_update(struct radeon_device *rdev,
744 struct radeon_vm *vm,
745 struct radeon_bo *bo,
746 struct ttm_mem_reg *mem)
749 struct radeon_bo_va *bo_va;
754 bo_va = radeon_vm_bo_find(vm, bo);
756 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
760 if (!bo_va->soffset) {
761 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
766 if ((bo_va->valid && mem) || (!bo_va->valid && mem == NULL))
769 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
770 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
772 addr = mem->start << PAGE_SHIFT;
773 if (mem->mem_type != TTM_PL_SYSTEM) {
774 bo_va->flags |= RADEON_VM_PAGE_VALID;
777 if (mem->mem_type == TTM_PL_TT) {
778 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
780 addr += rdev->vm_manager.vram_base_offset;
784 bo_va->valid = false;
787 trace_radeon_vm_bo_update(bo_va);
789 nptes = radeon_bo_ngpu_pages(bo);
794 if (RADEON_VM_BLOCK_SIZE > 11)
795 /* reserve space for one header for every 2k dwords */
796 ndw += (nptes >> 11) * 4;
798 /* reserve space for one header for
799 every (1 << BLOCK_SIZE) entries */
800 ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4;
802 /* reserve space for pte addresses */
805 /* update too big for an IB */
809 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
814 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
815 addr, radeon_vm_page_flags(bo_va->flags));
817 radeon_semaphore_sync_to(ib.semaphore, vm->fence);
818 r = radeon_ib_schedule(rdev, &ib, NULL);
820 radeon_ib_free(rdev, &ib);
823 radeon_fence_unref(&vm->fence);
824 vm->fence = radeon_fence_ref(ib.fence);
825 radeon_ib_free(rdev, &ib);
826 radeon_fence_unref(&vm->last_flush);
832 * radeon_vm_bo_rmv - remove a bo to a specific vm
834 * @rdev: radeon_device pointer
835 * @bo_va: requested bo_va
837 * Remove @bo_va->bo from the requested vm (cayman+).
838 * Remove @bo_va->bo from the list of bos associated with the bo_va->vm and
839 * remove the ptes for @bo_va in the page table.
840 * Returns 0 for success.
842 * Object have to be reserved!
844 int radeon_vm_bo_rmv(struct radeon_device *rdev,
845 struct radeon_bo_va *bo_va)
849 mutex_lock(&bo_va->vm->mutex);
851 r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL);
853 list_del(&bo_va->vm_list);
854 mutex_unlock(&bo_va->vm->mutex);
855 list_del(&bo_va->bo_list);
862 * radeon_vm_bo_invalidate - mark the bo as invalid
864 * @rdev: radeon_device pointer
866 * @bo: radeon buffer object
868 * Mark @bo as invalid (cayman+).
870 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
871 struct radeon_bo *bo)
873 struct radeon_bo_va *bo_va;
875 list_for_each_entry(bo_va, &bo->va, bo_list) {
876 bo_va->valid = false;
881 * radeon_vm_init - initialize a vm instance
883 * @rdev: radeon_device pointer
886 * Init @vm fields (cayman+).
888 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
890 unsigned pd_size, pd_entries, pts_size;
895 vm->last_flush = NULL;
896 vm->last_id_use = NULL;
897 mutex_init(&vm->mutex);
898 INIT_LIST_HEAD(&vm->va);
900 pd_size = radeon_vm_directory_size(rdev);
901 pd_entries = radeon_vm_num_pdes(rdev);
903 /* allocate page table array */
904 pts_size = pd_entries * sizeof(struct radeon_vm_pt);
905 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
906 if (vm->page_tables == NULL) {
907 DRM_ERROR("Cannot allocate memory for page table array\n");
911 r = radeon_bo_create(rdev, pd_size, RADEON_VM_PTB_ALIGN_SIZE, false,
912 RADEON_GEM_DOMAIN_VRAM, NULL,
913 &vm->page_directory);
917 r = radeon_vm_clear_bo(rdev, vm->page_directory);
919 radeon_bo_unref(&vm->page_directory);
920 vm->page_directory = NULL;
928 * radeon_vm_fini - tear down a vm instance
930 * @rdev: radeon_device pointer
933 * Tear down @vm (cayman+).
934 * Unbind the VM and remove all bos from the vm bo list
936 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
938 struct radeon_bo_va *bo_va, *tmp;
941 if (!list_empty(&vm->va)) {
942 dev_err(rdev->dev, "still active bo inside vm\n");
944 list_for_each_entry_safe(bo_va, tmp, &vm->va, vm_list) {
945 list_del_init(&bo_va->vm_list);
946 r = radeon_bo_reserve(bo_va->bo, false);
948 list_del_init(&bo_va->bo_list);
949 radeon_bo_unreserve(bo_va->bo);
955 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
956 radeon_bo_unref(&vm->page_tables[i].bo);
957 kfree(vm->page_tables);
959 radeon_bo_unref(&vm->page_directory);
961 radeon_fence_unref(&vm->fence);
962 radeon_fence_unref(&vm->last_flush);
963 radeon_fence_unref(&vm->last_id_use);
965 mutex_destroy(&vm->mutex);