2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_asic.h"
35 /* This files gather functions specifics to : rs400,rs480 */
36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
38 void rs400_gart_adjust_size(struct radeon_device *rdev)
41 switch (rdev->mc.gtt_size/(1024*1024)) {
51 DRM_ERROR("Unable to use IGP GART size %uM\n",
52 (unsigned)(rdev->mc.gtt_size >> 20));
53 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
54 DRM_ERROR("Forcing to 32M GART size\n");
55 rdev->mc.gtt_size = 32 * 1024 * 1024;
58 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
59 /* FIXME: RS400 & RS480 seems to have issue with GART size
60 * if 4G of system memory (needs more testing)
62 /* XXX is this still an issue with proper alignment? */
63 rdev->mc.gtt_size = 32 * 1024 * 1024;
64 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
68 void rs400_gart_tlb_flush(struct radeon_device *rdev)
71 unsigned int timeout = rdev->usec_timeout;
73 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
75 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
76 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
80 } while (timeout > 0);
81 WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
84 int rs400_gart_init(struct radeon_device *rdev)
88 if (rdev->gart.table.ram.ptr) {
89 WARN(1, "RS400 GART already initialized.\n");
93 switch(rdev->mc.gtt_size / (1024 * 1024)) {
105 /* Initialize common gart structure */
106 r = radeon_gart_init(rdev);
109 if (rs400_debugfs_pcie_gart_info_init(rdev))
110 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
111 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
112 return radeon_gart_table_ram_alloc(rdev);
115 int rs400_gart_enable(struct radeon_device *rdev)
120 radeon_gart_restore(rdev);
121 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
122 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
123 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
124 /* Check gart size */
125 switch(rdev->mc.gtt_size / (1024 * 1024)) {
127 size_reg = RS480_VA_SIZE_32MB;
130 size_reg = RS480_VA_SIZE_64MB;
133 size_reg = RS480_VA_SIZE_128MB;
136 size_reg = RS480_VA_SIZE_256MB;
139 size_reg = RS480_VA_SIZE_512MB;
142 size_reg = RS480_VA_SIZE_1GB;
145 size_reg = RS480_VA_SIZE_2GB;
150 /* It should be fine to program it to max value */
151 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
152 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
153 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
155 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
156 WREG32(RS480_AGP_BASE_2, 0);
158 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
159 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
160 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
161 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
162 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
163 WREG32(RADEON_BUS_CNTL, tmp);
165 WREG32(RADEON_MC_AGP_LOCATION, tmp);
166 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
167 WREG32(RADEON_BUS_CNTL, tmp);
169 /* Table should be in 32bits address space so ignore bits above. */
170 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
171 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
173 WREG32_MC(RS480_GART_BASE, tmp);
174 /* TODO: more tweaking here */
175 WREG32_MC(RS480_GART_FEATURE_ID,
177 RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
178 /* Disable snooping */
179 WREG32_MC(RS480_AGP_MODE_CNTL,
180 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
181 /* Disable AGP mode */
182 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
183 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
184 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
185 WREG32_MC(RS480_MC_MISC_CNTL,
186 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
188 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
191 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
192 rs400_gart_tlb_flush(rdev);
193 rdev->gart.ready = true;
197 void rs400_gart_disable(struct radeon_device *rdev)
201 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
202 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
203 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
204 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
207 void rs400_gart_fini(struct radeon_device *rdev)
209 radeon_gart_fini(rdev);
210 rs400_gart_disable(rdev);
211 radeon_gart_table_ram_free(rdev);
214 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
218 if (i < 0 || i > rdev->gart.num_gpu_pages) {
222 entry = (lower_32_bits(addr) & PAGE_MASK) |
223 ((upper_32_bits(addr) & 0xff) << 4) |
225 entry = cpu_to_le32(entry);
226 rdev->gart.table.ram.ptr[i] = entry;
230 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
235 for (i = 0; i < rdev->usec_timeout; i++) {
237 tmp = RREG32(0x0150);
238 if (tmp & (1 << 2)) {
246 void rs400_gpu_init(struct radeon_device *rdev)
248 /* FIXME: is this correct ? */
249 r420_pipes_init(rdev);
250 if (rs400_mc_wait_for_idle(rdev)) {
251 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
252 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
256 void rs400_mc_init(struct radeon_device *rdev)
260 rs400_gart_adjust_size(rdev);
261 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
262 /* DDR for all card after R300 & IGP */
263 rdev->mc.vram_is_ddr = true;
264 rdev->mc.vram_width = 128;
265 r100_vram_init_sizes(rdev);
266 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
267 radeon_vram_location(rdev, &rdev->mc, base);
268 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
269 radeon_gtt_location(rdev, &rdev->mc);
270 radeon_update_bandwidth_info(rdev);
273 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
277 WREG32(RS480_NB_MC_INDEX, reg & 0xff);
278 r = RREG32(RS480_NB_MC_DATA);
279 WREG32(RS480_NB_MC_INDEX, 0xff);
283 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
285 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
286 WREG32(RS480_NB_MC_DATA, (v));
287 WREG32(RS480_NB_MC_INDEX, 0xff);
290 #if defined(CONFIG_DEBUG_FS)
291 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
293 struct drm_info_node *node = (struct drm_info_node *) m->private;
294 struct drm_device *dev = node->minor->dev;
295 struct radeon_device *rdev = dev->dev_private;
298 tmp = RREG32(RADEON_HOST_PATH_CNTL);
299 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
300 tmp = RREG32(RADEON_BUS_CNTL);
301 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
302 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
303 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
304 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
305 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
306 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
307 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
308 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
309 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
310 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
311 tmp = RREG32_MC(0x100);
312 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
314 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
316 tmp = RREG32(RADEON_AGP_BASE);
317 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
318 tmp = RREG32(RS480_AGP_BASE_2);
319 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
320 tmp = RREG32(RADEON_MC_AGP_LOCATION);
321 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
323 tmp = RREG32_MC(RS480_GART_BASE);
324 seq_printf(m, "GART_BASE 0x%08x\n", tmp);
325 tmp = RREG32_MC(RS480_GART_FEATURE_ID);
326 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
327 tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
328 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
329 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
330 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
331 tmp = RREG32_MC(0x5F);
332 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
333 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
334 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
335 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
336 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
337 tmp = RREG32_MC(0x3B);
338 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
339 tmp = RREG32_MC(0x3C);
340 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
341 tmp = RREG32_MC(0x30);
342 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
343 tmp = RREG32_MC(0x31);
344 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
345 tmp = RREG32_MC(0x32);
346 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
347 tmp = RREG32_MC(0x33);
348 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
349 tmp = RREG32_MC(0x34);
350 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
351 tmp = RREG32_MC(0x35);
352 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
353 tmp = RREG32_MC(0x36);
354 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
355 tmp = RREG32_MC(0x37);
356 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
360 static struct drm_info_list rs400_gart_info_list[] = {
361 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
365 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
367 #if defined(CONFIG_DEBUG_FS)
368 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
374 void rs400_mc_program(struct radeon_device *rdev)
376 struct r100_mc_save save;
378 /* Stops all mc clients */
379 r100_mc_stop(rdev, &save);
381 /* Wait for mc idle */
382 if (rs400_mc_wait_for_idle(rdev))
383 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
384 WREG32(R_000148_MC_FB_LOCATION,
385 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
386 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
388 r100_mc_resume(rdev, &save);
391 static int rs400_startup(struct radeon_device *rdev)
395 r100_set_common_regs(rdev);
397 rs400_mc_program(rdev);
399 r300_clock_startup(rdev);
400 /* Initialize GPU configuration (# pipes, ...) */
401 rs400_gpu_init(rdev);
402 r100_enable_bm(rdev);
403 /* Initialize GART (initialize after TTM so we can allocate
404 * memory through TTM but finalize after TTM) */
405 r = rs400_gart_enable(rdev);
410 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
412 r = r100_cp_init(rdev, 1024 * 1024);
414 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
417 r = r100_wb_init(rdev);
419 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
420 r = r100_ib_init(rdev);
422 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
428 int rs400_resume(struct radeon_device *rdev)
430 /* Make sur GART are not working */
431 rs400_gart_disable(rdev);
432 /* Resume clock before doing reset */
433 r300_clock_startup(rdev);
434 /* setup MC before calling post tables */
435 rs400_mc_program(rdev);
436 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
437 if (radeon_asic_reset(rdev)) {
438 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
439 RREG32(R_000E40_RBBM_STATUS),
440 RREG32(R_0007C0_CP_STAT));
443 radeon_combios_asic_init(rdev->ddev);
444 /* Resume clock after posting */
445 r300_clock_startup(rdev);
446 /* Initialize surface registers */
447 radeon_surface_init(rdev);
448 return rs400_startup(rdev);
451 int rs400_suspend(struct radeon_device *rdev)
453 r100_cp_disable(rdev);
454 r100_wb_disable(rdev);
455 r100_irq_disable(rdev);
456 rs400_gart_disable(rdev);
460 void rs400_fini(struct radeon_device *rdev)
465 radeon_gem_fini(rdev);
466 rs400_gart_fini(rdev);
467 radeon_irq_kms_fini(rdev);
468 radeon_fence_driver_fini(rdev);
469 radeon_bo_fini(rdev);
470 radeon_atombios_fini(rdev);
475 int rs400_init(struct radeon_device *rdev)
480 r100_vga_render_disable(rdev);
481 /* Initialize scratch registers */
482 radeon_scratch_init(rdev);
483 /* Initialize surface registers */
484 radeon_surface_init(rdev);
485 /* TODO: disable VGA need to use VGA request */
487 if (!radeon_get_bios(rdev)) {
488 if (ASIC_IS_AVIVO(rdev))
491 if (rdev->is_atom_bios) {
492 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
495 r = radeon_combios_init(rdev);
499 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
500 if (radeon_asic_reset(rdev)) {
502 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
503 RREG32(R_000E40_RBBM_STATUS),
504 RREG32(R_0007C0_CP_STAT));
506 /* check if cards are posted or not */
507 if (radeon_boot_test_post_card(rdev) == false)
510 /* Initialize clocks */
511 radeon_get_clock_info(rdev->ddev);
512 /* initialize memory controller */
515 r = radeon_fence_driver_init(rdev);
518 r = radeon_irq_kms_init(rdev);
522 r = radeon_bo_init(rdev);
525 r = rs400_gart_init(rdev);
528 r300_set_reg_safe(rdev);
529 rdev->accel_working = true;
530 r = rs400_startup(rdev);
532 /* Somethings want wront with the accel init stop accel */
533 dev_err(rdev->dev, "Disabling GPU acceleration\n");
537 rs400_gart_fini(rdev);
538 radeon_irq_kms_fini(rdev);
539 rdev->accel_working = false;