2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "radeon_asic.h"
34 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
39 for (i = 0; i < rdev->usec_timeout; i++) {
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
49 static void rs690_gpu_init(struct radeon_device *rdev)
51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
64 void rs690_pm_info(struct radeon_device *rdev)
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
76 /* Get various system informations from bios */
79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 if (le16_to_cpu(info->info.usK8MemoryClock))
83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
93 tmp.full = dfixed_const(100);
94 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
96 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
98 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
108 /* We assume the slower possible clock ie worst case */
109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
117 /* We assume the slower possible clock ie worst case */
118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
133 rdev->pm.igp_ht_link_width);
134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
148 static void rs690_mc_init(struct radeon_device *rdev)
151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
154 rs400_gart_adjust_size(rdev);
155 rdev->mc.vram_is_ddr = true;
156 rdev->mc.vram_width = 128;
157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
161 rdev->mc.visible_vram_size = rdev->mc.aper_size;
162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163 base = G_000100_MC_FB_START(base) << 16;
164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
187 radeon_vram_location(rdev, &rdev->mc, base);
188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
189 radeon_gtt_location(rdev, &rdev->mc);
190 radeon_update_bandwidth_info(rdev);
193 void rs690_line_buffer_adjust(struct radeon_device *rdev,
194 struct drm_display_mode *mode1,
195 struct drm_display_mode *mode2)
201 * There is a single line buffer shared by both display controllers.
202 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
203 * the display controllers. The paritioning can either be done
204 * manually or via one of four preset allocations specified in bits 1:0:
205 * 0 - line buffer is divided in half and shared between crtc
206 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
207 * 2 - D1 gets the whole buffer
208 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
209 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
210 * allocation mode. In manual allocation mode, D1 always starts at 0,
211 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
213 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
214 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
216 if (mode1 && mode2) {
217 if (mode1->hdisplay > mode2->hdisplay) {
218 if (mode1->hdisplay > 2560)
219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
221 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
222 } else if (mode2->hdisplay > mode1->hdisplay) {
223 if (mode2->hdisplay > 2560)
224 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
226 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
228 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
230 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
234 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
237 struct rs690_watermark {
238 u32 lb_request_fifo_depth;
239 fixed20_12 num_line_pair;
240 fixed20_12 estimated_width;
241 fixed20_12 worst_case_latency;
242 fixed20_12 consumption_rate;
243 fixed20_12 active_time;
245 fixed20_12 priority_mark_max;
246 fixed20_12 priority_mark;
250 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
251 struct radeon_crtc *crtc,
252 struct rs690_watermark *wm,
255 struct drm_display_mode *mode = &crtc->base.mode;
257 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
258 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
259 fixed20_12 sclk, core_bandwidth, max_bandwidth;
262 if (!crtc->base.enabled) {
263 /* FIXME: wouldn't it better to set priority mark to maximum */
264 wm->lb_request_fifo_depth = 4;
268 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
269 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
270 selected_sclk = radeon_dpm_get_sclk(rdev, low);
272 selected_sclk = rdev->pm.current_sclk;
275 a.full = dfixed_const(100);
276 sclk.full = dfixed_const(selected_sclk);
277 sclk.full = dfixed_div(sclk, a);
279 /* core_bandwidth = sclk(Mhz) * 16 */
280 a.full = dfixed_const(16);
281 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
283 if (crtc->vsc.full > dfixed_const(2))
284 wm->num_line_pair.full = dfixed_const(2);
286 wm->num_line_pair.full = dfixed_const(1);
288 b.full = dfixed_const(mode->crtc_hdisplay);
289 c.full = dfixed_const(256);
290 a.full = dfixed_div(b, c);
291 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
292 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
293 if (a.full < dfixed_const(4)) {
294 wm->lb_request_fifo_depth = 4;
296 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
299 /* Determine consumption rate
300 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
301 * vtaps = number of vertical taps,
302 * vsc = vertical scaling ratio, defined as source/destination
303 * hsc = horizontal scaling ration, defined as source/destination
305 a.full = dfixed_const(mode->clock);
306 b.full = dfixed_const(1000);
307 a.full = dfixed_div(a, b);
308 pclk.full = dfixed_div(b, a);
309 if (crtc->rmx_type != RMX_OFF) {
310 b.full = dfixed_const(2);
311 if (crtc->vsc.full > b.full)
312 b.full = crtc->vsc.full;
313 b.full = dfixed_mul(b, crtc->hsc);
314 c.full = dfixed_const(2);
315 b.full = dfixed_div(b, c);
316 consumption_time.full = dfixed_div(pclk, b);
318 consumption_time.full = pclk.full;
320 a.full = dfixed_const(1);
321 wm->consumption_rate.full = dfixed_div(a, consumption_time);
324 /* Determine line time
325 * LineTime = total time for one line of displayhtotal
326 * LineTime = total number of horizontal pixels
327 * pclk = pixel clock period(ns)
329 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
330 line_time.full = dfixed_mul(a, pclk);
332 /* Determine active time
333 * ActiveTime = time of active region of display within one line,
334 * hactive = total number of horizontal active pixels
335 * htotal = total number of horizontal pixels
337 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
338 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
339 wm->active_time.full = dfixed_mul(line_time, b);
340 wm->active_time.full = dfixed_div(wm->active_time, a);
342 /* Maximun bandwidth is the minimun bandwidth of all component */
343 max_bandwidth = core_bandwidth;
344 if (rdev->mc.igp_sideport_enabled) {
345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
346 rdev->pm.sideport_bandwidth.full)
347 max_bandwidth = rdev->pm.sideport_bandwidth;
348 read_delay_latency.full = dfixed_const(370 * 800);
349 a.full = dfixed_const(1000);
350 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
351 read_delay_latency.full = dfixed_div(read_delay_latency, b);
352 read_delay_latency.full = dfixed_mul(read_delay_latency, a);
354 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
355 rdev->pm.k8_bandwidth.full)
356 max_bandwidth = rdev->pm.k8_bandwidth;
357 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
358 rdev->pm.ht_bandwidth.full)
359 max_bandwidth = rdev->pm.ht_bandwidth;
360 read_delay_latency.full = dfixed_const(5000);
363 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
364 a.full = dfixed_const(16);
365 sclk.full = dfixed_mul(max_bandwidth, a);
366 a.full = dfixed_const(1000);
367 sclk.full = dfixed_div(a, sclk);
368 /* Determine chunk time
369 * ChunkTime = the time it takes the DCP to send one chunk of data
370 * to the LB which consists of pipeline delay and inter chunk gap
371 * sclk = system clock(ns)
373 a.full = dfixed_const(256 * 13);
374 chunk_time.full = dfixed_mul(sclk, a);
375 a.full = dfixed_const(10);
376 chunk_time.full = dfixed_div(chunk_time, a);
378 /* Determine the worst case latency
379 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
380 * WorstCaseLatency = worst case time from urgent to when the MC starts
382 * READ_DELAY_IDLE_MAX = constant of 1us
383 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
384 * which consists of pipeline delay and inter chunk gap
386 if (dfixed_trunc(wm->num_line_pair) > 1) {
387 a.full = dfixed_const(3);
388 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
389 wm->worst_case_latency.full += read_delay_latency.full;
391 a.full = dfixed_const(2);
392 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
393 wm->worst_case_latency.full += read_delay_latency.full;
396 /* Determine the tolerable latency
397 * TolerableLatency = Any given request has only 1 line time
398 * for the data to be returned
399 * LBRequestFifoDepth = Number of chunk requests the LB can
400 * put into the request FIFO for a display
401 * LineTime = total time for one line of display
402 * ChunkTime = the time it takes the DCP to send one chunk
403 * of data to the LB which consists of
404 * pipeline delay and inter chunk gap
406 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
407 tolerable_latency.full = line_time.full;
409 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
410 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
411 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
412 tolerable_latency.full = line_time.full - tolerable_latency.full;
414 /* We assume worst case 32bits (4 bytes) */
415 wm->dbpp.full = dfixed_const(4 * 8);
417 /* Determine the maximum priority mark
418 * width = viewport width in pixels
420 a.full = dfixed_const(16);
421 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
422 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
423 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
425 /* Determine estimated width */
426 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
427 estimated_width.full = dfixed_div(estimated_width, consumption_time);
428 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
429 wm->priority_mark.full = dfixed_const(10);
431 a.full = dfixed_const(16);
432 wm->priority_mark.full = dfixed_div(estimated_width, a);
433 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
434 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
438 static void rs690_compute_mode_priority(struct radeon_device *rdev,
439 struct rs690_watermark *wm0,
440 struct rs690_watermark *wm1,
441 struct drm_display_mode *mode0,
442 struct drm_display_mode *mode1,
443 u32 *d1mode_priority_a_cnt,
444 u32 *d2mode_priority_a_cnt)
446 fixed20_12 priority_mark02, priority_mark12, fill_rate;
449 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
450 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
452 if (mode0 && mode1) {
453 if (dfixed_trunc(wm0->dbpp) > 64)
454 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
456 a.full = wm0->num_line_pair.full;
457 if (dfixed_trunc(wm1->dbpp) > 64)
458 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
460 b.full = wm1->num_line_pair.full;
462 fill_rate.full = dfixed_div(wm0->sclk, a);
463 if (wm0->consumption_rate.full > fill_rate.full) {
464 b.full = wm0->consumption_rate.full - fill_rate.full;
465 b.full = dfixed_mul(b, wm0->active_time);
466 a.full = dfixed_mul(wm0->worst_case_latency,
467 wm0->consumption_rate);
468 a.full = a.full + b.full;
469 b.full = dfixed_const(16 * 1000);
470 priority_mark02.full = dfixed_div(a, b);
472 a.full = dfixed_mul(wm0->worst_case_latency,
473 wm0->consumption_rate);
474 b.full = dfixed_const(16 * 1000);
475 priority_mark02.full = dfixed_div(a, b);
477 if (wm1->consumption_rate.full > fill_rate.full) {
478 b.full = wm1->consumption_rate.full - fill_rate.full;
479 b.full = dfixed_mul(b, wm1->active_time);
480 a.full = dfixed_mul(wm1->worst_case_latency,
481 wm1->consumption_rate);
482 a.full = a.full + b.full;
483 b.full = dfixed_const(16 * 1000);
484 priority_mark12.full = dfixed_div(a, b);
486 a.full = dfixed_mul(wm1->worst_case_latency,
487 wm1->consumption_rate);
488 b.full = dfixed_const(16 * 1000);
489 priority_mark12.full = dfixed_div(a, b);
491 if (wm0->priority_mark.full > priority_mark02.full)
492 priority_mark02.full = wm0->priority_mark.full;
493 if (wm0->priority_mark_max.full > priority_mark02.full)
494 priority_mark02.full = wm0->priority_mark_max.full;
495 if (wm1->priority_mark.full > priority_mark12.full)
496 priority_mark12.full = wm1->priority_mark.full;
497 if (wm1->priority_mark_max.full > priority_mark12.full)
498 priority_mark12.full = wm1->priority_mark_max.full;
499 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
500 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
501 if (rdev->disp_priority == 2) {
502 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
503 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
506 if (dfixed_trunc(wm0->dbpp) > 64)
507 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
509 a.full = wm0->num_line_pair.full;
510 fill_rate.full = dfixed_div(wm0->sclk, a);
511 if (wm0->consumption_rate.full > fill_rate.full) {
512 b.full = wm0->consumption_rate.full - fill_rate.full;
513 b.full = dfixed_mul(b, wm0->active_time);
514 a.full = dfixed_mul(wm0->worst_case_latency,
515 wm0->consumption_rate);
516 a.full = a.full + b.full;
517 b.full = dfixed_const(16 * 1000);
518 priority_mark02.full = dfixed_div(a, b);
520 a.full = dfixed_mul(wm0->worst_case_latency,
521 wm0->consumption_rate);
522 b.full = dfixed_const(16 * 1000);
523 priority_mark02.full = dfixed_div(a, b);
525 if (wm0->priority_mark.full > priority_mark02.full)
526 priority_mark02.full = wm0->priority_mark.full;
527 if (wm0->priority_mark_max.full > priority_mark02.full)
528 priority_mark02.full = wm0->priority_mark_max.full;
529 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
530 if (rdev->disp_priority == 2)
531 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
533 if (dfixed_trunc(wm1->dbpp) > 64)
534 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
536 a.full = wm1->num_line_pair.full;
537 fill_rate.full = dfixed_div(wm1->sclk, a);
538 if (wm1->consumption_rate.full > fill_rate.full) {
539 b.full = wm1->consumption_rate.full - fill_rate.full;
540 b.full = dfixed_mul(b, wm1->active_time);
541 a.full = dfixed_mul(wm1->worst_case_latency,
542 wm1->consumption_rate);
543 a.full = a.full + b.full;
544 b.full = dfixed_const(16 * 1000);
545 priority_mark12.full = dfixed_div(a, b);
547 a.full = dfixed_mul(wm1->worst_case_latency,
548 wm1->consumption_rate);
549 b.full = dfixed_const(16 * 1000);
550 priority_mark12.full = dfixed_div(a, b);
552 if (wm1->priority_mark.full > priority_mark12.full)
553 priority_mark12.full = wm1->priority_mark.full;
554 if (wm1->priority_mark_max.full > priority_mark12.full)
555 priority_mark12.full = wm1->priority_mark_max.full;
556 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
557 if (rdev->disp_priority == 2)
558 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
562 void rs690_bandwidth_update(struct radeon_device *rdev)
564 struct drm_display_mode *mode0 = NULL;
565 struct drm_display_mode *mode1 = NULL;
566 struct rs690_watermark wm0_high, wm0_low;
567 struct rs690_watermark wm1_high, wm1_low;
569 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
570 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
572 radeon_update_display_priority(rdev);
574 if (rdev->mode_info.crtcs[0]->base.enabled)
575 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
576 if (rdev->mode_info.crtcs[1]->base.enabled)
577 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
579 * Set display0/1 priority up in the memory controller for
580 * modes if the user specifies HIGH for displaypriority
583 if ((rdev->disp_priority == 2) &&
584 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
585 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
586 tmp &= C_000104_MC_DISP0R_INIT_LAT;
587 tmp &= C_000104_MC_DISP1R_INIT_LAT;
589 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
591 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
592 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
594 rs690_line_buffer_adjust(rdev, mode0, mode1);
596 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
597 WREG32(R_006C9C_DCP_CONTROL, 0);
598 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
599 WREG32(R_006C9C_DCP_CONTROL, 2);
601 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
602 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
604 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
605 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
607 tmp = (wm0_high.lb_request_fifo_depth - 1);
608 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
609 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
611 rs690_compute_mode_priority(rdev,
612 &wm0_high, &wm1_high,
614 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
615 rs690_compute_mode_priority(rdev,
618 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
620 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
621 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
622 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
623 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
626 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
631 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
632 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
633 r = RREG32(R_00007C_MC_DATA);
634 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
635 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
639 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
643 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
644 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
645 S_000078_MC_IND_WR_EN(1));
646 WREG32(R_00007C_MC_DATA, v);
647 WREG32(R_000078_MC_INDEX, 0x7F);
648 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
651 static void rs690_mc_program(struct radeon_device *rdev)
653 struct rv515_mc_save save;
655 /* Stops all mc clients */
656 rv515_mc_stop(rdev, &save);
658 /* Wait for mc idle */
659 if (rs690_mc_wait_for_idle(rdev))
660 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
661 /* Program MC, should be a 32bits limited address space */
662 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
663 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
664 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
665 WREG32(R_000134_HDP_FB_LOCATION,
666 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
668 rv515_mc_resume(rdev, &save);
671 static int rs690_startup(struct radeon_device *rdev)
675 rs690_mc_program(rdev);
677 rv515_clock_startup(rdev);
678 /* Initialize GPU configuration (# pipes, ...) */
679 rs690_gpu_init(rdev);
680 /* Initialize GART (initialize after TTM so we can allocate
681 * memory through TTM but finalize after TTM) */
682 r = rs400_gart_enable(rdev);
686 /* allocate wb buffer */
687 r = radeon_wb_init(rdev);
691 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
693 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
698 if (!rdev->irq.installed) {
699 r = radeon_irq_kms_init(rdev);
705 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
707 r = r100_cp_init(rdev, 1024 * 1024);
709 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
713 r = radeon_ib_pool_init(rdev);
715 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
719 r = r600_audio_init(rdev);
721 dev_err(rdev->dev, "failed initializing audio\n");
728 int rs690_resume(struct radeon_device *rdev)
732 /* Make sur GART are not working */
733 rs400_gart_disable(rdev);
734 /* Resume clock before doing reset */
735 rv515_clock_startup(rdev);
736 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
737 if (radeon_asic_reset(rdev)) {
738 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
739 RREG32(R_000E40_RBBM_STATUS),
740 RREG32(R_0007C0_CP_STAT));
743 atom_asic_init(rdev->mode_info.atom_context);
744 /* Resume clock after posting */
745 rv515_clock_startup(rdev);
746 /* Initialize surface registers */
747 radeon_surface_init(rdev);
749 rdev->accel_working = true;
750 r = rs690_startup(rdev);
752 rdev->accel_working = false;
757 int rs690_suspend(struct radeon_device *rdev)
759 r600_audio_fini(rdev);
760 r100_cp_disable(rdev);
761 radeon_wb_disable(rdev);
762 rs600_irq_disable(rdev);
763 rs400_gart_disable(rdev);
767 void rs690_fini(struct radeon_device *rdev)
769 r600_audio_fini(rdev);
771 radeon_wb_fini(rdev);
772 radeon_ib_pool_fini(rdev);
773 radeon_gem_fini(rdev);
774 rs400_gart_fini(rdev);
775 radeon_irq_kms_fini(rdev);
776 radeon_fence_driver_fini(rdev);
777 radeon_bo_fini(rdev);
778 radeon_atombios_fini(rdev);
783 int rs690_init(struct radeon_device *rdev)
788 rv515_vga_render_disable(rdev);
789 /* Initialize scratch registers */
790 radeon_scratch_init(rdev);
791 /* Initialize surface registers */
792 radeon_surface_init(rdev);
793 /* restore some register to sane defaults */
794 r100_restore_sanity(rdev);
795 /* TODO: disable VGA need to use VGA request */
797 if (!radeon_get_bios(rdev)) {
798 if (ASIC_IS_AVIVO(rdev))
801 if (rdev->is_atom_bios) {
802 r = radeon_atombios_init(rdev);
806 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
809 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
810 if (radeon_asic_reset(rdev)) {
812 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
813 RREG32(R_000E40_RBBM_STATUS),
814 RREG32(R_0007C0_CP_STAT));
816 /* check if cards are posted or not */
817 if (radeon_boot_test_post_card(rdev) == false)
820 /* Initialize clocks */
821 radeon_get_clock_info(rdev->ddev);
822 /* initialize memory controller */
826 r = radeon_fence_driver_init(rdev);
830 r = radeon_bo_init(rdev);
833 r = rs400_gart_init(rdev);
836 rs600_set_safe_registers(rdev);
838 rdev->accel_working = true;
839 r = rs690_startup(rdev);
841 /* Somethings want wront with the accel init stop accel */
842 dev_err(rdev->dev, "Disabling GPU acceleration\n");
844 radeon_wb_fini(rdev);
845 radeon_ib_pool_fini(rdev);
846 rs400_gart_fini(rdev);
847 radeon_irq_kms_fini(rdev);
848 rdev->accel_working = false;