2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "radeon_asic.h"
34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
39 for (i = 0; i < rdev->usec_timeout; i++) {
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
49 static void rs690_gpu_init(struct radeon_device *rdev)
51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
64 void rs690_pm_info(struct radeon_device *rdev)
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
76 /* Get various system informations from bios */
79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
83 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
84 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
87 tmp.full = dfixed_const(100);
88 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
89 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
91 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
92 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
93 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
94 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
97 tmp.full = dfixed_const(100);
98 /* We assume the slower possible clock ie worst case */
100 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
101 /* FIXME: system clock ? */
102 rdev->pm.igp_system_mclk.full = dfixed_const(100);
103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
106 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
110 tmp.full = dfixed_const(100);
111 /* We assume the slower possible clock ie worst case */
113 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
114 /* FIXME: system clock ? */
115 rdev->pm.igp_system_mclk.full = dfixed_const(100);
116 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
117 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
118 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
119 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
121 /* Compute various bandwidth */
122 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
123 tmp.full = dfixed_const(4);
124 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
125 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
126 * = ht_clk * ht_width / 5
128 tmp.full = dfixed_const(5);
129 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
130 rdev->pm.igp_ht_link_width);
131 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
132 if (tmp.full < rdev->pm.max_bandwidth.full) {
133 /* HT link is a limiting factor */
134 rdev->pm.max_bandwidth.full = tmp.full;
136 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
137 * = (sideport_clk * 14) / 10
139 tmp.full = dfixed_const(14);
140 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
141 tmp.full = dfixed_const(10);
142 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
145 void rs690_mc_init(struct radeon_device *rdev)
149 rs400_gart_adjust_size(rdev);
150 rdev->mc.vram_is_ddr = true;
151 rdev->mc.vram_width = 128;
152 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
153 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
154 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
155 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
156 rdev->mc.visible_vram_size = rdev->mc.aper_size;
157 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
158 base = G_000100_MC_FB_START(base) << 16;
160 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
161 radeon_vram_location(rdev, &rdev->mc, base);
162 radeon_gtt_location(rdev, &rdev->mc);
163 radeon_update_bandwidth_info(rdev);
166 void rs690_line_buffer_adjust(struct radeon_device *rdev,
167 struct drm_display_mode *mode1,
168 struct drm_display_mode *mode2)
174 * There is a single line buffer shared by both display controllers.
175 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
176 * the display controllers. The paritioning can either be done
177 * manually or via one of four preset allocations specified in bits 1:0:
178 * 0 - line buffer is divided in half and shared between crtc
179 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
180 * 2 - D1 gets the whole buffer
181 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
182 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
183 * allocation mode. In manual allocation mode, D1 always starts at 0,
184 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
186 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
187 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
189 if (mode1 && mode2) {
190 if (mode1->hdisplay > mode2->hdisplay) {
191 if (mode1->hdisplay > 2560)
192 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
194 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
195 } else if (mode2->hdisplay > mode1->hdisplay) {
196 if (mode2->hdisplay > 2560)
197 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
199 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
207 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
210 struct rs690_watermark {
211 u32 lb_request_fifo_depth;
212 fixed20_12 num_line_pair;
213 fixed20_12 estimated_width;
214 fixed20_12 worst_case_latency;
215 fixed20_12 consumption_rate;
216 fixed20_12 active_time;
218 fixed20_12 priority_mark_max;
219 fixed20_12 priority_mark;
223 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
224 struct radeon_crtc *crtc,
225 struct rs690_watermark *wm)
227 struct drm_display_mode *mode = &crtc->base.mode;
229 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
230 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
232 if (!crtc->base.enabled) {
233 /* FIXME: wouldn't it better to set priority mark to maximum */
234 wm->lb_request_fifo_depth = 4;
238 if (crtc->vsc.full > dfixed_const(2))
239 wm->num_line_pair.full = dfixed_const(2);
241 wm->num_line_pair.full = dfixed_const(1);
243 b.full = dfixed_const(mode->crtc_hdisplay);
244 c.full = dfixed_const(256);
245 a.full = dfixed_div(b, c);
246 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
247 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
248 if (a.full < dfixed_const(4)) {
249 wm->lb_request_fifo_depth = 4;
251 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
254 /* Determine consumption rate
255 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
256 * vtaps = number of vertical taps,
257 * vsc = vertical scaling ratio, defined as source/destination
258 * hsc = horizontal scaling ration, defined as source/destination
260 a.full = dfixed_const(mode->clock);
261 b.full = dfixed_const(1000);
262 a.full = dfixed_div(a, b);
263 pclk.full = dfixed_div(b, a);
264 if (crtc->rmx_type != RMX_OFF) {
265 b.full = dfixed_const(2);
266 if (crtc->vsc.full > b.full)
267 b.full = crtc->vsc.full;
268 b.full = dfixed_mul(b, crtc->hsc);
269 c.full = dfixed_const(2);
270 b.full = dfixed_div(b, c);
271 consumption_time.full = dfixed_div(pclk, b);
273 consumption_time.full = pclk.full;
275 a.full = dfixed_const(1);
276 wm->consumption_rate.full = dfixed_div(a, consumption_time);
279 /* Determine line time
280 * LineTime = total time for one line of displayhtotal
281 * LineTime = total number of horizontal pixels
282 * pclk = pixel clock period(ns)
284 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
285 line_time.full = dfixed_mul(a, pclk);
287 /* Determine active time
288 * ActiveTime = time of active region of display within one line,
289 * hactive = total number of horizontal active pixels
290 * htotal = total number of horizontal pixels
292 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
293 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
294 wm->active_time.full = dfixed_mul(line_time, b);
295 wm->active_time.full = dfixed_div(wm->active_time, a);
297 /* Maximun bandwidth is the minimun bandwidth of all component */
298 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
299 if (rdev->mc.igp_sideport_enabled) {
300 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
301 rdev->pm.sideport_bandwidth.full)
302 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
303 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
304 read_delay_latency.full = dfixed_div(read_delay_latency,
305 rdev->pm.igp_sideport_mclk);
307 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
308 rdev->pm.k8_bandwidth.full)
309 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
310 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
311 rdev->pm.ht_bandwidth.full)
312 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
313 read_delay_latency.full = dfixed_const(5000);
316 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
317 a.full = dfixed_const(16);
318 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
319 a.full = dfixed_const(1000);
320 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
321 /* Determine chunk time
322 * ChunkTime = the time it takes the DCP to send one chunk of data
323 * to the LB which consists of pipeline delay and inter chunk gap
324 * sclk = system clock(ns)
326 a.full = dfixed_const(256 * 13);
327 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
328 a.full = dfixed_const(10);
329 chunk_time.full = dfixed_div(chunk_time, a);
331 /* Determine the worst case latency
332 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
333 * WorstCaseLatency = worst case time from urgent to when the MC starts
335 * READ_DELAY_IDLE_MAX = constant of 1us
336 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
337 * which consists of pipeline delay and inter chunk gap
339 if (dfixed_trunc(wm->num_line_pair) > 1) {
340 a.full = dfixed_const(3);
341 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
342 wm->worst_case_latency.full += read_delay_latency.full;
344 a.full = dfixed_const(2);
345 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
346 wm->worst_case_latency.full += read_delay_latency.full;
349 /* Determine the tolerable latency
350 * TolerableLatency = Any given request has only 1 line time
351 * for the data to be returned
352 * LBRequestFifoDepth = Number of chunk requests the LB can
353 * put into the request FIFO for a display
354 * LineTime = total time for one line of display
355 * ChunkTime = the time it takes the DCP to send one chunk
356 * of data to the LB which consists of
357 * pipeline delay and inter chunk gap
359 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
360 tolerable_latency.full = line_time.full;
362 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
363 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
364 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
365 tolerable_latency.full = line_time.full - tolerable_latency.full;
367 /* We assume worst case 32bits (4 bytes) */
368 wm->dbpp.full = dfixed_const(4 * 8);
370 /* Determine the maximum priority mark
371 * width = viewport width in pixels
373 a.full = dfixed_const(16);
374 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
375 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
376 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
378 /* Determine estimated width */
379 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
380 estimated_width.full = dfixed_div(estimated_width, consumption_time);
381 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
382 wm->priority_mark.full = dfixed_const(10);
384 a.full = dfixed_const(16);
385 wm->priority_mark.full = dfixed_div(estimated_width, a);
386 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
387 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
391 void rs690_bandwidth_update(struct radeon_device *rdev)
393 struct drm_display_mode *mode0 = NULL;
394 struct drm_display_mode *mode1 = NULL;
395 struct rs690_watermark wm0;
396 struct rs690_watermark wm1;
397 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
398 fixed20_12 priority_mark02, priority_mark12, fill_rate;
401 radeon_update_display_priority(rdev);
403 if (rdev->mode_info.crtcs[0]->base.enabled)
404 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
405 if (rdev->mode_info.crtcs[1]->base.enabled)
406 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
408 * Set display0/1 priority up in the memory controller for
409 * modes if the user specifies HIGH for displaypriority
412 if ((rdev->disp_priority == 2) &&
413 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
414 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
415 tmp &= C_000104_MC_DISP0R_INIT_LAT;
416 tmp &= C_000104_MC_DISP1R_INIT_LAT;
418 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
420 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
421 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
423 rs690_line_buffer_adjust(rdev, mode0, mode1);
425 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
426 WREG32(R_006C9C_DCP_CONTROL, 0);
427 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
428 WREG32(R_006C9C_DCP_CONTROL, 2);
430 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
431 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
433 tmp = (wm0.lb_request_fifo_depth - 1);
434 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
435 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
437 if (mode0 && mode1) {
438 if (dfixed_trunc(wm0.dbpp) > 64)
439 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
441 a.full = wm0.num_line_pair.full;
442 if (dfixed_trunc(wm1.dbpp) > 64)
443 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
445 b.full = wm1.num_line_pair.full;
447 fill_rate.full = dfixed_div(wm0.sclk, a);
448 if (wm0.consumption_rate.full > fill_rate.full) {
449 b.full = wm0.consumption_rate.full - fill_rate.full;
450 b.full = dfixed_mul(b, wm0.active_time);
451 a.full = dfixed_mul(wm0.worst_case_latency,
452 wm0.consumption_rate);
453 a.full = a.full + b.full;
454 b.full = dfixed_const(16 * 1000);
455 priority_mark02.full = dfixed_div(a, b);
457 a.full = dfixed_mul(wm0.worst_case_latency,
458 wm0.consumption_rate);
459 b.full = dfixed_const(16 * 1000);
460 priority_mark02.full = dfixed_div(a, b);
462 if (wm1.consumption_rate.full > fill_rate.full) {
463 b.full = wm1.consumption_rate.full - fill_rate.full;
464 b.full = dfixed_mul(b, wm1.active_time);
465 a.full = dfixed_mul(wm1.worst_case_latency,
466 wm1.consumption_rate);
467 a.full = a.full + b.full;
468 b.full = dfixed_const(16 * 1000);
469 priority_mark12.full = dfixed_div(a, b);
471 a.full = dfixed_mul(wm1.worst_case_latency,
472 wm1.consumption_rate);
473 b.full = dfixed_const(16 * 1000);
474 priority_mark12.full = dfixed_div(a, b);
476 if (wm0.priority_mark.full > priority_mark02.full)
477 priority_mark02.full = wm0.priority_mark.full;
478 if (dfixed_trunc(priority_mark02) < 0)
479 priority_mark02.full = 0;
480 if (wm0.priority_mark_max.full > priority_mark02.full)
481 priority_mark02.full = wm0.priority_mark_max.full;
482 if (wm1.priority_mark.full > priority_mark12.full)
483 priority_mark12.full = wm1.priority_mark.full;
484 if (dfixed_trunc(priority_mark12) < 0)
485 priority_mark12.full = 0;
486 if (wm1.priority_mark_max.full > priority_mark12.full)
487 priority_mark12.full = wm1.priority_mark_max.full;
488 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
489 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
490 if (rdev->disp_priority == 2) {
491 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
492 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
494 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
495 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
496 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
497 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
499 if (dfixed_trunc(wm0.dbpp) > 64)
500 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
502 a.full = wm0.num_line_pair.full;
503 fill_rate.full = dfixed_div(wm0.sclk, a);
504 if (wm0.consumption_rate.full > fill_rate.full) {
505 b.full = wm0.consumption_rate.full - fill_rate.full;
506 b.full = dfixed_mul(b, wm0.active_time);
507 a.full = dfixed_mul(wm0.worst_case_latency,
508 wm0.consumption_rate);
509 a.full = a.full + b.full;
510 b.full = dfixed_const(16 * 1000);
511 priority_mark02.full = dfixed_div(a, b);
513 a.full = dfixed_mul(wm0.worst_case_latency,
514 wm0.consumption_rate);
515 b.full = dfixed_const(16 * 1000);
516 priority_mark02.full = dfixed_div(a, b);
518 if (wm0.priority_mark.full > priority_mark02.full)
519 priority_mark02.full = wm0.priority_mark.full;
520 if (dfixed_trunc(priority_mark02) < 0)
521 priority_mark02.full = 0;
522 if (wm0.priority_mark_max.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark_max.full;
524 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
525 if (rdev->disp_priority == 2)
526 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
527 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
528 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
529 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
530 S_006D48_D2MODE_PRIORITY_A_OFF(1));
531 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
532 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
534 if (dfixed_trunc(wm1.dbpp) > 64)
535 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
537 a.full = wm1.num_line_pair.full;
538 fill_rate.full = dfixed_div(wm1.sclk, a);
539 if (wm1.consumption_rate.full > fill_rate.full) {
540 b.full = wm1.consumption_rate.full - fill_rate.full;
541 b.full = dfixed_mul(b, wm1.active_time);
542 a.full = dfixed_mul(wm1.worst_case_latency,
543 wm1.consumption_rate);
544 a.full = a.full + b.full;
545 b.full = dfixed_const(16 * 1000);
546 priority_mark12.full = dfixed_div(a, b);
548 a.full = dfixed_mul(wm1.worst_case_latency,
549 wm1.consumption_rate);
550 b.full = dfixed_const(16 * 1000);
551 priority_mark12.full = dfixed_div(a, b);
553 if (wm1.priority_mark.full > priority_mark12.full)
554 priority_mark12.full = wm1.priority_mark.full;
555 if (dfixed_trunc(priority_mark12) < 0)
556 priority_mark12.full = 0;
557 if (wm1.priority_mark_max.full > priority_mark12.full)
558 priority_mark12.full = wm1.priority_mark_max.full;
559 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
560 if (rdev->disp_priority == 2)
561 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
562 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
563 S_006548_D1MODE_PRIORITY_A_OFF(1));
564 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
565 S_00654C_D1MODE_PRIORITY_B_OFF(1));
566 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
567 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
571 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
575 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
576 r = RREG32(R_00007C_MC_DATA);
577 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
581 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
583 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
584 S_000078_MC_IND_WR_EN(1));
585 WREG32(R_00007C_MC_DATA, v);
586 WREG32(R_000078_MC_INDEX, 0x7F);
589 void rs690_mc_program(struct radeon_device *rdev)
591 struct rv515_mc_save save;
593 /* Stops all mc clients */
594 rv515_mc_stop(rdev, &save);
596 /* Wait for mc idle */
597 if (rs690_mc_wait_for_idle(rdev))
598 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
599 /* Program MC, should be a 32bits limited address space */
600 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
601 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
602 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
603 WREG32(R_000134_HDP_FB_LOCATION,
604 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
606 rv515_mc_resume(rdev, &save);
609 static int rs690_startup(struct radeon_device *rdev)
613 rs690_mc_program(rdev);
615 rv515_clock_startup(rdev);
616 /* Initialize GPU configuration (# pipes, ...) */
617 rs690_gpu_init(rdev);
618 /* Initialize GART (initialize after TTM so we can allocate
619 * memory through TTM but finalize after TTM) */
620 r = rs400_gart_enable(rdev);
625 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
627 r = r100_cp_init(rdev, 1024 * 1024);
629 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
632 r = r100_wb_init(rdev);
634 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
635 r = r100_ib_init(rdev);
637 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
643 int rs690_resume(struct radeon_device *rdev)
645 /* Make sur GART are not working */
646 rs400_gart_disable(rdev);
647 /* Resume clock before doing reset */
648 rv515_clock_startup(rdev);
649 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
650 if (radeon_asic_reset(rdev)) {
651 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
652 RREG32(R_000E40_RBBM_STATUS),
653 RREG32(R_0007C0_CP_STAT));
656 atom_asic_init(rdev->mode_info.atom_context);
657 /* Resume clock after posting */
658 rv515_clock_startup(rdev);
659 /* Initialize surface registers */
660 radeon_surface_init(rdev);
661 return rs690_startup(rdev);
664 int rs690_suspend(struct radeon_device *rdev)
666 r100_cp_disable(rdev);
667 r100_wb_disable(rdev);
668 rs600_irq_disable(rdev);
669 rs400_gart_disable(rdev);
673 void rs690_fini(struct radeon_device *rdev)
678 radeon_gem_fini(rdev);
679 rs400_gart_fini(rdev);
680 radeon_irq_kms_fini(rdev);
681 radeon_fence_driver_fini(rdev);
682 radeon_bo_fini(rdev);
683 radeon_atombios_fini(rdev);
688 int rs690_init(struct radeon_device *rdev)
693 rv515_vga_render_disable(rdev);
694 /* Initialize scratch registers */
695 radeon_scratch_init(rdev);
696 /* Initialize surface registers */
697 radeon_surface_init(rdev);
698 /* TODO: disable VGA need to use VGA request */
700 if (!radeon_get_bios(rdev)) {
701 if (ASIC_IS_AVIVO(rdev))
704 if (rdev->is_atom_bios) {
705 r = radeon_atombios_init(rdev);
709 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
712 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
713 if (radeon_asic_reset(rdev)) {
715 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
716 RREG32(R_000E40_RBBM_STATUS),
717 RREG32(R_0007C0_CP_STAT));
719 /* check if cards are posted or not */
720 if (radeon_boot_test_post_card(rdev) == false)
723 /* Initialize clocks */
724 radeon_get_clock_info(rdev->ddev);
725 /* initialize memory controller */
729 r = radeon_fence_driver_init(rdev);
732 r = radeon_irq_kms_init(rdev);
736 r = radeon_bo_init(rdev);
739 r = rs400_gart_init(rdev);
742 rs600_set_safe_registers(rdev);
743 rdev->accel_working = true;
744 r = rs690_startup(rdev);
746 /* Somethings want wront with the accel init stop accel */
747 dev_err(rdev->dev, "Disabling GPU acceleration\n");
751 rs400_gart_fini(rdev);
752 radeon_irq_kms_fini(rdev);
753 rdev->accel_working = false;