drivers/gpu/drm/radeon/rs780_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "rs780d.h"
  28 #include "r600_dpm.h"
  29 #include "rs780_dpm.h"
  30 #include "atom.h"
  31 #include <linux/seq_file.h>
  32
  33 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
  34 {
  35         struct igp_ps *ps = rps->ps_priv;
  36
  37         return ps;
  38 }
  39
  40 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
  41 {
  42         struct igp_power_info *pi = rdev->pm.dpm.priv;
  43
  44         return pi;
  45 }
  46
  47 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
  48 {
  49         struct igp_power_info *pi = rs780_get_pi(rdev);
  50         struct radeon_mode_info *minfo = &rdev->mode_info;
  51         struct drm_crtc *crtc;
  52         struct radeon_crtc *radeon_crtc;
  53         int i;
  54
  55         /* defaults */
  56         pi->crtc_id = 0;
  57         pi->refresh_rate = 60;
  58
  59         for (i = 0; i < rdev->num_crtc; i++) {
  60                 crtc = (struct drm_crtc *)minfo->crtcs[i];
  61                 if (crtc && crtc->enabled) {
  62                         radeon_crtc = to_radeon_crtc(crtc);
  63                         pi->crtc_id = radeon_crtc->crtc_id;
  64                         if (crtc->mode.htotal && crtc->mode.vtotal)
  65                                 pi->refresh_rate =
  66                                         (crtc->mode.clock * 1000) /
  67                                         (crtc->mode.htotal * crtc->mode.vtotal);
  68                         break;
  69                 }
  70         }
  71 }
  72
  73 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
  74
  75 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
  76                                             struct radeon_ps *boot_ps)
  77 {
  78         struct atom_clock_dividers dividers;
  79         struct igp_ps *default_state = rs780_get_ps(boot_ps);
  80         int i, ret;
  81
  82         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  83                                              default_state->sclk_low, false, &dividers);
  84         if (ret)
  85                 return ret;
  86
  87         r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
  88         r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
  89         r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
  90
  91         if (dividers.enable_post_div)
  92                 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
  93         else
  94                 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
  95
  96         r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
  97         r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
  98
  99         r600_engine_clock_entry_enable(rdev, 0, true);
 100         for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
 101                 r600_engine_clock_entry_enable(rdev, i, false);
 102
 103         r600_enable_mclk_control(rdev, false);
 104         r600_voltage_control_enable_pins(rdev, 0);
 105
 106         return 0;
 107 }
 108
 109 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
 110                                            struct radeon_ps *boot_ps)
 111 {
 112         int ret = 0;
 113         int i;
 114
 115         r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
 116
 117         r600_set_at(rdev, 0, 0, 0, 0);
 118
 119         r600_set_git(rdev, R600_GICST_DFLT);
 120
 121         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
 122                 r600_set_tc(rdev, i, 0, 0);
 123
 124         r600_select_td(rdev, R600_TD_DFLT);
 125         r600_set_vrc(rdev, 0);
 126
 127         r600_set_tpu(rdev, R600_TPU_DFLT);
 128         r600_set_tpc(rdev, R600_TPC_DFLT);
 129
 130         r600_set_sstu(rdev, R600_SSTU_DFLT);
 131         r600_set_sst(rdev, R600_SST_DFLT);
 132
 133         r600_set_fctu(rdev, R600_FCTU_DFLT);
 134         r600_set_fct(rdev, R600_FCT_DFLT);
 135
 136         r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 137         r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
 138         r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
 139         r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
 140         r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
 141
 142         r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
 143         r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
 144         r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
 145
 146         ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
 147
 148         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,     0);
 149         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,  0);
 150         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,    0);
 151
 152         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
 153         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
 154         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
 155
 156         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
 157         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
 158         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
 159
 160         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,    R600_DISPLAY_WATERMARK_HIGH);
 161         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
 162         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,   R600_DISPLAY_WATERMARK_HIGH);
 163
 164         r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
 165         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
 166         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
 167         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
 168
 169         r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
 170
 171         r600_set_vrc(rdev, RS780_CGFTV_DFLT);
 172
 173         return ret;
 174 }
 175
 176 static void rs780_start_dpm(struct radeon_device *rdev)
 177 {
 178         r600_enable_sclk_control(rdev, false);
 179         r600_enable_mclk_control(rdev, false);
 180
 181         r600_dynamicpm_enable(rdev, true);
 182
 183         radeon_wait_for_vblank(rdev, 0);
 184         radeon_wait_for_vblank(rdev, 1);
 185
 186         r600_enable_spll_bypass(rdev, true);
 187         r600_wait_for_spll_change(rdev);
 188         r600_enable_spll_bypass(rdev, false);
 189         r600_wait_for_spll_change(rdev);
 190
 191         r600_enable_spll_bypass(rdev, true);
 192         r600_wait_for_spll_change(rdev);
 193         r600_enable_spll_bypass(rdev, false);
 194         r600_wait_for_spll_change(rdev);
 195
 196         r600_enable_sclk_control(rdev, true);
 197 }
 198
 199
 200 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
 201 {
 202         WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
 203                  ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
 204
 205         WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
 206                  RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
 207                  ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
 208 }
 209
 210 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
 211 {
 212         u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
 213
 214         WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
 215                  ~STARTING_FEEDBACK_DIV_MASK);
 216
 217         WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
 218                  ~FORCED_FEEDBACK_DIV_MASK);
 219
 220         WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
 221 }
 222
 223 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
 224 {
 225         struct igp_power_info *pi = rs780_get_pi(rdev);
 226         struct drm_device *dev = rdev->ddev;
 227         u32 fv_throt_pwm_fb_div_range[3];
 228         u32 fv_throt_pwm_range[4];
 229
 230         if (dev->pdev->device == 0x9614) {
 231                 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 232                 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 233                 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 234         } else if ((dev->pdev->device == 0x9714) ||
 235                    (dev->pdev->device == 0x9715)) {
 236                 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 237                 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 238                 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 239         } else {
 240                 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 241                 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 242                 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 243         }
 244
 245         if (pi->pwm_voltage_control) {
 246                 fv_throt_pwm_range[0] = pi->min_voltage;
 247                 fv_throt_pwm_range[1] = pi->min_voltage;
 248                 fv_throt_pwm_range[2] = pi->max_voltage;
 249                 fv_throt_pwm_range[3] = pi->max_voltage;
 250         } else {
 251                 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
 252                         RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
 253                 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
 254                         RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
 255                 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
 256                         RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
 257                 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
 258                         RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
 259         }
 260
 261         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 262                  STARTING_PWM_HIGHTIME(pi->max_voltage),
 263                  ~STARTING_PWM_HIGHTIME_MASK);
 264
 265         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 266                  NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
 267                  ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
 268
 269         WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
 270                  ~FORCE_STARTING_PWM_HIGHTIME);
 271
 272         if (pi->invert_pwm_required)
 273                 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
 274         else
 275                 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
 276
 277         rs780_voltage_scaling_enable(rdev, true);
 278
 279         WREG32(FVTHROT_PWM_CTRL_REG1,
 280                (MIN_PWM_HIGHTIME(pi->min_voltage) |
 281                 MAX_PWM_HIGHTIME(pi->max_voltage)));
 282
 283         WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
 284         WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
 285         WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
 286         WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
 287
 288         WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
 289                  RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
 290                  ~RANGE0_PWM_FEEDBACK_DIV_MASK);
 291
 292         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
 293                (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
 294                 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
 295
 296         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
 297                (RANGE0_PWM(fv_throt_pwm_range[1]) |
 298                 RANGE1_PWM(fv_throt_pwm_range[2])));
 299         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
 300                (RANGE2_PWM(fv_throt_pwm_range[1]) |
 301                 RANGE3_PWM(fv_throt_pwm_range[2])));
 302 }
 303
 304 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
 305 {
 306         if (enable)
 307                 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
 308                          ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
 309         else
 310                 WREG32_P(FVTHROT_CNTRL_REG, 0,
 311                          ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
 312 }
 313
 314 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
 315 {
 316         if (enable)
 317                 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
 318         else
 319                 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
 320 }
 321
 322 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
 323 {
 324         WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
 325         WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
 326         WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
 327         WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
 328         WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
 329
 330         WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
 331         WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
 332         WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
 333         WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
 334         WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
 335 }
 336
 337 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
 338 {
 339         WREG32_P(FVTHROT_FBDIV_REG2,
 340                  FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
 341                  ~FB_DIV_TIMER_VAL_MASK);
 342
 343         WREG32_P(FVTHROT_CNTRL_REG,
 344                  REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
 345                  ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
 346 }
 347
 348 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
 349 {
 350         WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
 351 }
 352
 353 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
 354 {
 355         WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
 356         WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
 357         WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
 358         WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
 359
 360         WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
 361 }
 362
 363 static void rs780_program_at(struct radeon_device *rdev)
 364 {
 365         struct igp_power_info *pi = rs780_get_pi(rdev);
 366
 367         WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
 368         WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
 369         WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
 370         WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
 371         WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
 372 }
 373
 374 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
 375 {
 376         WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
 377 }
 378
 379 static void rs780_force_voltage_to_high(struct radeon_device *rdev)
 380 {
 381         struct igp_power_info *pi = rs780_get_pi(rdev);
 382         struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
 383
 384         if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
 385             (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
 386                 return;
 387
 388         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 389
 390         udelay(1);
 391
 392         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 393                  STARTING_PWM_HIGHTIME(pi->max_voltage),
 394                  ~STARTING_PWM_HIGHTIME_MASK);
 395
 396         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 397                  FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
 398
 399         WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
 400                 ~RANGE_PWM_FEEDBACK_DIV_EN);
 401
 402         udelay(1);
 403
 404         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 405 }
 406
 407 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
 408                                           struct radeon_ps *new_ps,
 409                                           struct radeon_ps *old_ps)
 410 {
 411         struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
 412         struct igp_ps *new_state = rs780_get_ps(new_ps);
 413         struct igp_ps *old_state = rs780_get_ps(old_ps);
 414         int ret;
 415
 416         if ((new_state->sclk_high == old_state->sclk_high) &&
 417             (new_state->sclk_low == old_state->sclk_low))
 418                 return 0;
 419
 420         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 421                                              new_state->sclk_low, false, &min_dividers);
 422         if (ret)
 423                 return ret;
 424
 425         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 426                                              new_state->sclk_high, false, &max_dividers);
 427         if (ret)
 428                 return ret;
 429
 430         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 431                                              old_state->sclk_high, false, &current_max_dividers);
 432         if (ret)
 433                 return ret;
 434
 435         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 436
 437         WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div),
 438                  ~FORCED_FEEDBACK_DIV_MASK);
 439         WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div),
 440                  ~STARTING_FEEDBACK_DIV_MASK);
 441         WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
 442
 443         udelay(100);
 444
 445         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 446
 447         if (max_dividers.fb_div > min_dividers.fb_div) {
 448                 WREG32_P(FVTHROT_FBDIV_REG0,
 449                          MIN_FEEDBACK_DIV(min_dividers.fb_div) |
 450                          MAX_FEEDBACK_DIV(max_dividers.fb_div),
 451                          ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
 452
 453                 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
 454         }
 455
 456         return 0;
 457 }
 458
 459 static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
 460                                        struct radeon_ps *new_ps,
 461                                        struct radeon_ps *old_ps)
 462 {
 463         struct igp_ps *new_state = rs780_get_ps(new_ps);
 464         struct igp_ps *old_state = rs780_get_ps(old_ps);
 465         struct igp_power_info *pi = rs780_get_pi(rdev);
 466
 467         if ((new_state->sclk_high == old_state->sclk_high) &&
 468             (new_state->sclk_low == old_state->sclk_low))
 469                 return;
 470
 471         if (pi->crtc_id == 0)
 472                 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
 473         else
 474                 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
 475
 476 }
 477
 478 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
 479                                               struct radeon_ps *new_ps,
 480                                               struct radeon_ps *old_ps)
 481 {
 482         struct igp_ps *new_state = rs780_get_ps(new_ps);
 483         struct igp_ps *old_state = rs780_get_ps(old_ps);
 484
 485         if ((new_state->sclk_high == old_state->sclk_high) &&
 486             (new_state->sclk_low == old_state->sclk_low))
 487                 return;
 488
 489         rs780_clk_scaling_enable(rdev, true);
 490 }
 491
 492 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
 493                                             enum rs780_vddc_level vddc)
 494 {
 495         struct igp_power_info *pi = rs780_get_pi(rdev);
 496
 497         if (vddc == RS780_VDDC_LEVEL_HIGH)
 498                 return pi->max_voltage;
 499         else if (vddc == RS780_VDDC_LEVEL_LOW)
 500                 return pi->min_voltage;
 501         else
 502                 return pi->max_voltage;
 503 }
 504
 505 static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
 506                                          struct radeon_ps *new_ps)
 507 {
 508         struct igp_ps *new_state = rs780_get_ps(new_ps);
 509         struct igp_power_info *pi = rs780_get_pi(rdev);
 510         enum rs780_vddc_level vddc_high, vddc_low;
 511
 512         udelay(100);
 513
 514         if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
 515             (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
 516                 return;
 517
 518         vddc_high = rs780_get_voltage_for_vddc_level(rdev,
 519                                                      new_state->max_voltage);
 520         vddc_low = rs780_get_voltage_for_vddc_level(rdev,
 521                                                     new_state->min_voltage);
 522
 523         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 524
 525         udelay(1);
 526         if (vddc_high > vddc_low) {
 527                 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
 528                          RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
 529
 530                 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
 531         } else if (vddc_high == vddc_low) {
 532                 if (pi->max_voltage != vddc_high) {
 533                         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 534                                  STARTING_PWM_HIGHTIME(vddc_high),
 535                                  ~STARTING_PWM_HIGHTIME_MASK);
 536
 537                         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 538                                  FORCE_STARTING_PWM_HIGHTIME,
 539                                  ~FORCE_STARTING_PWM_HIGHTIME);
 540                 }
 541         }
 542
 543         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 544 }
 545
 546 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 547                                                      struct radeon_ps *new_ps,
 548                                                      struct radeon_ps *old_ps)
 549 {
 550         struct igp_ps *new_state = rs780_get_ps(new_ps);
 551         struct igp_ps *current_state = rs780_get_ps(old_ps);
 552
 553         if ((new_ps->vclk == old_ps->vclk) &&
 554             (new_ps->dclk == old_ps->dclk))
 555                 return;
 556
 557         if (new_state->sclk_high >= current_state->sclk_high)
 558                 return;
 559
 560         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
 561 }
 562
 563 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 564                                                     struct radeon_ps *new_ps,
 565                                                     struct radeon_ps *old_ps)
 566 {
 567         struct igp_ps *new_state = rs780_get_ps(new_ps);
 568         struct igp_ps *current_state = rs780_get_ps(old_ps);
 569
 570         if ((new_ps->vclk == old_ps->vclk) &&
 571             (new_ps->dclk == old_ps->dclk))
 572                 return;
 573
 574         if (new_state->sclk_high < current_state->sclk_high)
 575                 return;
 576
 577         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
 578 }
 579
 580 int rs780_dpm_enable(struct radeon_device *rdev)
 581 {
 582         struct igp_power_info *pi = rs780_get_pi(rdev);
 583         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
 584         int ret;
 585
 586         rs780_get_pm_mode_parameters(rdev);
 587         rs780_disable_vbios_powersaving(rdev);
 588
 589         if (r600_dynamicpm_enabled(rdev))
 590                 return -EINVAL;
 591         ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
 592         if (ret)
 593                 return ret;
 594         rs780_start_dpm(rdev);
 595
 596         rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
 597         rs780_preset_starting_fbdiv(rdev);
 598         if (pi->voltage_control)
 599                 rs780_voltage_scaling_init(rdev);
 600         rs780_clk_scaling_enable(rdev, true);
 601         rs780_set_engine_clock_sc(rdev);
 602         rs780_set_engine_clock_wfc(rdev);
 603         rs780_program_at(rdev);
 604         rs780_set_engine_clock_tdc(rdev);
 605         rs780_set_engine_clock_ssc(rdev);
 606
 607         if (pi->gfx_clock_gating)
 608                 r600_gfx_clockgating_enable(rdev, true);
 609
 610         if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
 611                 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
 612                 if (ret)
 613                         return ret;
 614                 rdev->irq.dpm_thermal = true;
 615                 radeon_irq_set(rdev);
 616         }
 617
 618         return 0;
 619 }
 620
 621 void rs780_dpm_disable(struct radeon_device *rdev)
 622 {
 623         struct igp_power_info *pi = rs780_get_pi(rdev);
 624
 625         r600_dynamicpm_enable(rdev, false);
 626
 627         rs780_clk_scaling_enable(rdev, false);
 628         rs780_voltage_scaling_enable(rdev, false);
 629
 630         if (pi->gfx_clock_gating)
 631                 r600_gfx_clockgating_enable(rdev, false);
 632
 633         if (rdev->irq.installed &&
 634             (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
 635                 rdev->irq.dpm_thermal = false;
 636                 radeon_irq_set(rdev);
 637         }
 638 }
 639
 640 int rs780_dpm_set_power_state(struct radeon_device *rdev)
 641 {
 642         struct igp_power_info *pi = rs780_get_pi(rdev);
 643         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
 644         struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
 645         int ret;
 646
 647         rs780_get_pm_mode_parameters(rdev);
 648
 649         rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
 650
 651         if (pi->voltage_control) {
 652                 rs780_force_voltage_to_high(rdev);
 653                 mdelay(5);
 654         }
 655
 656         ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
 657         if (ret)
 658                 return ret;
 659         rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
 660
 661         rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
 662
 663         if (pi->voltage_control)
 664                 rs780_enable_voltage_scaling(rdev, new_ps);
 665
 666         rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
 667
 668         return 0;
 669 }
 670
 671 void rs780_dpm_setup_asic(struct radeon_device *rdev)
 672 {
 673
 674 }
 675
 676 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
 677 {
 678         rs780_get_pm_mode_parameters(rdev);
 679         rs780_program_at(rdev);
 680 }
 681
 682 union igp_info {
 683         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 684         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 685 };
 686
 687 union power_info {
 688         struct _ATOM_POWERPLAY_INFO info;
 689         struct _ATOM_POWERPLAY_INFO_V2 info_2;
 690         struct _ATOM_POWERPLAY_INFO_V3 info_3;
 691         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 692         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
 693         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
 694 };
 695
 696 union pplib_clock_info {
 697         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
 698         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
 699         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
 700         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
 701 };
 702
 703 union pplib_power_state {
 704         struct _ATOM_PPLIB_STATE v1;
 705         struct _ATOM_PPLIB_STATE_V2 v2;
 706 };
 707
 708 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
 709                                              struct radeon_ps *rps,
 710                                              struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
 711                                              u8 table_rev)
 712 {
 713         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
 714         rps->class = le16_to_cpu(non_clock_info->usClassification);
 715         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
 716
 717         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
 718                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
 719                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
 720         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
 721                 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
 722                 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
 723         } else {
 724                 rps->vclk = 0;
 725                 rps->dclk = 0;
 726         }
 727
 728         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
 729                 rdev->pm.dpm.boot_ps = rps;
 730         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
 731                 rdev->pm.dpm.uvd_ps = rps;
 732 }
 733
 734 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
 735                                          struct radeon_ps *rps,
 736                                          union pplib_clock_info *clock_info)
 737 {
 738         struct igp_ps *ps = rs780_get_ps(rps);
 739         u32 sclk;
 740
 741         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
 742         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
 743         ps->sclk_low = sclk;
 744         sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
 745         sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
 746         ps->sclk_high = sclk;
 747         switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
 748         case ATOM_PPLIB_RS780_VOLTAGE_NONE:
 749         default:
 750                 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
 751                 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
 752                 break;
 753         case ATOM_PPLIB_RS780_VOLTAGE_LOW:
 754                 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
 755                 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
 756                 break;
 757         case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
 758                 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
 759                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 760                 break;
 761         case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
 762                 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
 763                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 764                 break;
 765         }
 766         ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
 767
 768         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
 769                 ps->sclk_low = rdev->clock.default_sclk;
 770                 ps->sclk_high = rdev->clock.default_sclk;
 771                 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
 772                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 773         }
 774 }
 775
 776 static int rs780_parse_power_table(struct radeon_device *rdev)
 777 {
 778         struct radeon_mode_info *mode_info = &rdev->mode_info;
 779         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
 780         union pplib_power_state *power_state;
 781         int i;
 782         union pplib_clock_info *clock_info;
 783         union power_info *power_info;
 784         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 785         u16 data_offset;
 786         u8 frev, crev;
 787         struct igp_ps *ps;
 788
 789         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
 790                                    &frev, &crev, &data_offset))
 791                 return -EINVAL;
 792         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 793
 794         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
 795                                   power_info->pplib.ucNumStates, GFP_KERNEL);
 796         if (!rdev->pm.dpm.ps)
 797                 return -ENOMEM;
 798         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
 799         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
 800         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
 801
 802         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
 803                 power_state = (union pplib_power_state *)
 804                         (mode_info->atom_context->bios + data_offset +
 805                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
 806                          i * power_info->pplib.ucStateEntrySize);
 807                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
 808                         (mode_info->atom_context->bios + data_offset +
 809                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
 810                          (power_state->v1.ucNonClockStateIndex *
 811                           power_info->pplib.ucNonClockSize));
 812                 if (power_info->pplib.ucStateEntrySize - 1) {
 813                         clock_info = (union pplib_clock_info *)
 814                                 (mode_info->atom_context->bios + data_offset +
 815                                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
 816                                  (power_state->v1.ucClockStateIndices[0] *
 817                                   power_info->pplib.ucClockInfoSize));
 818                         ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
 819                         if (ps == NULL) {
 820                                 kfree(rdev->pm.dpm.ps);
 821                                 return -ENOMEM;
 822                         }
 823                         rdev->pm.dpm.ps[i].ps_priv = ps;
 824                         rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
 825                                                          non_clock_info,
 826                                                          power_info->pplib.ucNonClockSize);
 827                         rs780_parse_pplib_clock_info(rdev,
 828                                                      &rdev->pm.dpm.ps[i],
 829                                                      clock_info);
 830                 }
 831         }
 832         rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
 833         return 0;
 834 }
 835
 836 int rs780_dpm_init(struct radeon_device *rdev)
 837 {
 838         struct igp_power_info *pi;
 839         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 840         union igp_info *info;
 841         u16 data_offset;
 842         u8 frev, crev;
 843         int ret;
 844
 845         pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
 846         if (pi == NULL)
 847                 return -ENOMEM;
 848         rdev->pm.dpm.priv = pi;
 849
 850         ret = rs780_parse_power_table(rdev);
 851         if (ret)
 852                 return ret;
 853
 854         pi->voltage_control = false;
 855         pi->gfx_clock_gating = true;
 856
 857         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
 858                                    &frev, &crev, &data_offset)) {
 859                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
 860
 861                 /* Get various system informations from bios */
 862                 switch (crev) {
 863                 case 1:
 864                         pi->num_of_cycles_in_period =
 865                                 info->info.ucNumberOfCyclesInPeriod;
 866                         pi->num_of_cycles_in_period |=
 867                                 info->info.ucNumberOfCyclesInPeriodHi << 8;
 868                         pi->invert_pwm_required =
 869                                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
 870                         pi->boot_voltage = info->info.ucStartingPWM_HighTime;
 871                         pi->max_voltage = info->info.ucMaxNBVoltage;
 872                         pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
 873                         pi->min_voltage = info->info.ucMinNBVoltage;
 874                         pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
 875                         pi->inter_voltage_low =
 876                                 le16_to_cpu(info->info.usInterNBVoltageLow);
 877                         pi->inter_voltage_high =
 878                                 le16_to_cpu(info->info.usInterNBVoltageHigh);
 879                         pi->voltage_control = true;
 880                         pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
 881                         break;
 882                 case 2:
 883                         pi->num_of_cycles_in_period =
 884                                 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
 885                         pi->invert_pwm_required =
 886                                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
 887                         pi->boot_voltage =
 888                                 le16_to_cpu(info->info_2.usBootUpNBVoltage);
 889                         pi->max_voltage =
 890                                 le16_to_cpu(info->info_2.usMaxNBVoltage);
 891                         pi->min_voltage =
 892                                 le16_to_cpu(info->info_2.usMinNBVoltage);
 893                         pi->system_config =
 894                                 le32_to_cpu(info->info_2.ulSystemConfig);
 895                         pi->pwm_voltage_control =
 896                                 (pi->system_config & 0x4) ? true : false;
 897                         pi->voltage_control = true;
 898                         pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
 899                         break;
 900                 default:
 901                         DRM_ERROR("No integrated system info for your GPU\n");
 902                         return -EINVAL;
 903                 }
 904                 if (pi->min_voltage > pi->max_voltage)
 905                         pi->voltage_control = false;
 906                 if (pi->pwm_voltage_control) {
 907                         if ((pi->num_of_cycles_in_period == 0) ||
 908                             (pi->max_voltage == 0) ||
 909                             (pi->min_voltage == 0))
 910                                 pi->voltage_control = false;
 911                 } else {
 912                         if ((pi->num_of_cycles_in_period == 0) ||
 913                             (pi->max_voltage == 0))
 914                                 pi->voltage_control = false;
 915                 }
 916
 917                 return 0;
 918         }
 919         radeon_dpm_fini(rdev);
 920         return -EINVAL;
 921 }
 922
 923 void rs780_dpm_print_power_state(struct radeon_device *rdev,
 924                                  struct radeon_ps *rps)
 925 {
 926         struct igp_ps *ps = rs780_get_ps(rps);
 927
 928         r600_dpm_print_class_info(rps->class, rps->class2);
 929         r600_dpm_print_cap_info(rps->caps);
 930         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 931         printk("\t\tpower level 0    sclk: %u vddc_index: %d\n",
 932                ps->sclk_low, ps->min_voltage);
 933         printk("\t\tpower level 1    sclk: %u vddc_index: %d\n",
 934                ps->sclk_high, ps->max_voltage);
 935         r600_dpm_print_ps_status(rdev, rps);
 936 }
 937
 938 void rs780_dpm_fini(struct radeon_device *rdev)
 939 {
 940         int i;
 941
 942         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 943                 kfree(rdev->pm.dpm.ps[i].ps_priv);
 944         }
 945         kfree(rdev->pm.dpm.ps);
 946         kfree(rdev->pm.dpm.priv);
 947 }
 948
 949 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
 950 {
 951         struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
 952
 953         if (low)
 954                 return requested_state->sclk_low;
 955         else
 956                 return requested_state->sclk_high;
 957 }
 958
 959 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
 960 {
 961         struct igp_power_info *pi = rs780_get_pi(rdev);
 962
 963         return pi->bootup_uma_clk;
 964 }
 965
 966 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 967                                                        struct seq_file *m)
 968 {
 969         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
 970         struct igp_ps *ps = rs780_get_ps(rps);
 971         u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
 972         u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
 973         u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
 974         u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
 975                 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
 976         u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
 977                 (post_div * ref_div);
 978
 979         seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 980
 981         /* guess based on the current sclk */
 982         if (sclk < (ps->sclk_low + 500))
 983                 seq_printf(m, "power level 0    sclk: %u vddc_index: %d\n",
 984                            ps->sclk_low, ps->min_voltage);
 985         else
 986                 seq_printf(m, "power level 1    sclk: %u vddc_index: %d\n",
 987                            ps->sclk_high, ps->max_voltage);
 988 }