2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
45 void rv770_pm_misc(struct radeon_device *rdev)
47 int requested_index = rdev->pm.requested_power_state_index;
48 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
49 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
52 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
53 if (voltage->voltage != rdev->pm.current_vddc) {
54 radeon_atom_set_voltage(rdev, voltage->voltage);
55 rdev->pm.current_vddc = voltage->voltage;
63 int rv770_pcie_gart_enable(struct radeon_device *rdev)
68 if (rdev->gart.table.vram.robj == NULL) {
69 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
72 r = radeon_gart_table_vram_pin(rdev);
75 radeon_gart_restore(rdev);
77 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
78 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
79 EFFECTIVE_L2_QUEUE_SIZE(7));
80 WREG32(VM_L2_CNTL2, 0);
81 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
82 /* Setup TLB control */
83 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
84 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
85 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
86 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
87 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
88 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
89 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
90 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
91 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
92 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
93 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
94 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
95 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
96 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
97 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
98 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
99 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
100 (u32)(rdev->dummy_page.addr >> 12));
101 for (i = 1; i < 7; i++)
102 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
104 r600_pcie_gart_tlb_flush(rdev);
105 rdev->gart.ready = true;
109 void rv770_pcie_gart_disable(struct radeon_device *rdev)
114 /* Disable all tables */
115 for (i = 0; i < 7; i++)
116 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
119 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
120 EFFECTIVE_L2_QUEUE_SIZE(7));
121 WREG32(VM_L2_CNTL2, 0);
122 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
123 /* Setup TLB control */
124 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
125 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
126 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
127 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
128 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
129 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
130 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
131 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
132 if (rdev->gart.table.vram.robj) {
133 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
134 if (likely(r == 0)) {
135 radeon_bo_kunmap(rdev->gart.table.vram.robj);
136 radeon_bo_unpin(rdev->gart.table.vram.robj);
137 radeon_bo_unreserve(rdev->gart.table.vram.robj);
142 void rv770_pcie_gart_fini(struct radeon_device *rdev)
144 radeon_gart_fini(rdev);
145 rv770_pcie_gart_disable(rdev);
146 radeon_gart_table_vram_free(rdev);
150 void rv770_agp_enable(struct radeon_device *rdev)
156 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
157 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
158 EFFECTIVE_L2_QUEUE_SIZE(7));
159 WREG32(VM_L2_CNTL2, 0);
160 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
161 /* Setup TLB control */
162 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
163 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
164 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
165 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
166 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
167 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
168 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
169 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
170 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
171 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
172 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
173 for (i = 0; i < 7; i++)
174 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
177 static void rv770_mc_program(struct radeon_device *rdev)
179 struct rv515_mc_save save;
184 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
185 WREG32((0x2c14 + j), 0x00000000);
186 WREG32((0x2c18 + j), 0x00000000);
187 WREG32((0x2c1c + j), 0x00000000);
188 WREG32((0x2c20 + j), 0x00000000);
189 WREG32((0x2c24 + j), 0x00000000);
191 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
193 rv515_mc_stop(rdev, &save);
194 if (r600_mc_wait_for_idle(rdev)) {
195 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
197 /* Lockout access through VGA aperture*/
198 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
199 /* Update configuration */
200 if (rdev->flags & RADEON_IS_AGP) {
201 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
202 /* VRAM before AGP */
203 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
204 rdev->mc.vram_start >> 12);
205 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
206 rdev->mc.gtt_end >> 12);
209 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
210 rdev->mc.gtt_start >> 12);
211 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
212 rdev->mc.vram_end >> 12);
215 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
216 rdev->mc.vram_start >> 12);
217 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
218 rdev->mc.vram_end >> 12);
220 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
221 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
222 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
223 WREG32(MC_VM_FB_LOCATION, tmp);
224 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
225 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
226 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
227 if (rdev->flags & RADEON_IS_AGP) {
228 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
229 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
230 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
232 WREG32(MC_VM_AGP_BASE, 0);
233 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
234 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
236 if (r600_mc_wait_for_idle(rdev)) {
237 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
239 rv515_mc_resume(rdev, &save);
240 /* we need to own VRAM, so turn off the VGA renderer here
241 * to stop it overwriting our objects */
242 rv515_vga_render_disable(rdev);
249 void r700_cp_stop(struct radeon_device *rdev)
251 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
254 static int rv770_cp_load_microcode(struct radeon_device *rdev)
256 const __be32 *fw_data;
259 if (!rdev->me_fw || !rdev->pfp_fw)
263 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
266 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
267 RREG32(GRBM_SOFT_RESET);
269 WREG32(GRBM_SOFT_RESET, 0);
271 fw_data = (const __be32 *)rdev->pfp_fw->data;
272 WREG32(CP_PFP_UCODE_ADDR, 0);
273 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
274 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
275 WREG32(CP_PFP_UCODE_ADDR, 0);
277 fw_data = (const __be32 *)rdev->me_fw->data;
278 WREG32(CP_ME_RAM_WADDR, 0);
279 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
280 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
282 WREG32(CP_PFP_UCODE_ADDR, 0);
283 WREG32(CP_ME_RAM_WADDR, 0);
284 WREG32(CP_ME_RAM_RADDR, 0);
288 void r700_cp_fini(struct radeon_device *rdev)
291 radeon_ring_fini(rdev);
297 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
300 u32 backend_disable_mask)
303 u32 enabled_backends_mask;
304 u32 enabled_backends_count;
306 u32 swizzle_pipe[R7XX_MAX_PIPES];
309 bool force_no_swizzle;
311 if (num_tile_pipes > R7XX_MAX_PIPES)
312 num_tile_pipes = R7XX_MAX_PIPES;
313 if (num_tile_pipes < 1)
315 if (num_backends > R7XX_MAX_BACKENDS)
316 num_backends = R7XX_MAX_BACKENDS;
317 if (num_backends < 1)
320 enabled_backends_mask = 0;
321 enabled_backends_count = 0;
322 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
323 if (((backend_disable_mask >> i) & 1) == 0) {
324 enabled_backends_mask |= (1 << i);
325 ++enabled_backends_count;
327 if (enabled_backends_count == num_backends)
331 if (enabled_backends_count == 0) {
332 enabled_backends_mask = 1;
333 enabled_backends_count = 1;
336 if (enabled_backends_count != num_backends)
337 num_backends = enabled_backends_count;
339 switch (rdev->family) {
342 force_no_swizzle = false;
347 force_no_swizzle = true;
351 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
352 switch (num_tile_pipes) {
361 if (force_no_swizzle) {
372 if (force_no_swizzle) {
385 if (force_no_swizzle) {
400 if (force_no_swizzle) {
417 if (force_no_swizzle) {
436 if (force_no_swizzle) {
459 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
460 while (((1 << cur_backend) & enabled_backends_mask) == 0)
461 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
463 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
465 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
471 static void rv770_gpu_init(struct radeon_device *rdev)
473 int i, j, num_qd_pipes;
478 u32 num_gs_verts_per_thread;
480 u32 gs_prim_buffer_depth = 0;
481 u32 sq_ms_fifo_sizes;
483 u32 sq_thread_resource_mgmt;
484 u32 hdp_host_path_cntl;
485 u32 sq_dyn_gpr_size_simd_ab_0;
487 u32 gb_tiling_config = 0;
488 u32 cc_rb_backend_disable = 0;
489 u32 cc_gc_shader_pipe_config = 0;
493 /* setup chip specs */
494 switch (rdev->family) {
496 rdev->config.rv770.max_pipes = 4;
497 rdev->config.rv770.max_tile_pipes = 8;
498 rdev->config.rv770.max_simds = 10;
499 rdev->config.rv770.max_backends = 4;
500 rdev->config.rv770.max_gprs = 256;
501 rdev->config.rv770.max_threads = 248;
502 rdev->config.rv770.max_stack_entries = 512;
503 rdev->config.rv770.max_hw_contexts = 8;
504 rdev->config.rv770.max_gs_threads = 16 * 2;
505 rdev->config.rv770.sx_max_export_size = 128;
506 rdev->config.rv770.sx_max_export_pos_size = 16;
507 rdev->config.rv770.sx_max_export_smx_size = 112;
508 rdev->config.rv770.sq_num_cf_insts = 2;
510 rdev->config.rv770.sx_num_of_sets = 7;
511 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
512 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
513 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
516 rdev->config.rv770.max_pipes = 2;
517 rdev->config.rv770.max_tile_pipes = 4;
518 rdev->config.rv770.max_simds = 8;
519 rdev->config.rv770.max_backends = 2;
520 rdev->config.rv770.max_gprs = 128;
521 rdev->config.rv770.max_threads = 248;
522 rdev->config.rv770.max_stack_entries = 256;
523 rdev->config.rv770.max_hw_contexts = 8;
524 rdev->config.rv770.max_gs_threads = 16 * 2;
525 rdev->config.rv770.sx_max_export_size = 256;
526 rdev->config.rv770.sx_max_export_pos_size = 32;
527 rdev->config.rv770.sx_max_export_smx_size = 224;
528 rdev->config.rv770.sq_num_cf_insts = 2;
530 rdev->config.rv770.sx_num_of_sets = 7;
531 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
532 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
533 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
534 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
535 rdev->config.rv770.sx_max_export_pos_size -= 16;
536 rdev->config.rv770.sx_max_export_smx_size += 16;
540 rdev->config.rv770.max_pipes = 2;
541 rdev->config.rv770.max_tile_pipes = 2;
542 rdev->config.rv770.max_simds = 2;
543 rdev->config.rv770.max_backends = 1;
544 rdev->config.rv770.max_gprs = 256;
545 rdev->config.rv770.max_threads = 192;
546 rdev->config.rv770.max_stack_entries = 256;
547 rdev->config.rv770.max_hw_contexts = 4;
548 rdev->config.rv770.max_gs_threads = 8 * 2;
549 rdev->config.rv770.sx_max_export_size = 128;
550 rdev->config.rv770.sx_max_export_pos_size = 16;
551 rdev->config.rv770.sx_max_export_smx_size = 112;
552 rdev->config.rv770.sq_num_cf_insts = 1;
554 rdev->config.rv770.sx_num_of_sets = 7;
555 rdev->config.rv770.sc_prim_fifo_size = 0x40;
556 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
557 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
560 rdev->config.rv770.max_pipes = 4;
561 rdev->config.rv770.max_tile_pipes = 4;
562 rdev->config.rv770.max_simds = 8;
563 rdev->config.rv770.max_backends = 4;
564 rdev->config.rv770.max_gprs = 256;
565 rdev->config.rv770.max_threads = 248;
566 rdev->config.rv770.max_stack_entries = 512;
567 rdev->config.rv770.max_hw_contexts = 8;
568 rdev->config.rv770.max_gs_threads = 16 * 2;
569 rdev->config.rv770.sx_max_export_size = 256;
570 rdev->config.rv770.sx_max_export_pos_size = 32;
571 rdev->config.rv770.sx_max_export_smx_size = 224;
572 rdev->config.rv770.sq_num_cf_insts = 2;
574 rdev->config.rv770.sx_num_of_sets = 7;
575 rdev->config.rv770.sc_prim_fifo_size = 0x100;
576 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
577 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
579 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
580 rdev->config.rv770.sx_max_export_pos_size -= 16;
581 rdev->config.rv770.sx_max_export_smx_size += 16;
590 for (i = 0; i < 32; i++) {
591 WREG32((0x2c14 + j), 0x00000000);
592 WREG32((0x2c18 + j), 0x00000000);
593 WREG32((0x2c1c + j), 0x00000000);
594 WREG32((0x2c20 + j), 0x00000000);
595 WREG32((0x2c24 + j), 0x00000000);
599 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
601 /* setup tiling, simd, pipe config */
602 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
604 switch (rdev->config.rv770.max_tile_pipes) {
607 gb_tiling_config |= PIPE_TILING(0);
610 gb_tiling_config |= PIPE_TILING(1);
613 gb_tiling_config |= PIPE_TILING(2);
616 gb_tiling_config |= PIPE_TILING(3);
619 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
621 if (rdev->family == CHIP_RV770)
622 gb_tiling_config |= BANK_TILING(1);
624 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
625 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
627 gb_tiling_config |= GROUP_SIZE(0);
628 rdev->config.rv770.tiling_group_size = 256;
630 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
631 gb_tiling_config |= ROW_TILING(3);
632 gb_tiling_config |= SAMPLE_SPLIT(3);
635 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
637 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
640 gb_tiling_config |= BANK_SWAPS(1);
642 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
643 cc_rb_backend_disable |=
644 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
646 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
647 cc_gc_shader_pipe_config |=
648 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
649 cc_gc_shader_pipe_config |=
650 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
652 if (rdev->family == CHIP_RV740)
655 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
656 rdev->config.rv770.max_tile_pipes,
658 r600_count_pipe_bits((cc_rb_backend_disable &
659 R7XX_MAX_BACKENDS_MASK) >> 16)),
660 (cc_rb_backend_disable >> 16));
661 gb_tiling_config |= BACKEND_MAP(backend_map);
664 WREG32(GB_TILING_CONFIG, gb_tiling_config);
665 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
666 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
668 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
669 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
670 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
671 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
673 WREG32(CGTS_SYS_TCC_DISABLE, 0);
674 WREG32(CGTS_TCC_DISABLE, 0);
675 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
676 WREG32(CGTS_USER_TCC_DISABLE, 0);
679 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
680 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
681 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
683 /* set HW defaults for 3D engine */
684 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
685 ROQ_IB2_START(0x2b)));
687 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
689 ta_aux_cntl = RREG32(TA_CNTL_AUX);
690 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
692 sx_debug_1 = RREG32(SX_DEBUG_1);
693 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
694 WREG32(SX_DEBUG_1, sx_debug_1);
696 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
697 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
698 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
699 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
701 if (rdev->family != CHIP_RV740)
702 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
707 db_debug3 = RREG32(DB_DEBUG3);
708 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
709 switch (rdev->family) {
712 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
717 db_debug3 |= DB_CLK_OFF_DELAY(2);
720 WREG32(DB_DEBUG3, db_debug3);
722 if (rdev->family != CHIP_RV770) {
723 db_debug4 = RREG32(DB_DEBUG4);
724 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
725 WREG32(DB_DEBUG4, db_debug4);
728 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
729 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
730 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
732 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
733 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
734 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
736 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
738 WREG32(VGT_NUM_INSTANCES, 1);
740 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
742 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
744 WREG32(CP_PERFMON_CNTL, 0);
746 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
747 DONE_FIFO_HIWATER(0xe0) |
748 ALU_UPDATE_FIFO_HIWATER(0x8));
749 switch (rdev->family) {
753 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
757 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
760 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
762 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
763 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
765 sq_config = RREG32(SQ_CONFIG);
766 sq_config &= ~(PS_PRIO(3) |
770 sq_config |= (DX9_CONSTS |
777 if (rdev->family == CHIP_RV710)
778 /* no vertex cache */
779 sq_config &= ~VC_ENABLE;
781 WREG32(SQ_CONFIG, sq_config);
783 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
784 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
785 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
787 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
788 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
790 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
791 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
792 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
793 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
794 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
796 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
797 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
799 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
800 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
802 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
803 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
805 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
806 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
807 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
808 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
810 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
811 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
812 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
813 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
814 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
815 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
816 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
817 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
819 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
820 FORCE_EOV_MAX_REZ_CNT(255)));
822 if (rdev->family == CHIP_RV710)
823 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
824 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
826 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
827 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
829 switch (rdev->family) {
833 gs_prim_buffer_depth = 384;
836 gs_prim_buffer_depth = 128;
842 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
843 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
844 /* Max value for this is 256 */
845 if (vgt_gs_per_es > 256)
848 WREG32(VGT_ES_PER_GS, 128);
849 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
850 WREG32(VGT_GS_PER_VS, 2);
852 /* more default values. 2D/3D driver should adjust as needed */
853 WREG32(VGT_GS_VERTEX_REUSE, 16);
854 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
855 WREG32(VGT_STRMOUT_EN, 0);
857 WREG32(PA_SC_MODE_CNTL, 0);
858 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
859 WREG32(PA_SC_AA_CONFIG, 0);
860 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
861 WREG32(PA_SC_LINE_STIPPLE, 0);
862 WREG32(SPI_INPUT_Z, 0);
863 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
864 WREG32(CB_COLOR7_FRAG, 0);
866 /* clear render buffer base addresses */
867 WREG32(CB_COLOR0_BASE, 0);
868 WREG32(CB_COLOR1_BASE, 0);
869 WREG32(CB_COLOR2_BASE, 0);
870 WREG32(CB_COLOR3_BASE, 0);
871 WREG32(CB_COLOR4_BASE, 0);
872 WREG32(CB_COLOR5_BASE, 0);
873 WREG32(CB_COLOR6_BASE, 0);
874 WREG32(CB_COLOR7_BASE, 0);
878 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
879 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
881 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
883 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
888 int rv770_mc_init(struct radeon_device *rdev)
891 int chansize, numchan;
893 /* Get VRAM informations */
894 rdev->mc.vram_is_ddr = true;
895 tmp = RREG32(MC_ARB_RAMCFG);
896 if (tmp & CHANSIZE_OVERRIDE) {
898 } else if (tmp & CHANSIZE_MASK) {
903 tmp = RREG32(MC_SHARED_CHMAP);
904 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
919 rdev->mc.vram_width = numchan * chansize;
920 /* Could aper size report 0 ? */
921 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
922 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
923 /* Setup GPU memory space */
924 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
925 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
926 rdev->mc.visible_vram_size = rdev->mc.aper_size;
927 r600_vram_gtt_location(rdev, &rdev->mc);
928 radeon_update_bandwidth_info(rdev);
933 static int rv770_startup(struct radeon_device *rdev)
937 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
938 r = r600_init_microcode(rdev);
940 DRM_ERROR("Failed to load firmware!\n");
945 rv770_mc_program(rdev);
946 if (rdev->flags & RADEON_IS_AGP) {
947 rv770_agp_enable(rdev);
949 r = rv770_pcie_gart_enable(rdev);
953 rv770_gpu_init(rdev);
954 r = r600_blit_init(rdev);
956 r600_blit_fini(rdev);
957 rdev->asic->copy = NULL;
958 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
960 /* pin copy shader into vram */
961 if (rdev->r600_blit.shader_obj) {
962 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
963 if (unlikely(r != 0))
965 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
966 &rdev->r600_blit.shader_gpu_addr);
967 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
969 DRM_ERROR("failed to pin blit object %d\n", r);
974 r = r600_irq_init(rdev);
976 DRM_ERROR("radeon: IH init failed (%d).\n", r);
977 radeon_irq_kms_fini(rdev);
982 r = radeon_ring_init(rdev, rdev->cp.ring_size);
985 r = rv770_cp_load_microcode(rdev);
988 r = r600_cp_resume(rdev);
991 /* write back buffer are not vital so don't worry about failure */
992 r600_wb_enable(rdev);
996 int rv770_resume(struct radeon_device *rdev)
1000 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1001 * posting will perform necessary task to bring back GPU into good
1005 atom_asic_init(rdev->mode_info.atom_context);
1006 /* Initialize clocks */
1007 r = radeon_clocks_init(rdev);
1012 r = rv770_startup(rdev);
1014 DRM_ERROR("r600 startup failed on resume\n");
1018 r = r600_ib_test(rdev);
1020 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1024 r = r600_audio_init(rdev);
1026 dev_err(rdev->dev, "radeon: audio init failed\n");
1034 int rv770_suspend(struct radeon_device *rdev)
1038 r600_audio_fini(rdev);
1039 /* FIXME: we should wait for ring to be empty */
1041 rdev->cp.ready = false;
1042 r600_irq_suspend(rdev);
1043 r600_wb_disable(rdev);
1044 rv770_pcie_gart_disable(rdev);
1045 /* unpin shaders bo */
1046 if (rdev->r600_blit.shader_obj) {
1047 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1048 if (likely(r == 0)) {
1049 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1050 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1056 /* Plan is to move initialization in that function and use
1057 * helper function so that radeon_device_init pretty much
1058 * do nothing more than calling asic specific function. This
1059 * should also allow to remove a bunch of callback function
1062 int rv770_init(struct radeon_device *rdev)
1066 r = radeon_dummy_page_init(rdev);
1069 /* This don't do much */
1070 r = radeon_gem_init(rdev);
1074 if (!radeon_get_bios(rdev)) {
1075 if (ASIC_IS_AVIVO(rdev))
1078 /* Must be an ATOMBIOS */
1079 if (!rdev->is_atom_bios) {
1080 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1083 r = radeon_atombios_init(rdev);
1086 /* Post card if necessary */
1087 if (!r600_card_posted(rdev)) {
1089 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1092 DRM_INFO("GPU not posted. posting now...\n");
1093 atom_asic_init(rdev->mode_info.atom_context);
1095 /* Initialize scratch registers */
1096 r600_scratch_init(rdev);
1097 /* Initialize surface registers */
1098 radeon_surface_init(rdev);
1099 /* Initialize clocks */
1100 radeon_get_clock_info(rdev->ddev);
1101 r = radeon_clocks_init(rdev);
1105 r = radeon_fence_driver_init(rdev);
1108 /* initialize AGP */
1109 if (rdev->flags & RADEON_IS_AGP) {
1110 r = radeon_agp_init(rdev);
1112 radeon_agp_disable(rdev);
1114 r = rv770_mc_init(rdev);
1117 /* Memory manager */
1118 r = radeon_bo_init(rdev);
1122 r = radeon_irq_kms_init(rdev);
1126 rdev->cp.ring_obj = NULL;
1127 r600_ring_init(rdev, 1024 * 1024);
1129 rdev->ih.ring_obj = NULL;
1130 r600_ih_ring_init(rdev, 64 * 1024);
1132 r = r600_pcie_gart_init(rdev);
1136 rdev->accel_working = true;
1137 r = rv770_startup(rdev);
1139 dev_err(rdev->dev, "disabling GPU acceleration\n");
1142 r600_irq_fini(rdev);
1143 radeon_irq_kms_fini(rdev);
1144 rv770_pcie_gart_fini(rdev);
1145 rdev->accel_working = false;
1147 if (rdev->accel_working) {
1148 r = radeon_ib_pool_init(rdev);
1150 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1151 rdev->accel_working = false;
1153 r = r600_ib_test(rdev);
1155 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1156 rdev->accel_working = false;
1161 r = r600_audio_init(rdev);
1163 dev_err(rdev->dev, "radeon: audio init failed\n");
1170 void rv770_fini(struct radeon_device *rdev)
1172 r600_blit_fini(rdev);
1175 r600_irq_fini(rdev);
1176 radeon_irq_kms_fini(rdev);
1177 rv770_pcie_gart_fini(rdev);
1178 radeon_gem_fini(rdev);
1179 radeon_fence_driver_fini(rdev);
1180 radeon_clocks_fini(rdev);
1181 radeon_agp_fini(rdev);
1182 radeon_bo_fini(rdev);
1183 radeon_atombios_fini(rdev);
1186 radeon_dummy_page_fini(rdev);