2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
45 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
48 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50 /* Lock the graphics update lock */
51 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
52 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
54 /* update the scanout addresses */
55 if (radeon_crtc->crtc_id) {
56 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
57 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
60 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
64 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
67 /* Wait for update_pending to go high. */
68 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
69 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
71 /* Unlock the lock, so double-buffering can take place inside vblank */
72 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
73 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
75 /* Return current update_pending status: */
76 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
79 /* get temperature in millidegrees */
80 u32 rv770_get_temp(struct radeon_device *rdev)
82 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
89 actual_temp = (temp >> 1) & 0xff;
91 return actual_temp * 1000;
94 void rv770_pm_misc(struct radeon_device *rdev)
96 int req_ps_idx = rdev->pm.requested_power_state_index;
97 int req_cm_idx = rdev->pm.requested_clock_mode_index;
98 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
99 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
101 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
102 if (voltage->voltage != rdev->pm.current_vddc) {
103 radeon_atom_set_voltage(rdev, voltage->voltage);
104 rdev->pm.current_vddc = voltage->voltage;
105 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
113 int rv770_pcie_gart_enable(struct radeon_device *rdev)
118 if (rdev->gart.table.vram.robj == NULL) {
119 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
122 r = radeon_gart_table_vram_pin(rdev);
125 radeon_gart_restore(rdev);
127 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
128 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
129 EFFECTIVE_L2_QUEUE_SIZE(7));
130 WREG32(VM_L2_CNTL2, 0);
131 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
132 /* Setup TLB control */
133 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
134 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
135 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
136 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
137 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
138 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
139 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
140 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
141 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
142 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
143 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
144 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
145 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
146 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
147 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
148 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
149 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
150 (u32)(rdev->dummy_page.addr >> 12));
151 for (i = 1; i < 7; i++)
152 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
154 r600_pcie_gart_tlb_flush(rdev);
155 rdev->gart.ready = true;
159 void rv770_pcie_gart_disable(struct radeon_device *rdev)
164 /* Disable all tables */
165 for (i = 0; i < 7; i++)
166 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
169 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
170 EFFECTIVE_L2_QUEUE_SIZE(7));
171 WREG32(VM_L2_CNTL2, 0);
172 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
173 /* Setup TLB control */
174 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
175 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
176 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
177 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
178 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
179 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
180 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
181 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
182 if (rdev->gart.table.vram.robj) {
183 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
184 if (likely(r == 0)) {
185 radeon_bo_kunmap(rdev->gart.table.vram.robj);
186 radeon_bo_unpin(rdev->gart.table.vram.robj);
187 radeon_bo_unreserve(rdev->gart.table.vram.robj);
192 void rv770_pcie_gart_fini(struct radeon_device *rdev)
194 radeon_gart_fini(rdev);
195 rv770_pcie_gart_disable(rdev);
196 radeon_gart_table_vram_free(rdev);
200 void rv770_agp_enable(struct radeon_device *rdev)
206 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
207 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
208 EFFECTIVE_L2_QUEUE_SIZE(7));
209 WREG32(VM_L2_CNTL2, 0);
210 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
211 /* Setup TLB control */
212 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
213 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
214 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
215 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
216 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
217 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
218 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
219 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
220 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
221 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
222 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
223 for (i = 0; i < 7; i++)
224 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
227 static void rv770_mc_program(struct radeon_device *rdev)
229 struct rv515_mc_save save;
234 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
235 WREG32((0x2c14 + j), 0x00000000);
236 WREG32((0x2c18 + j), 0x00000000);
237 WREG32((0x2c1c + j), 0x00000000);
238 WREG32((0x2c20 + j), 0x00000000);
239 WREG32((0x2c24 + j), 0x00000000);
241 /* r7xx hw bug. Read from HDP_DEBUG1 rather
242 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
244 tmp = RREG32(HDP_DEBUG1);
246 rv515_mc_stop(rdev, &save);
247 if (r600_mc_wait_for_idle(rdev)) {
248 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
250 /* Lockout access through VGA aperture*/
251 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
252 /* Update configuration */
253 if (rdev->flags & RADEON_IS_AGP) {
254 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
255 /* VRAM before AGP */
256 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
257 rdev->mc.vram_start >> 12);
258 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
259 rdev->mc.gtt_end >> 12);
262 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
263 rdev->mc.gtt_start >> 12);
264 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
265 rdev->mc.vram_end >> 12);
268 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 rdev->mc.vram_start >> 12);
270 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 rdev->mc.vram_end >> 12);
273 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
274 if (rdev->flags & RADEON_IS_IGP) {
275 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
276 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
277 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
278 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
280 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
281 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
282 WREG32(MC_VM_FB_LOCATION, tmp);
283 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
284 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
285 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
286 if (rdev->flags & RADEON_IS_AGP) {
287 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
288 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
289 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
291 WREG32(MC_VM_AGP_BASE, 0);
292 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
293 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
295 if (r600_mc_wait_for_idle(rdev)) {
296 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
298 rv515_mc_resume(rdev, &save);
299 /* we need to own VRAM, so turn off the VGA renderer here
300 * to stop it overwriting our objects */
301 rv515_vga_render_disable(rdev);
308 void r700_cp_stop(struct radeon_device *rdev)
310 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
311 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
312 WREG32(SCRATCH_UMSK, 0);
315 static int rv770_cp_load_microcode(struct radeon_device *rdev)
317 const __be32 *fw_data;
320 if (!rdev->me_fw || !rdev->pfp_fw)
324 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
327 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
328 RREG32(GRBM_SOFT_RESET);
330 WREG32(GRBM_SOFT_RESET, 0);
332 fw_data = (const __be32 *)rdev->pfp_fw->data;
333 WREG32(CP_PFP_UCODE_ADDR, 0);
334 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
335 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
336 WREG32(CP_PFP_UCODE_ADDR, 0);
338 fw_data = (const __be32 *)rdev->me_fw->data;
339 WREG32(CP_ME_RAM_WADDR, 0);
340 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
341 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344 WREG32(CP_ME_RAM_WADDR, 0);
345 WREG32(CP_ME_RAM_RADDR, 0);
349 void r700_cp_fini(struct radeon_device *rdev)
352 radeon_ring_fini(rdev);
358 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
361 u32 backend_disable_mask)
364 u32 enabled_backends_mask;
365 u32 enabled_backends_count;
367 u32 swizzle_pipe[R7XX_MAX_PIPES];
370 bool force_no_swizzle;
372 if (num_tile_pipes > R7XX_MAX_PIPES)
373 num_tile_pipes = R7XX_MAX_PIPES;
374 if (num_tile_pipes < 1)
376 if (num_backends > R7XX_MAX_BACKENDS)
377 num_backends = R7XX_MAX_BACKENDS;
378 if (num_backends < 1)
381 enabled_backends_mask = 0;
382 enabled_backends_count = 0;
383 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
384 if (((backend_disable_mask >> i) & 1) == 0) {
385 enabled_backends_mask |= (1 << i);
386 ++enabled_backends_count;
388 if (enabled_backends_count == num_backends)
392 if (enabled_backends_count == 0) {
393 enabled_backends_mask = 1;
394 enabled_backends_count = 1;
397 if (enabled_backends_count != num_backends)
398 num_backends = enabled_backends_count;
400 switch (rdev->family) {
403 force_no_swizzle = false;
408 force_no_swizzle = true;
412 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
413 switch (num_tile_pipes) {
422 if (force_no_swizzle) {
433 if (force_no_swizzle) {
446 if (force_no_swizzle) {
461 if (force_no_swizzle) {
478 if (force_no_swizzle) {
497 if (force_no_swizzle) {
520 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
521 while (((1 << cur_backend) & enabled_backends_mask) == 0)
522 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
524 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
526 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
532 static void rv770_program_channel_remap(struct radeon_device *rdev)
534 u32 tcp_chan_steer, mc_shared_chremap, tmp;
535 bool force_no_swizzle;
537 switch (rdev->family) {
540 force_no_swizzle = false;
545 force_no_swizzle = true;
549 tmp = RREG32(MC_SHARED_CHMAP);
550 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
554 /* default mapping */
555 mc_shared_chremap = 0x00fac688;
559 if (force_no_swizzle)
560 mc_shared_chremap = 0x00fac688;
562 mc_shared_chremap = 0x00bbc298;
566 if (rdev->family == CHIP_RV740)
567 tcp_chan_steer = 0x00ef2a60;
569 tcp_chan_steer = 0x00fac688;
571 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
572 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
575 static void rv770_gpu_init(struct radeon_device *rdev)
577 int i, j, num_qd_pipes;
582 u32 num_gs_verts_per_thread;
584 u32 gs_prim_buffer_depth = 0;
585 u32 sq_ms_fifo_sizes;
587 u32 sq_thread_resource_mgmt;
588 u32 hdp_host_path_cntl;
589 u32 sq_dyn_gpr_size_simd_ab_0;
591 u32 gb_tiling_config = 0;
592 u32 cc_rb_backend_disable = 0;
593 u32 cc_gc_shader_pipe_config = 0;
597 /* setup chip specs */
598 switch (rdev->family) {
600 rdev->config.rv770.max_pipes = 4;
601 rdev->config.rv770.max_tile_pipes = 8;
602 rdev->config.rv770.max_simds = 10;
603 rdev->config.rv770.max_backends = 4;
604 rdev->config.rv770.max_gprs = 256;
605 rdev->config.rv770.max_threads = 248;
606 rdev->config.rv770.max_stack_entries = 512;
607 rdev->config.rv770.max_hw_contexts = 8;
608 rdev->config.rv770.max_gs_threads = 16 * 2;
609 rdev->config.rv770.sx_max_export_size = 128;
610 rdev->config.rv770.sx_max_export_pos_size = 16;
611 rdev->config.rv770.sx_max_export_smx_size = 112;
612 rdev->config.rv770.sq_num_cf_insts = 2;
614 rdev->config.rv770.sx_num_of_sets = 7;
615 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
616 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
617 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
620 rdev->config.rv770.max_pipes = 2;
621 rdev->config.rv770.max_tile_pipes = 4;
622 rdev->config.rv770.max_simds = 8;
623 rdev->config.rv770.max_backends = 2;
624 rdev->config.rv770.max_gprs = 128;
625 rdev->config.rv770.max_threads = 248;
626 rdev->config.rv770.max_stack_entries = 256;
627 rdev->config.rv770.max_hw_contexts = 8;
628 rdev->config.rv770.max_gs_threads = 16 * 2;
629 rdev->config.rv770.sx_max_export_size = 256;
630 rdev->config.rv770.sx_max_export_pos_size = 32;
631 rdev->config.rv770.sx_max_export_smx_size = 224;
632 rdev->config.rv770.sq_num_cf_insts = 2;
634 rdev->config.rv770.sx_num_of_sets = 7;
635 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
636 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
637 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
638 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
639 rdev->config.rv770.sx_max_export_pos_size -= 16;
640 rdev->config.rv770.sx_max_export_smx_size += 16;
644 rdev->config.rv770.max_pipes = 2;
645 rdev->config.rv770.max_tile_pipes = 2;
646 rdev->config.rv770.max_simds = 2;
647 rdev->config.rv770.max_backends = 1;
648 rdev->config.rv770.max_gprs = 256;
649 rdev->config.rv770.max_threads = 192;
650 rdev->config.rv770.max_stack_entries = 256;
651 rdev->config.rv770.max_hw_contexts = 4;
652 rdev->config.rv770.max_gs_threads = 8 * 2;
653 rdev->config.rv770.sx_max_export_size = 128;
654 rdev->config.rv770.sx_max_export_pos_size = 16;
655 rdev->config.rv770.sx_max_export_smx_size = 112;
656 rdev->config.rv770.sq_num_cf_insts = 1;
658 rdev->config.rv770.sx_num_of_sets = 7;
659 rdev->config.rv770.sc_prim_fifo_size = 0x40;
660 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
661 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
664 rdev->config.rv770.max_pipes = 4;
665 rdev->config.rv770.max_tile_pipes = 4;
666 rdev->config.rv770.max_simds = 8;
667 rdev->config.rv770.max_backends = 4;
668 rdev->config.rv770.max_gprs = 256;
669 rdev->config.rv770.max_threads = 248;
670 rdev->config.rv770.max_stack_entries = 512;
671 rdev->config.rv770.max_hw_contexts = 8;
672 rdev->config.rv770.max_gs_threads = 16 * 2;
673 rdev->config.rv770.sx_max_export_size = 256;
674 rdev->config.rv770.sx_max_export_pos_size = 32;
675 rdev->config.rv770.sx_max_export_smx_size = 224;
676 rdev->config.rv770.sq_num_cf_insts = 2;
678 rdev->config.rv770.sx_num_of_sets = 7;
679 rdev->config.rv770.sc_prim_fifo_size = 0x100;
680 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
681 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
683 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
684 rdev->config.rv770.sx_max_export_pos_size -= 16;
685 rdev->config.rv770.sx_max_export_smx_size += 16;
694 for (i = 0; i < 32; i++) {
695 WREG32((0x2c14 + j), 0x00000000);
696 WREG32((0x2c18 + j), 0x00000000);
697 WREG32((0x2c1c + j), 0x00000000);
698 WREG32((0x2c20 + j), 0x00000000);
699 WREG32((0x2c24 + j), 0x00000000);
703 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
705 /* setup tiling, simd, pipe config */
706 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
708 switch (rdev->config.rv770.max_tile_pipes) {
711 gb_tiling_config |= PIPE_TILING(0);
714 gb_tiling_config |= PIPE_TILING(1);
717 gb_tiling_config |= PIPE_TILING(2);
720 gb_tiling_config |= PIPE_TILING(3);
723 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
725 if (rdev->family == CHIP_RV770)
726 gb_tiling_config |= BANK_TILING(1);
728 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
729 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
730 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
731 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
732 rdev->config.rv770.tiling_group_size = 512;
734 rdev->config.rv770.tiling_group_size = 256;
735 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
736 gb_tiling_config |= ROW_TILING(3);
737 gb_tiling_config |= SAMPLE_SPLIT(3);
740 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
742 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
745 gb_tiling_config |= BANK_SWAPS(1);
747 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
748 cc_rb_backend_disable |=
749 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
751 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
752 cc_gc_shader_pipe_config |=
753 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
754 cc_gc_shader_pipe_config |=
755 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
757 if (rdev->family == CHIP_RV740)
760 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
761 rdev->config.rv770.max_tile_pipes,
763 r600_count_pipe_bits((cc_rb_backend_disable &
764 R7XX_MAX_BACKENDS_MASK) >> 16)),
765 (cc_rb_backend_disable >> 16));
767 rdev->config.rv770.tile_config = gb_tiling_config;
768 gb_tiling_config |= BACKEND_MAP(backend_map);
770 WREG32(GB_TILING_CONFIG, gb_tiling_config);
771 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
772 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
774 rv770_program_channel_remap(rdev);
776 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
777 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
778 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
779 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
781 WREG32(CGTS_SYS_TCC_DISABLE, 0);
782 WREG32(CGTS_TCC_DISABLE, 0);
783 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
784 WREG32(CGTS_USER_TCC_DISABLE, 0);
787 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
788 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
789 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
791 /* set HW defaults for 3D engine */
792 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
793 ROQ_IB2_START(0x2b)));
795 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
797 ta_aux_cntl = RREG32(TA_CNTL_AUX);
798 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
800 sx_debug_1 = RREG32(SX_DEBUG_1);
801 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
802 WREG32(SX_DEBUG_1, sx_debug_1);
804 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
805 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
806 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
807 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
809 if (rdev->family != CHIP_RV740)
810 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
815 db_debug3 = RREG32(DB_DEBUG3);
816 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
817 switch (rdev->family) {
820 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
825 db_debug3 |= DB_CLK_OFF_DELAY(2);
828 WREG32(DB_DEBUG3, db_debug3);
830 if (rdev->family != CHIP_RV770) {
831 db_debug4 = RREG32(DB_DEBUG4);
832 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
833 WREG32(DB_DEBUG4, db_debug4);
836 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
837 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
838 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
840 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
841 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
842 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
844 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
846 WREG32(VGT_NUM_INSTANCES, 1);
848 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
850 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
852 WREG32(CP_PERFMON_CNTL, 0);
854 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
855 DONE_FIFO_HIWATER(0xe0) |
856 ALU_UPDATE_FIFO_HIWATER(0x8));
857 switch (rdev->family) {
861 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
865 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
868 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
870 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
871 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
873 sq_config = RREG32(SQ_CONFIG);
874 sq_config &= ~(PS_PRIO(3) |
878 sq_config |= (DX9_CONSTS |
885 if (rdev->family == CHIP_RV710)
886 /* no vertex cache */
887 sq_config &= ~VC_ENABLE;
889 WREG32(SQ_CONFIG, sq_config);
891 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
892 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
893 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
895 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
896 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
898 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
899 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
900 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
901 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
902 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
904 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
905 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
907 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
908 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
910 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
911 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
913 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
914 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
915 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
916 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
918 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
919 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
920 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
921 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
922 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
923 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
924 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
925 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
927 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
928 FORCE_EOV_MAX_REZ_CNT(255)));
930 if (rdev->family == CHIP_RV710)
931 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
932 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
934 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
935 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
937 switch (rdev->family) {
941 gs_prim_buffer_depth = 384;
944 gs_prim_buffer_depth = 128;
950 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
951 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
952 /* Max value for this is 256 */
953 if (vgt_gs_per_es > 256)
956 WREG32(VGT_ES_PER_GS, 128);
957 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
958 WREG32(VGT_GS_PER_VS, 2);
960 /* more default values. 2D/3D driver should adjust as needed */
961 WREG32(VGT_GS_VERTEX_REUSE, 16);
962 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
963 WREG32(VGT_STRMOUT_EN, 0);
965 WREG32(PA_SC_MODE_CNTL, 0);
966 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
967 WREG32(PA_SC_AA_CONFIG, 0);
968 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
969 WREG32(PA_SC_LINE_STIPPLE, 0);
970 WREG32(SPI_INPUT_Z, 0);
971 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
972 WREG32(CB_COLOR7_FRAG, 0);
974 /* clear render buffer base addresses */
975 WREG32(CB_COLOR0_BASE, 0);
976 WREG32(CB_COLOR1_BASE, 0);
977 WREG32(CB_COLOR2_BASE, 0);
978 WREG32(CB_COLOR3_BASE, 0);
979 WREG32(CB_COLOR4_BASE, 0);
980 WREG32(CB_COLOR5_BASE, 0);
981 WREG32(CB_COLOR6_BASE, 0);
982 WREG32(CB_COLOR7_BASE, 0);
986 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
987 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
989 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
991 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
996 static int rv770_vram_scratch_init(struct radeon_device *rdev)
1001 if (rdev->vram_scratch.robj == NULL) {
1002 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
1003 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1004 &rdev->vram_scratch.robj);
1010 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1011 if (unlikely(r != 0))
1013 r = radeon_bo_pin(rdev->vram_scratch.robj,
1014 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
1016 radeon_bo_unreserve(rdev->vram_scratch.robj);
1019 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1020 (void **)&rdev->vram_scratch.ptr);
1022 radeon_bo_unpin(rdev->vram_scratch.robj);
1023 radeon_bo_unreserve(rdev->vram_scratch.robj);
1028 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
1032 if (rdev->vram_scratch.robj == NULL) {
1035 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1036 if (likely(r == 0)) {
1037 radeon_bo_kunmap(rdev->vram_scratch.robj);
1038 radeon_bo_unpin(rdev->vram_scratch.robj);
1039 radeon_bo_unreserve(rdev->vram_scratch.robj);
1041 radeon_bo_unref(&rdev->vram_scratch.robj);
1044 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1046 u64 size_bf, size_af;
1048 if (mc->mc_vram_size > 0xE0000000) {
1049 /* leave room for at least 512M GTT */
1050 dev_warn(rdev->dev, "limiting VRAM\n");
1051 mc->real_vram_size = 0xE0000000;
1052 mc->mc_vram_size = 0xE0000000;
1054 if (rdev->flags & RADEON_IS_AGP) {
1055 size_bf = mc->gtt_start;
1056 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1057 if (size_bf > size_af) {
1058 if (mc->mc_vram_size > size_bf) {
1059 dev_warn(rdev->dev, "limiting VRAM\n");
1060 mc->real_vram_size = size_bf;
1061 mc->mc_vram_size = size_bf;
1063 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1065 if (mc->mc_vram_size > size_af) {
1066 dev_warn(rdev->dev, "limiting VRAM\n");
1067 mc->real_vram_size = size_af;
1068 mc->mc_vram_size = size_af;
1070 mc->vram_start = mc->gtt_end;
1072 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1073 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1074 mc->mc_vram_size >> 20, mc->vram_start,
1075 mc->vram_end, mc->real_vram_size >> 20);
1078 if (rdev->flags & RADEON_IS_IGP) {
1079 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1080 base |= RREG32(MC_FUS_VM_FB_OFFSET) & 0x00F00000;
1082 radeon_vram_location(rdev, &rdev->mc, base);
1083 rdev->mc.gtt_base_align = 0;
1084 radeon_gtt_location(rdev, mc);
1088 int rv770_mc_init(struct radeon_device *rdev)
1091 int chansize, numchan;
1093 /* Get VRAM informations */
1094 rdev->mc.vram_is_ddr = true;
1095 tmp = RREG32(MC_ARB_RAMCFG);
1096 if (tmp & CHANSIZE_OVERRIDE) {
1098 } else if (tmp & CHANSIZE_MASK) {
1103 tmp = RREG32(MC_SHARED_CHMAP);
1104 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1119 rdev->mc.vram_width = numchan * chansize;
1120 /* Could aper size report 0 ? */
1121 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1122 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1123 /* Setup GPU memory space */
1124 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1125 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1126 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1127 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1128 r700_vram_gtt_location(rdev, &rdev->mc);
1129 radeon_update_bandwidth_info(rdev);
1134 static int rv770_startup(struct radeon_device *rdev)
1138 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1139 r = r600_init_microcode(rdev);
1141 DRM_ERROR("Failed to load firmware!\n");
1146 rv770_mc_program(rdev);
1147 if (rdev->flags & RADEON_IS_AGP) {
1148 rv770_agp_enable(rdev);
1150 r = rv770_pcie_gart_enable(rdev);
1154 r = rv770_vram_scratch_init(rdev);
1157 rv770_gpu_init(rdev);
1158 r = r600_blit_init(rdev);
1160 r600_blit_fini(rdev);
1161 rdev->asic->copy = NULL;
1162 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1165 /* allocate wb buffer */
1166 r = radeon_wb_init(rdev);
1171 r = r600_irq_init(rdev);
1173 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1174 radeon_irq_kms_fini(rdev);
1179 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1182 r = rv770_cp_load_microcode(rdev);
1185 r = r600_cp_resume(rdev);
1192 int rv770_resume(struct radeon_device *rdev)
1196 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1197 * posting will perform necessary task to bring back GPU into good
1201 atom_asic_init(rdev->mode_info.atom_context);
1203 r = rv770_startup(rdev);
1205 DRM_ERROR("r600 startup failed on resume\n");
1209 r = r600_ib_test(rdev);
1211 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1215 r = r600_audio_init(rdev);
1217 dev_err(rdev->dev, "radeon: audio init failed\n");
1225 int rv770_suspend(struct radeon_device *rdev)
1229 r600_audio_fini(rdev);
1230 /* FIXME: we should wait for ring to be empty */
1232 rdev->cp.ready = false;
1233 r600_irq_suspend(rdev);
1234 radeon_wb_disable(rdev);
1235 rv770_pcie_gart_disable(rdev);
1236 /* unpin shaders bo */
1237 if (rdev->r600_blit.shader_obj) {
1238 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1239 if (likely(r == 0)) {
1240 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1241 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1247 /* Plan is to move initialization in that function and use
1248 * helper function so that radeon_device_init pretty much
1249 * do nothing more than calling asic specific function. This
1250 * should also allow to remove a bunch of callback function
1253 int rv770_init(struct radeon_device *rdev)
1257 r = radeon_dummy_page_init(rdev);
1260 /* This don't do much */
1261 r = radeon_gem_init(rdev);
1265 if (!radeon_get_bios(rdev)) {
1266 if (ASIC_IS_AVIVO(rdev))
1269 /* Must be an ATOMBIOS */
1270 if (!rdev->is_atom_bios) {
1271 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1274 r = radeon_atombios_init(rdev);
1277 /* Post card if necessary */
1278 if (!r600_card_posted(rdev)) {
1280 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1283 DRM_INFO("GPU not posted. posting now...\n");
1284 atom_asic_init(rdev->mode_info.atom_context);
1286 /* Initialize scratch registers */
1287 r600_scratch_init(rdev);
1288 /* Initialize surface registers */
1289 radeon_surface_init(rdev);
1290 /* Initialize clocks */
1291 radeon_get_clock_info(rdev->ddev);
1293 r = radeon_fence_driver_init(rdev);
1296 /* initialize AGP */
1297 if (rdev->flags & RADEON_IS_AGP) {
1298 r = radeon_agp_init(rdev);
1300 radeon_agp_disable(rdev);
1302 r = rv770_mc_init(rdev);
1305 /* Memory manager */
1306 r = radeon_bo_init(rdev);
1310 r = radeon_irq_kms_init(rdev);
1314 rdev->cp.ring_obj = NULL;
1315 r600_ring_init(rdev, 1024 * 1024);
1317 rdev->ih.ring_obj = NULL;
1318 r600_ih_ring_init(rdev, 64 * 1024);
1320 r = r600_pcie_gart_init(rdev);
1324 rdev->accel_working = true;
1325 r = rv770_startup(rdev);
1327 dev_err(rdev->dev, "disabling GPU acceleration\n");
1329 r600_irq_fini(rdev);
1330 radeon_wb_fini(rdev);
1331 radeon_irq_kms_fini(rdev);
1332 rv770_pcie_gart_fini(rdev);
1333 rdev->accel_working = false;
1335 if (rdev->accel_working) {
1336 r = radeon_ib_pool_init(rdev);
1338 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1339 rdev->accel_working = false;
1341 r = r600_ib_test(rdev);
1343 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1344 rdev->accel_working = false;
1349 r = r600_audio_init(rdev);
1351 dev_err(rdev->dev, "radeon: audio init failed\n");
1358 void rv770_fini(struct radeon_device *rdev)
1360 r600_blit_fini(rdev);
1362 r600_irq_fini(rdev);
1363 radeon_wb_fini(rdev);
1364 radeon_irq_kms_fini(rdev);
1365 rv770_pcie_gart_fini(rdev);
1366 rv770_vram_scratch_fini(rdev);
1367 radeon_gem_fini(rdev);
1368 radeon_fence_driver_fini(rdev);
1369 radeon_agp_fini(rdev);
1370 radeon_bo_fini(rdev);
1371 radeon_atombios_fini(rdev);
1374 radeon_dummy_page_fini(rdev);