drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44
  45 /* get temperature in millidegrees */
  46 u32 rv770_get_temp(struct radeon_device *rdev)
  47 {
  48         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  49                 ASIC_T_SHIFT;
  50         u32 actual_temp = 0;
  51
  52         if ((temp >> 9) & 1)
  53                 actual_temp = 0;
  54         else
  55                 actual_temp = (temp >> 1) & 0xff;
  56
  57         return actual_temp * 1000;
  58 }
  59
  60 void rv770_pm_misc(struct radeon_device *rdev)
  61 {
  62         int req_ps_idx = rdev->pm.requested_power_state_index;
  63         int req_cm_idx = rdev->pm.requested_clock_mode_index;
  64         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  65         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  66
  67         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
  68                 if (voltage->voltage != rdev->pm.current_vddc) {
  69                         radeon_atom_set_voltage(rdev, voltage->voltage);
  70                         rdev->pm.current_vddc = voltage->voltage;
  71                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
  72                 }
  73         }
  74 }
  75
  76 /*
  77  * GART
  78  */
  79 int rv770_pcie_gart_enable(struct radeon_device *rdev)
  80 {
  81         u32 tmp;
  82         int r, i;
  83
  84         if (rdev->gart.table.vram.robj == NULL) {
  85                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  86                 return -EINVAL;
  87         }
  88         r = radeon_gart_table_vram_pin(rdev);
  89         if (r)
  90                 return r;
  91         radeon_gart_restore(rdev);
  92         /* Setup L2 cache */
  93         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  94                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  95                                 EFFECTIVE_L2_QUEUE_SIZE(7));
  96         WREG32(VM_L2_CNTL2, 0);
  97         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  98         /* Setup TLB control */
  99         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 100                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 101                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 102                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 103         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 104         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 105         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 106         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 107         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 108         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 109         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 110         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 111         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 112         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 113         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 114                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 115         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 116                         (u32)(rdev->dummy_page.addr >> 12));
 117         for (i = 1; i < 7; i++)
 118                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 119
 120         r600_pcie_gart_tlb_flush(rdev);
 121         rdev->gart.ready = true;
 122         return 0;
 123 }
 124
 125 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 126 {
 127         u32 tmp;
 128         int i, r;
 129
 130         /* Disable all tables */
 131         for (i = 0; i < 7; i++)
 132                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 133
 134         /* Setup L2 cache */
 135         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 136                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 137         WREG32(VM_L2_CNTL2, 0);
 138         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 139         /* Setup TLB control */
 140         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 141         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 142         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 143         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 144         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 145         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 146         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 147         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 148         if (rdev->gart.table.vram.robj) {
 149                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 150                 if (likely(r == 0)) {
 151                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 152                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 153                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 154                 }
 155         }
 156 }
 157
 158 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 159 {
 160         radeon_gart_fini(rdev);
 161         rv770_pcie_gart_disable(rdev);
 162         radeon_gart_table_vram_free(rdev);
 163 }
 164
 165
 166 void rv770_agp_enable(struct radeon_device *rdev)
 167 {
 168         u32 tmp;
 169         int i;
 170
 171         /* Setup L2 cache */
 172         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 173                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 174                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 175         WREG32(VM_L2_CNTL2, 0);
 176         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 177         /* Setup TLB control */
 178         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 179                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 180                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 181                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 182         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 183         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 184         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 185         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 186         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 187         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 188         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 189         for (i = 0; i < 7; i++)
 190                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 191 }
 192
 193 static void rv770_mc_program(struct radeon_device *rdev)
 194 {
 195         struct rv515_mc_save save;
 196         u32 tmp;
 197         int i, j;
 198
 199         /* Initialize HDP */
 200         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 201                 WREG32((0x2c14 + j), 0x00000000);
 202                 WREG32((0x2c18 + j), 0x00000000);
 203                 WREG32((0x2c1c + j), 0x00000000);
 204                 WREG32((0x2c20 + j), 0x00000000);
 205                 WREG32((0x2c24 + j), 0x00000000);
 206         }
 207         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 208
 209         rv515_mc_stop(rdev, &save);
 210         if (r600_mc_wait_for_idle(rdev)) {
 211                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 212         }
 213         /* Lockout access through VGA aperture*/
 214         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 215         /* Update configuration */
 216         if (rdev->flags & RADEON_IS_AGP) {
 217                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 218                         /* VRAM before AGP */
 219                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 220                                 rdev->mc.vram_start >> 12);
 221                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 222                                 rdev->mc.gtt_end >> 12);
 223                 } else {
 224                         /* VRAM after AGP */
 225                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 226                                 rdev->mc.gtt_start >> 12);
 227                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 228                                 rdev->mc.vram_end >> 12);
 229                 }
 230         } else {
 231                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 232                         rdev->mc.vram_start >> 12);
 233                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 234                         rdev->mc.vram_end >> 12);
 235         }
 236         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 237         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 238         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 239         WREG32(MC_VM_FB_LOCATION, tmp);
 240         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 241         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 242         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 243         if (rdev->flags & RADEON_IS_AGP) {
 244                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 245                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 246                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 247         } else {
 248                 WREG32(MC_VM_AGP_BASE, 0);
 249                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 250                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 251         }
 252         if (r600_mc_wait_for_idle(rdev)) {
 253                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 254         }
 255         rv515_mc_resume(rdev, &save);
 256         /* we need to own VRAM, so turn off the VGA renderer here
 257          * to stop it overwriting our objects */
 258         rv515_vga_render_disable(rdev);
 259 }
 260
 261
 262 /*
 263  * CP.
 264  */
 265 void r700_cp_stop(struct radeon_device *rdev)
 266 {
 267         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 268 }
 269
 270 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 271 {
 272         const __be32 *fw_data;
 273         int i;
 274
 275         if (!rdev->me_fw || !rdev->pfp_fw)
 276                 return -EINVAL;
 277
 278         r700_cp_stop(rdev);
 279         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 280
 281         /* Reset cp */
 282         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 283         RREG32(GRBM_SOFT_RESET);
 284         mdelay(15);
 285         WREG32(GRBM_SOFT_RESET, 0);
 286
 287         fw_data = (const __be32 *)rdev->pfp_fw->data;
 288         WREG32(CP_PFP_UCODE_ADDR, 0);
 289         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 290                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 291         WREG32(CP_PFP_UCODE_ADDR, 0);
 292
 293         fw_data = (const __be32 *)rdev->me_fw->data;
 294         WREG32(CP_ME_RAM_WADDR, 0);
 295         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 296                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 297
 298         WREG32(CP_PFP_UCODE_ADDR, 0);
 299         WREG32(CP_ME_RAM_WADDR, 0);
 300         WREG32(CP_ME_RAM_RADDR, 0);
 301         return 0;
 302 }
 303
 304 void r700_cp_fini(struct radeon_device *rdev)
 305 {
 306         r700_cp_stop(rdev);
 307         radeon_ring_fini(rdev);
 308 }
 309
 310 /*
 311  * Core functions
 312  */
 313 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 314                                              u32 num_tile_pipes,
 315                                              u32 num_backends,
 316                                              u32 backend_disable_mask)
 317 {
 318         u32 backend_map = 0;
 319         u32 enabled_backends_mask;
 320         u32 enabled_backends_count;
 321         u32 cur_pipe;
 322         u32 swizzle_pipe[R7XX_MAX_PIPES];
 323         u32 cur_backend;
 324         u32 i;
 325         bool force_no_swizzle;
 326
 327         if (num_tile_pipes > R7XX_MAX_PIPES)
 328                 num_tile_pipes = R7XX_MAX_PIPES;
 329         if (num_tile_pipes < 1)
 330                 num_tile_pipes = 1;
 331         if (num_backends > R7XX_MAX_BACKENDS)
 332                 num_backends = R7XX_MAX_BACKENDS;
 333         if (num_backends < 1)
 334                 num_backends = 1;
 335
 336         enabled_backends_mask = 0;
 337         enabled_backends_count = 0;
 338         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 339                 if (((backend_disable_mask >> i) & 1) == 0) {
 340                         enabled_backends_mask |= (1 << i);
 341                         ++enabled_backends_count;
 342                 }
 343                 if (enabled_backends_count == num_backends)
 344                         break;
 345         }
 346
 347         if (enabled_backends_count == 0) {
 348                 enabled_backends_mask = 1;
 349                 enabled_backends_count = 1;
 350         }
 351
 352         if (enabled_backends_count != num_backends)
 353                 num_backends = enabled_backends_count;
 354
 355         switch (rdev->family) {
 356         case CHIP_RV770:
 357         case CHIP_RV730:
 358                 force_no_swizzle = false;
 359                 break;
 360         case CHIP_RV710:
 361         case CHIP_RV740:
 362         default:
 363                 force_no_swizzle = true;
 364                 break;
 365         }
 366
 367         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 368         switch (num_tile_pipes) {
 369         case 1:
 370                 swizzle_pipe[0] = 0;
 371                 break;
 372         case 2:
 373                 swizzle_pipe[0] = 0;
 374                 swizzle_pipe[1] = 1;
 375                 break;
 376         case 3:
 377                 if (force_no_swizzle) {
 378                         swizzle_pipe[0] = 0;
 379                         swizzle_pipe[1] = 1;
 380                         swizzle_pipe[2] = 2;
 381                 } else {
 382                         swizzle_pipe[0] = 0;
 383                         swizzle_pipe[1] = 2;
 384                         swizzle_pipe[2] = 1;
 385                 }
 386                 break;
 387         case 4:
 388                 if (force_no_swizzle) {
 389                         swizzle_pipe[0] = 0;
 390                         swizzle_pipe[1] = 1;
 391                         swizzle_pipe[2] = 2;
 392                         swizzle_pipe[3] = 3;
 393                 } else {
 394                         swizzle_pipe[0] = 0;
 395                         swizzle_pipe[1] = 2;
 396                         swizzle_pipe[2] = 3;
 397                         swizzle_pipe[3] = 1;
 398                 }
 399                 break;
 400         case 5:
 401                 if (force_no_swizzle) {
 402                         swizzle_pipe[0] = 0;
 403                         swizzle_pipe[1] = 1;
 404                         swizzle_pipe[2] = 2;
 405                         swizzle_pipe[3] = 3;
 406                         swizzle_pipe[4] = 4;
 407                 } else {
 408                         swizzle_pipe[0] = 0;
 409                         swizzle_pipe[1] = 2;
 410                         swizzle_pipe[2] = 4;
 411                         swizzle_pipe[3] = 1;
 412                         swizzle_pipe[4] = 3;
 413                 }
 414                 break;
 415         case 6:
 416                 if (force_no_swizzle) {
 417                         swizzle_pipe[0] = 0;
 418                         swizzle_pipe[1] = 1;
 419                         swizzle_pipe[2] = 2;
 420                         swizzle_pipe[3] = 3;
 421                         swizzle_pipe[4] = 4;
 422                         swizzle_pipe[5] = 5;
 423                 } else {
 424                         swizzle_pipe[0] = 0;
 425                         swizzle_pipe[1] = 2;
 426                         swizzle_pipe[2] = 4;
 427                         swizzle_pipe[3] = 5;
 428                         swizzle_pipe[4] = 3;
 429                         swizzle_pipe[5] = 1;
 430                 }
 431                 break;
 432         case 7:
 433                 if (force_no_swizzle) {
 434                         swizzle_pipe[0] = 0;
 435                         swizzle_pipe[1] = 1;
 436                         swizzle_pipe[2] = 2;
 437                         swizzle_pipe[3] = 3;
 438                         swizzle_pipe[4] = 4;
 439                         swizzle_pipe[5] = 5;
 440                         swizzle_pipe[6] = 6;
 441                 } else {
 442                         swizzle_pipe[0] = 0;
 443                         swizzle_pipe[1] = 2;
 444                         swizzle_pipe[2] = 4;
 445                         swizzle_pipe[3] = 6;
 446                         swizzle_pipe[4] = 3;
 447                         swizzle_pipe[5] = 1;
 448                         swizzle_pipe[6] = 5;
 449                 }
 450                 break;
 451         case 8:
 452                 if (force_no_swizzle) {
 453                         swizzle_pipe[0] = 0;
 454                         swizzle_pipe[1] = 1;
 455                         swizzle_pipe[2] = 2;
 456                         swizzle_pipe[3] = 3;
 457                         swizzle_pipe[4] = 4;
 458                         swizzle_pipe[5] = 5;
 459                         swizzle_pipe[6] = 6;
 460                         swizzle_pipe[7] = 7;
 461                 } else {
 462                         swizzle_pipe[0] = 0;
 463                         swizzle_pipe[1] = 2;
 464                         swizzle_pipe[2] = 4;
 465                         swizzle_pipe[3] = 6;
 466                         swizzle_pipe[4] = 3;
 467                         swizzle_pipe[5] = 1;
 468                         swizzle_pipe[6] = 7;
 469                         swizzle_pipe[7] = 5;
 470                 }
 471                 break;
 472         }
 473
 474         cur_backend = 0;
 475         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 476                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 477                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 478
 479                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 480
 481                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 482         }
 483
 484         return backend_map;
 485 }
 486
 487 static void rv770_gpu_init(struct radeon_device *rdev)
 488 {
 489         int i, j, num_qd_pipes;
 490         u32 ta_aux_cntl;
 491         u32 sx_debug_1;
 492         u32 smx_dc_ctl0;
 493         u32 db_debug3;
 494         u32 num_gs_verts_per_thread;
 495         u32 vgt_gs_per_es;
 496         u32 gs_prim_buffer_depth = 0;
 497         u32 sq_ms_fifo_sizes;
 498         u32 sq_config;
 499         u32 sq_thread_resource_mgmt;
 500         u32 hdp_host_path_cntl;
 501         u32 sq_dyn_gpr_size_simd_ab_0;
 502         u32 backend_map;
 503         u32 gb_tiling_config = 0;
 504         u32 cc_rb_backend_disable = 0;
 505         u32 cc_gc_shader_pipe_config = 0;
 506         u32 mc_arb_ramcfg;
 507         u32 db_debug4;
 508
 509         /* setup chip specs */
 510         switch (rdev->family) {
 511         case CHIP_RV770:
 512                 rdev->config.rv770.max_pipes = 4;
 513                 rdev->config.rv770.max_tile_pipes = 8;
 514                 rdev->config.rv770.max_simds = 10;
 515                 rdev->config.rv770.max_backends = 4;
 516                 rdev->config.rv770.max_gprs = 256;
 517                 rdev->config.rv770.max_threads = 248;
 518                 rdev->config.rv770.max_stack_entries = 512;
 519                 rdev->config.rv770.max_hw_contexts = 8;
 520                 rdev->config.rv770.max_gs_threads = 16 * 2;
 521                 rdev->config.rv770.sx_max_export_size = 128;
 522                 rdev->config.rv770.sx_max_export_pos_size = 16;
 523                 rdev->config.rv770.sx_max_export_smx_size = 112;
 524                 rdev->config.rv770.sq_num_cf_insts = 2;
 525
 526                 rdev->config.rv770.sx_num_of_sets = 7;
 527                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 528                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 529                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 530                 break;
 531         case CHIP_RV730:
 532                 rdev->config.rv770.max_pipes = 2;
 533                 rdev->config.rv770.max_tile_pipes = 4;
 534                 rdev->config.rv770.max_simds = 8;
 535                 rdev->config.rv770.max_backends = 2;
 536                 rdev->config.rv770.max_gprs = 128;
 537                 rdev->config.rv770.max_threads = 248;
 538                 rdev->config.rv770.max_stack_entries = 256;
 539                 rdev->config.rv770.max_hw_contexts = 8;
 540                 rdev->config.rv770.max_gs_threads = 16 * 2;
 541                 rdev->config.rv770.sx_max_export_size = 256;
 542                 rdev->config.rv770.sx_max_export_pos_size = 32;
 543                 rdev->config.rv770.sx_max_export_smx_size = 224;
 544                 rdev->config.rv770.sq_num_cf_insts = 2;
 545
 546                 rdev->config.rv770.sx_num_of_sets = 7;
 547                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 548                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 549                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 550                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 551                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 552                         rdev->config.rv770.sx_max_export_smx_size += 16;
 553                 }
 554                 break;
 555         case CHIP_RV710:
 556                 rdev->config.rv770.max_pipes = 2;
 557                 rdev->config.rv770.max_tile_pipes = 2;
 558                 rdev->config.rv770.max_simds = 2;
 559                 rdev->config.rv770.max_backends = 1;
 560                 rdev->config.rv770.max_gprs = 256;
 561                 rdev->config.rv770.max_threads = 192;
 562                 rdev->config.rv770.max_stack_entries = 256;
 563                 rdev->config.rv770.max_hw_contexts = 4;
 564                 rdev->config.rv770.max_gs_threads = 8 * 2;
 565                 rdev->config.rv770.sx_max_export_size = 128;
 566                 rdev->config.rv770.sx_max_export_pos_size = 16;
 567                 rdev->config.rv770.sx_max_export_smx_size = 112;
 568                 rdev->config.rv770.sq_num_cf_insts = 1;
 569
 570                 rdev->config.rv770.sx_num_of_sets = 7;
 571                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 572                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 573                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 574                 break;
 575         case CHIP_RV740:
 576                 rdev->config.rv770.max_pipes = 4;
 577                 rdev->config.rv770.max_tile_pipes = 4;
 578                 rdev->config.rv770.max_simds = 8;
 579                 rdev->config.rv770.max_backends = 4;
 580                 rdev->config.rv770.max_gprs = 256;
 581                 rdev->config.rv770.max_threads = 248;
 582                 rdev->config.rv770.max_stack_entries = 512;
 583                 rdev->config.rv770.max_hw_contexts = 8;
 584                 rdev->config.rv770.max_gs_threads = 16 * 2;
 585                 rdev->config.rv770.sx_max_export_size = 256;
 586                 rdev->config.rv770.sx_max_export_pos_size = 32;
 587                 rdev->config.rv770.sx_max_export_smx_size = 224;
 588                 rdev->config.rv770.sq_num_cf_insts = 2;
 589
 590                 rdev->config.rv770.sx_num_of_sets = 7;
 591                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 592                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 593                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 594
 595                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 596                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 597                         rdev->config.rv770.sx_max_export_smx_size += 16;
 598                 }
 599                 break;
 600         default:
 601                 break;
 602         }
 603
 604         /* Initialize HDP */
 605         j = 0;
 606         for (i = 0; i < 32; i++) {
 607                 WREG32((0x2c14 + j), 0x00000000);
 608                 WREG32((0x2c18 + j), 0x00000000);
 609                 WREG32((0x2c1c + j), 0x00000000);
 610                 WREG32((0x2c20 + j), 0x00000000);
 611                 WREG32((0x2c24 + j), 0x00000000);
 612                 j += 0x18;
 613         }
 614
 615         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 616
 617         /* setup tiling, simd, pipe config */
 618         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 619
 620         switch (rdev->config.rv770.max_tile_pipes) {
 621         case 1:
 622         default:
 623                 gb_tiling_config |= PIPE_TILING(0);
 624                 break;
 625         case 2:
 626                 gb_tiling_config |= PIPE_TILING(1);
 627                 break;
 628         case 4:
 629                 gb_tiling_config |= PIPE_TILING(2);
 630                 break;
 631         case 8:
 632                 gb_tiling_config |= PIPE_TILING(3);
 633                 break;
 634         }
 635         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 636
 637         if (rdev->family == CHIP_RV770)
 638                 gb_tiling_config |= BANK_TILING(1);
 639         else
 640                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 641         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 642
 643         gb_tiling_config |= GROUP_SIZE(0);
 644         rdev->config.rv770.tiling_group_size = 256;
 645
 646         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 647                 gb_tiling_config |= ROW_TILING(3);
 648                 gb_tiling_config |= SAMPLE_SPLIT(3);
 649         } else {
 650                 gb_tiling_config |=
 651                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 652                 gb_tiling_config |=
 653                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 654         }
 655
 656         gb_tiling_config |= BANK_SWAPS(1);
 657
 658         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 659         cc_rb_backend_disable |=
 660                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 661
 662         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 663         cc_gc_shader_pipe_config |=
 664                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 665         cc_gc_shader_pipe_config |=
 666                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 667
 668         if (rdev->family == CHIP_RV740)
 669                 backend_map = 0x28;
 670         else
 671                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 672                                                                 rdev->config.rv770.max_tile_pipes,
 673                                                                 (R7XX_MAX_BACKENDS -
 674                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 675                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 676                                                                 (cc_rb_backend_disable >> 16));
 677         gb_tiling_config |= BACKEND_MAP(backend_map);
 678
 679
 680         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 681         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 682         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 683
 684         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 685         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 686         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 687         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 688
 689         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 690         WREG32(CGTS_TCC_DISABLE, 0);
 691         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 692         WREG32(CGTS_USER_TCC_DISABLE, 0);
 693
 694         num_qd_pipes =
 695                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 696         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 697         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 698
 699         /* set HW defaults for 3D engine */
 700         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 701                                      ROQ_IB2_START(0x2b)));
 702
 703         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 704
 705         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 706         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 707
 708         sx_debug_1 = RREG32(SX_DEBUG_1);
 709         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 710         WREG32(SX_DEBUG_1, sx_debug_1);
 711
 712         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 713         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 714         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 715         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 716
 717         if (rdev->family != CHIP_RV740)
 718                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 719                                        GS_FLUSH_CTL(4) |
 720                                        ACK_FLUSH_CTL(3) |
 721                                        SYNC_FLUSH_CTL));
 722
 723         db_debug3 = RREG32(DB_DEBUG3);
 724         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 725         switch (rdev->family) {
 726         case CHIP_RV770:
 727         case CHIP_RV740:
 728                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 729                 break;
 730         case CHIP_RV710:
 731         case CHIP_RV730:
 732         default:
 733                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 734                 break;
 735         }
 736         WREG32(DB_DEBUG3, db_debug3);
 737
 738         if (rdev->family != CHIP_RV770) {
 739                 db_debug4 = RREG32(DB_DEBUG4);
 740                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 741                 WREG32(DB_DEBUG4, db_debug4);
 742         }
 743
 744         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 745                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 746                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 747
 748         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 749                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 750                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 751
 752         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 753
 754         WREG32(VGT_NUM_INSTANCES, 1);
 755
 756         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 757
 758         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 759
 760         WREG32(CP_PERFMON_CNTL, 0);
 761
 762         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 763                             DONE_FIFO_HIWATER(0xe0) |
 764                             ALU_UPDATE_FIFO_HIWATER(0x8));
 765         switch (rdev->family) {
 766         case CHIP_RV770:
 767         case CHIP_RV730:
 768         case CHIP_RV710:
 769                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 770                 break;
 771         case CHIP_RV740:
 772         default:
 773                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 774                 break;
 775         }
 776         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 777
 778         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 779          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 780          */
 781         sq_config = RREG32(SQ_CONFIG);
 782         sq_config &= ~(PS_PRIO(3) |
 783                        VS_PRIO(3) |
 784                        GS_PRIO(3) |
 785                        ES_PRIO(3));
 786         sq_config |= (DX9_CONSTS |
 787                       VC_ENABLE |
 788                       EXPORT_SRC_C |
 789                       PS_PRIO(0) |
 790                       VS_PRIO(1) |
 791                       GS_PRIO(2) |
 792                       ES_PRIO(3));
 793         if (rdev->family == CHIP_RV710)
 794                 /* no vertex cache */
 795                 sq_config &= ~VC_ENABLE;
 796
 797         WREG32(SQ_CONFIG, sq_config);
 798
 799         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 800                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 801                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 802
 803         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 804                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 805
 806         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 807                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 808                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 809         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 810                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 811         else
 812                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 813         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 814
 815         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 816                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 817
 818         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 819                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 820
 821         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 822                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 823                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 824                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 825
 826         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 827         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 828         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 829         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 830         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 831         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 832         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 833         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 834
 835         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 836                                           FORCE_EOV_MAX_REZ_CNT(255)));
 837
 838         if (rdev->family == CHIP_RV710)
 839                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 840                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 841         else
 842                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 843                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 844
 845         switch (rdev->family) {
 846         case CHIP_RV770:
 847         case CHIP_RV730:
 848         case CHIP_RV740:
 849                 gs_prim_buffer_depth = 384;
 850                 break;
 851         case CHIP_RV710:
 852                 gs_prim_buffer_depth = 128;
 853                 break;
 854         default:
 855                 break;
 856         }
 857
 858         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 859         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 860         /* Max value for this is 256 */
 861         if (vgt_gs_per_es > 256)
 862                 vgt_gs_per_es = 256;
 863
 864         WREG32(VGT_ES_PER_GS, 128);
 865         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 866         WREG32(VGT_GS_PER_VS, 2);
 867
 868         /* more default values. 2D/3D driver should adjust as needed */
 869         WREG32(VGT_GS_VERTEX_REUSE, 16);
 870         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 871         WREG32(VGT_STRMOUT_EN, 0);
 872         WREG32(SX_MISC, 0);
 873         WREG32(PA_SC_MODE_CNTL, 0);
 874         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 875         WREG32(PA_SC_AA_CONFIG, 0);
 876         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 877         WREG32(PA_SC_LINE_STIPPLE, 0);
 878         WREG32(SPI_INPUT_Z, 0);
 879         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 880         WREG32(CB_COLOR7_FRAG, 0);
 881
 882         /* clear render buffer base addresses */
 883         WREG32(CB_COLOR0_BASE, 0);
 884         WREG32(CB_COLOR1_BASE, 0);
 885         WREG32(CB_COLOR2_BASE, 0);
 886         WREG32(CB_COLOR3_BASE, 0);
 887         WREG32(CB_COLOR4_BASE, 0);
 888         WREG32(CB_COLOR5_BASE, 0);
 889         WREG32(CB_COLOR6_BASE, 0);
 890         WREG32(CB_COLOR7_BASE, 0);
 891
 892         WREG32(TCP_CNTL, 0);
 893
 894         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 895         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 896
 897         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 898
 899         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 900                                           NUM_CLIP_SEQ(3)));
 901
 902 }
 903
 904 int rv770_mc_init(struct radeon_device *rdev)
 905 {
 906         u32 tmp;
 907         int chansize, numchan;
 908
 909         /* Get VRAM informations */
 910         rdev->mc.vram_is_ddr = true;
 911         tmp = RREG32(MC_ARB_RAMCFG);
 912         if (tmp & CHANSIZE_OVERRIDE) {
 913                 chansize = 16;
 914         } else if (tmp & CHANSIZE_MASK) {
 915                 chansize = 64;
 916         } else {
 917                 chansize = 32;
 918         }
 919         tmp = RREG32(MC_SHARED_CHMAP);
 920         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 921         case 0:
 922         default:
 923                 numchan = 1;
 924                 break;
 925         case 1:
 926                 numchan = 2;
 927                 break;
 928         case 2:
 929                 numchan = 4;
 930                 break;
 931         case 3:
 932                 numchan = 8;
 933                 break;
 934         }
 935         rdev->mc.vram_width = numchan * chansize;
 936         /* Could aper size report 0 ? */
 937         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 938         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 939         /* Setup GPU memory space */
 940         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 941         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 942         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 943         r600_vram_gtt_location(rdev, &rdev->mc);
 944         radeon_update_bandwidth_info(rdev);
 945
 946         return 0;
 947 }
 948
 949 static int rv770_startup(struct radeon_device *rdev)
 950 {
 951         int r;
 952
 953         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
 954                 r = r600_init_microcode(rdev);
 955                 if (r) {
 956                         DRM_ERROR("Failed to load firmware!\n");
 957                         return r;
 958                 }
 959         }
 960
 961         rv770_mc_program(rdev);
 962         if (rdev->flags & RADEON_IS_AGP) {
 963                 rv770_agp_enable(rdev);
 964         } else {
 965                 r = rv770_pcie_gart_enable(rdev);
 966                 if (r)
 967                         return r;
 968         }
 969         rv770_gpu_init(rdev);
 970         r = r600_blit_init(rdev);
 971         if (r) {
 972                 r600_blit_fini(rdev);
 973                 rdev->asic->copy = NULL;
 974                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
 975         }
 976         /* pin copy shader into vram */
 977         if (rdev->r600_blit.shader_obj) {
 978                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 979                 if (unlikely(r != 0))
 980                         return r;
 981                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 982                                 &rdev->r600_blit.shader_gpu_addr);
 983                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 984                 if (r) {
 985                         DRM_ERROR("failed to pin blit object %d\n", r);
 986                         return r;
 987                 }
 988         }
 989         /* Enable IRQ */
 990         r = r600_irq_init(rdev);
 991         if (r) {
 992                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
 993                 radeon_irq_kms_fini(rdev);
 994                 return r;
 995         }
 996         r600_irq_set(rdev);
 997
 998         r = radeon_ring_init(rdev, rdev->cp.ring_size);
 999         if (r)
1000                 return r;
1001         r = rv770_cp_load_microcode(rdev);
1002         if (r)
1003                 return r;
1004         r = r600_cp_resume(rdev);
1005         if (r)
1006                 return r;
1007         /* write back buffer are not vital so don't worry about failure */
1008         r600_wb_enable(rdev);
1009         return 0;
1010 }
1011
1012 int rv770_resume(struct radeon_device *rdev)
1013 {
1014         int r;
1015
1016         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1017          * posting will perform necessary task to bring back GPU into good
1018          * shape.
1019          */
1020         /* post card */
1021         atom_asic_init(rdev->mode_info.atom_context);
1022         /* Initialize clocks */
1023         r = radeon_clocks_init(rdev);
1024         if (r) {
1025                 return r;
1026         }
1027
1028         r = rv770_startup(rdev);
1029         if (r) {
1030                 DRM_ERROR("r600 startup failed on resume\n");
1031                 return r;
1032         }
1033
1034         r = r600_ib_test(rdev);
1035         if (r) {
1036                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1037                 return r;
1038         }
1039
1040         r = r600_audio_init(rdev);
1041         if (r) {
1042                 dev_err(rdev->dev, "radeon: audio init failed\n");
1043                 return r;
1044         }
1045
1046         return r;
1047
1048 }
1049
1050 int rv770_suspend(struct radeon_device *rdev)
1051 {
1052         int r;
1053
1054         r600_audio_fini(rdev);
1055         /* FIXME: we should wait for ring to be empty */
1056         r700_cp_stop(rdev);
1057         rdev->cp.ready = false;
1058         r600_irq_suspend(rdev);
1059         r600_wb_disable(rdev);
1060         rv770_pcie_gart_disable(rdev);
1061         /* unpin shaders bo */
1062         if (rdev->r600_blit.shader_obj) {
1063                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1064                 if (likely(r == 0)) {
1065                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1066                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1067                 }
1068         }
1069         return 0;
1070 }
1071
1072 /* Plan is to move initialization in that function and use
1073  * helper function so that radeon_device_init pretty much
1074  * do nothing more than calling asic specific function. This
1075  * should also allow to remove a bunch of callback function
1076  * like vram_info.
1077  */
1078 int rv770_init(struct radeon_device *rdev)
1079 {
1080         int r;
1081
1082         r = radeon_dummy_page_init(rdev);
1083         if (r)
1084                 return r;
1085         /* This don't do much */
1086         r = radeon_gem_init(rdev);
1087         if (r)
1088                 return r;
1089         /* Read BIOS */
1090         if (!radeon_get_bios(rdev)) {
1091                 if (ASIC_IS_AVIVO(rdev))
1092                         return -EINVAL;
1093         }
1094         /* Must be an ATOMBIOS */
1095         if (!rdev->is_atom_bios) {
1096                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1097                 return -EINVAL;
1098         }
1099         r = radeon_atombios_init(rdev);
1100         if (r)
1101                 return r;
1102         /* Post card if necessary */
1103         if (!r600_card_posted(rdev)) {
1104                 if (!rdev->bios) {
1105                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1106                         return -EINVAL;
1107                 }
1108                 DRM_INFO("GPU not posted. posting now...\n");
1109                 atom_asic_init(rdev->mode_info.atom_context);
1110         }
1111         /* Initialize scratch registers */
1112         r600_scratch_init(rdev);
1113         /* Initialize surface registers */
1114         radeon_surface_init(rdev);
1115         /* Initialize clocks */
1116         radeon_get_clock_info(rdev->ddev);
1117         r = radeon_clocks_init(rdev);
1118         if (r)
1119                 return r;
1120         /* Fence driver */
1121         r = radeon_fence_driver_init(rdev);
1122         if (r)
1123                 return r;
1124         /* initialize AGP */
1125         if (rdev->flags & RADEON_IS_AGP) {
1126                 r = radeon_agp_init(rdev);
1127                 if (r)
1128                         radeon_agp_disable(rdev);
1129         }
1130         r = rv770_mc_init(rdev);
1131         if (r)
1132                 return r;
1133         /* Memory manager */
1134         r = radeon_bo_init(rdev);
1135         if (r)
1136                 return r;
1137
1138         r = radeon_irq_kms_init(rdev);
1139         if (r)
1140                 return r;
1141
1142         rdev->cp.ring_obj = NULL;
1143         r600_ring_init(rdev, 1024 * 1024);
1144
1145         rdev->ih.ring_obj = NULL;
1146         r600_ih_ring_init(rdev, 64 * 1024);
1147
1148         r = r600_pcie_gart_init(rdev);
1149         if (r)
1150                 return r;
1151
1152         rdev->accel_working = true;
1153         r = rv770_startup(rdev);
1154         if (r) {
1155                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1156                 r700_cp_fini(rdev);
1157                 r600_wb_fini(rdev);
1158                 r600_irq_fini(rdev);
1159                 radeon_irq_kms_fini(rdev);
1160                 rv770_pcie_gart_fini(rdev);
1161                 rdev->accel_working = false;
1162         }
1163         if (rdev->accel_working) {
1164                 r = radeon_ib_pool_init(rdev);
1165                 if (r) {
1166                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1167                         rdev->accel_working = false;
1168                 } else {
1169                         r = r600_ib_test(rdev);
1170                         if (r) {
1171                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1172                                 rdev->accel_working = false;
1173                         }
1174                 }
1175         }
1176
1177         r = r600_audio_init(rdev);
1178         if (r) {
1179                 dev_err(rdev->dev, "radeon: audio init failed\n");
1180                 return r;
1181         }
1182
1183         return 0;
1184 }
1185
1186 void rv770_fini(struct radeon_device *rdev)
1187 {
1188         r600_blit_fini(rdev);
1189         r700_cp_fini(rdev);
1190         r600_wb_fini(rdev);
1191         r600_irq_fini(rdev);
1192         radeon_irq_kms_fini(rdev);
1193         rv770_pcie_gart_fini(rdev);
1194         radeon_gem_fini(rdev);
1195         radeon_fence_driver_fini(rdev);
1196         radeon_clocks_fini(rdev);
1197         radeon_agp_fini(rdev);
1198         radeon_bo_fini(rdev);
1199         radeon_atombios_fini(rdev);
1200         kfree(rdev->bios);
1201         rdev->bios = NULL;
1202         radeon_dummy_page_fini(rdev);
1203 }