drivers/gpu/drm/radeon/si.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "sid.h"
  33 #include "atom.h"
  34 #include "si_blit_shaders.h"
  35
  36 #define SI_PFP_UCODE_SIZE 2144
  37 #define SI_PM4_UCODE_SIZE 2144
  38 #define SI_CE_UCODE_SIZE 2144
  39 #define SI_RLC_UCODE_SIZE 2048
  40 #define SI_MC_UCODE_SIZE 7769
  41
  42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
  43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
  44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
  45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
  46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
  47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
  48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
  49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
  50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
  51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
  52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
  53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
  54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
  55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
  56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
  57
  58 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  59 extern void r600_ih_ring_fini(struct radeon_device *rdev);
  60 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  61 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  62 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  63 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
  64
  65 /* get temperature in millidegrees */
  66 int si_get_temp(struct radeon_device *rdev)
  67 {
  68         u32 temp;
  69         int actual_temp = 0;
  70
  71         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  72                 CTF_TEMP_SHIFT;
  73
  74         if (temp & 0x200)
  75                 actual_temp = 255;
  76         else
  77                 actual_temp = temp & 0x1ff;
  78
  79         actual_temp = (actual_temp * 1000);
  80
  81         return actual_temp;
  82 }
  83
  84 #define TAHITI_IO_MC_REGS_SIZE 36
  85
  86 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  87         {0x0000006f, 0x03044000},
  88         {0x00000070, 0x0480c018},
  89         {0x00000071, 0x00000040},
  90         {0x00000072, 0x01000000},
  91         {0x00000074, 0x000000ff},
  92         {0x00000075, 0x00143400},
  93         {0x00000076, 0x08ec0800},
  94         {0x00000077, 0x040000cc},
  95         {0x00000079, 0x00000000},
  96         {0x0000007a, 0x21000409},
  97         {0x0000007c, 0x00000000},
  98         {0x0000007d, 0xe8000000},
  99         {0x0000007e, 0x044408a8},
 100         {0x0000007f, 0x00000003},
 101         {0x00000080, 0x00000000},
 102         {0x00000081, 0x01000000},
 103         {0x00000082, 0x02000000},
 104         {0x00000083, 0x00000000},
 105         {0x00000084, 0xe3f3e4f4},
 106         {0x00000085, 0x00052024},
 107         {0x00000087, 0x00000000},
 108         {0x00000088, 0x66036603},
 109         {0x00000089, 0x01000000},
 110         {0x0000008b, 0x1c0a0000},
 111         {0x0000008c, 0xff010000},
 112         {0x0000008e, 0xffffefff},
 113         {0x0000008f, 0xfff3efff},
 114         {0x00000090, 0xfff3efbf},
 115         {0x00000094, 0x00101101},
 116         {0x00000095, 0x00000fff},
 117         {0x00000096, 0x00116fff},
 118         {0x00000097, 0x60010000},
 119         {0x00000098, 0x10010000},
 120         {0x00000099, 0x00006000},
 121         {0x0000009a, 0x00001000},
 122         {0x0000009f, 0x00a77400}
 123 };
 124
 125 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 126         {0x0000006f, 0x03044000},
 127         {0x00000070, 0x0480c018},
 128         {0x00000071, 0x00000040},
 129         {0x00000072, 0x01000000},
 130         {0x00000074, 0x000000ff},
 131         {0x00000075, 0x00143400},
 132         {0x00000076, 0x08ec0800},
 133         {0x00000077, 0x040000cc},
 134         {0x00000079, 0x00000000},
 135         {0x0000007a, 0x21000409},
 136         {0x0000007c, 0x00000000},
 137         {0x0000007d, 0xe8000000},
 138         {0x0000007e, 0x044408a8},
 139         {0x0000007f, 0x00000003},
 140         {0x00000080, 0x00000000},
 141         {0x00000081, 0x01000000},
 142         {0x00000082, 0x02000000},
 143         {0x00000083, 0x00000000},
 144         {0x00000084, 0xe3f3e4f4},
 145         {0x00000085, 0x00052024},
 146         {0x00000087, 0x00000000},
 147         {0x00000088, 0x66036603},
 148         {0x00000089, 0x01000000},
 149         {0x0000008b, 0x1c0a0000},
 150         {0x0000008c, 0xff010000},
 151         {0x0000008e, 0xffffefff},
 152         {0x0000008f, 0xfff3efff},
 153         {0x00000090, 0xfff3efbf},
 154         {0x00000094, 0x00101101},
 155         {0x00000095, 0x00000fff},
 156         {0x00000096, 0x00116fff},
 157         {0x00000097, 0x60010000},
 158         {0x00000098, 0x10010000},
 159         {0x00000099, 0x00006000},
 160         {0x0000009a, 0x00001000},
 161         {0x0000009f, 0x00a47400}
 162 };
 163
 164 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 165         {0x0000006f, 0x03044000},
 166         {0x00000070, 0x0480c018},
 167         {0x00000071, 0x00000040},
 168         {0x00000072, 0x01000000},
 169         {0x00000074, 0x000000ff},
 170         {0x00000075, 0x00143400},
 171         {0x00000076, 0x08ec0800},
 172         {0x00000077, 0x040000cc},
 173         {0x00000079, 0x00000000},
 174         {0x0000007a, 0x21000409},
 175         {0x0000007c, 0x00000000},
 176         {0x0000007d, 0xe8000000},
 177         {0x0000007e, 0x044408a8},
 178         {0x0000007f, 0x00000003},
 179         {0x00000080, 0x00000000},
 180         {0x00000081, 0x01000000},
 181         {0x00000082, 0x02000000},
 182         {0x00000083, 0x00000000},
 183         {0x00000084, 0xe3f3e4f4},
 184         {0x00000085, 0x00052024},
 185         {0x00000087, 0x00000000},
 186         {0x00000088, 0x66036603},
 187         {0x00000089, 0x01000000},
 188         {0x0000008b, 0x1c0a0000},
 189         {0x0000008c, 0xff010000},
 190         {0x0000008e, 0xffffefff},
 191         {0x0000008f, 0xfff3efff},
 192         {0x00000090, 0xfff3efbf},
 193         {0x00000094, 0x00101101},
 194         {0x00000095, 0x00000fff},
 195         {0x00000096, 0x00116fff},
 196         {0x00000097, 0x60010000},
 197         {0x00000098, 0x10010000},
 198         {0x00000099, 0x00006000},
 199         {0x0000009a, 0x00001000},
 200         {0x0000009f, 0x00a37400}
 201 };
 202
 203 /* ucode loading */
 204 static int si_mc_load_microcode(struct radeon_device *rdev)
 205 {
 206         const __be32 *fw_data;
 207         u32 running, blackout = 0;
 208         u32 *io_mc_regs;
 209         int i, ucode_size, regs_size;
 210
 211         if (!rdev->mc_fw)
 212                 return -EINVAL;
 213
 214         switch (rdev->family) {
 215         case CHIP_TAHITI:
 216                 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
 217                 ucode_size = SI_MC_UCODE_SIZE;
 218                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 219                 break;
 220         case CHIP_PITCAIRN:
 221                 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
 222                 ucode_size = SI_MC_UCODE_SIZE;
 223                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 224                 break;
 225         case CHIP_VERDE:
 226         default:
 227                 io_mc_regs = (u32 *)&verde_io_mc_regs;
 228                 ucode_size = SI_MC_UCODE_SIZE;
 229                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 230                 break;
 231         }
 232
 233         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 234
 235         if (running == 0) {
 236                 if (running) {
 237                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 238                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 239                 }
 240
 241                 /* reset the engine and set to writable */
 242                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 243                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 244
 245                 /* load mc io regs */
 246                 for (i = 0; i < regs_size; i++) {
 247                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 248                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 249                 }
 250                 /* load the MC ucode */
 251                 fw_data = (const __be32 *)rdev->mc_fw->data;
 252                 for (i = 0; i < ucode_size; i++)
 253                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 254
 255                 /* put the engine back into the active state */
 256                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 257                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 258                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 259
 260                 /* wait for training to complete */
 261                 for (i = 0; i < rdev->usec_timeout; i++) {
 262                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
 263                                 break;
 264                         udelay(1);
 265                 }
 266                 for (i = 0; i < rdev->usec_timeout; i++) {
 267                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
 268                                 break;
 269                         udelay(1);
 270                 }
 271
 272                 if (running)
 273                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 274         }
 275
 276         return 0;
 277 }
 278
 279 static int si_init_microcode(struct radeon_device *rdev)
 280 {
 281         struct platform_device *pdev;
 282         const char *chip_name;
 283         const char *rlc_chip_name;
 284         size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
 285         char fw_name[30];
 286         int err;
 287
 288         DRM_DEBUG("\n");
 289
 290         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 291         err = IS_ERR(pdev);
 292         if (err) {
 293                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 294                 return -EINVAL;
 295         }
 296
 297         switch (rdev->family) {
 298         case CHIP_TAHITI:
 299                 chip_name = "TAHITI";
 300                 rlc_chip_name = "TAHITI";
 301                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 302                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 303                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 304                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 305                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 306                 break;
 307         case CHIP_PITCAIRN:
 308                 chip_name = "PITCAIRN";
 309                 rlc_chip_name = "PITCAIRN";
 310                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 311                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 312                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 313                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 314                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 315                 break;
 316         case CHIP_VERDE:
 317                 chip_name = "VERDE";
 318                 rlc_chip_name = "VERDE";
 319                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 320                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 321                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 322                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 323                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 324                 break;
 325         default: BUG();
 326         }
 327
 328         DRM_INFO("Loading %s Microcode\n", chip_name);
 329
 330         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 331         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 332         if (err)
 333                 goto out;
 334         if (rdev->pfp_fw->size != pfp_req_size) {
 335                 printk(KERN_ERR
 336                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 337                        rdev->pfp_fw->size, fw_name);
 338                 err = -EINVAL;
 339                 goto out;
 340         }
 341
 342         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 343         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 344         if (err)
 345                 goto out;
 346         if (rdev->me_fw->size != me_req_size) {
 347                 printk(KERN_ERR
 348                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 349                        rdev->me_fw->size, fw_name);
 350                 err = -EINVAL;
 351         }
 352
 353         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 354         err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
 355         if (err)
 356                 goto out;
 357         if (rdev->ce_fw->size != ce_req_size) {
 358                 printk(KERN_ERR
 359                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 360                        rdev->ce_fw->size, fw_name);
 361                 err = -EINVAL;
 362         }
 363
 364         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 365         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 366         if (err)
 367                 goto out;
 368         if (rdev->rlc_fw->size != rlc_req_size) {
 369                 printk(KERN_ERR
 370                        "si_rlc: Bogus length %zu in firmware \"%s\"\n",
 371                        rdev->rlc_fw->size, fw_name);
 372                 err = -EINVAL;
 373         }
 374
 375         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 376         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 377         if (err)
 378                 goto out;
 379         if (rdev->mc_fw->size != mc_req_size) {
 380                 printk(KERN_ERR
 381                        "si_mc: Bogus length %zu in firmware \"%s\"\n",
 382                        rdev->mc_fw->size, fw_name);
 383                 err = -EINVAL;
 384         }
 385
 386 out:
 387         platform_device_unregister(pdev);
 388
 389         if (err) {
 390                 if (err != -EINVAL)
 391                         printk(KERN_ERR
 392                                "si_cp: Failed to load firmware \"%s\"\n",
 393                                fw_name);
 394                 release_firmware(rdev->pfp_fw);
 395                 rdev->pfp_fw = NULL;
 396                 release_firmware(rdev->me_fw);
 397                 rdev->me_fw = NULL;
 398                 release_firmware(rdev->ce_fw);
 399                 rdev->ce_fw = NULL;
 400                 release_firmware(rdev->rlc_fw);
 401                 rdev->rlc_fw = NULL;
 402                 release_firmware(rdev->mc_fw);
 403                 rdev->mc_fw = NULL;
 404         }
 405         return err;
 406 }
 407
 408 /* watermark setup */
 409 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
 410                                    struct radeon_crtc *radeon_crtc,
 411                                    struct drm_display_mode *mode,
 412                                    struct drm_display_mode *other_mode)
 413 {
 414         u32 tmp;
 415         /*
 416          * Line Buffer Setup
 417          * There are 3 line buffers, each one shared by 2 display controllers.
 418          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 419          * the display controllers.  The paritioning is done via one of four
 420          * preset allocations specified in bits 21:20:
 421          *  0 - half lb
 422          *  2 - whole lb, other crtc must be disabled
 423          */
 424         /* this can get tricky if we have two large displays on a paired group
 425          * of crtcs.  Ideally for multiple large displays we'd assign them to
 426          * non-linked crtcs for maximum line buffer allocation.
 427          */
 428         if (radeon_crtc->base.enabled && mode) {
 429                 if (other_mode)
 430                         tmp = 0; /* 1/2 */
 431                 else
 432                         tmp = 2; /* whole */
 433         } else
 434                 tmp = 0;
 435
 436         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
 437                DC_LB_MEMORY_CONFIG(tmp));
 438
 439         if (radeon_crtc->base.enabled && mode) {
 440                 switch (tmp) {
 441                 case 0:
 442                 default:
 443                         return 4096 * 2;
 444                 case 2:
 445                         return 8192 * 2;
 446                 }
 447         }
 448
 449         /* controller not enabled, so no lb used */
 450         return 0;
 451 }
 452
 453 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
 454 {
 455         u32 tmp = RREG32(MC_SHARED_CHMAP);
 456
 457         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 458         case 0:
 459         default:
 460                 return 1;
 461         case 1:
 462                 return 2;
 463         case 2:
 464                 return 4;
 465         case 3:
 466                 return 8;
 467         case 4:
 468                 return 3;
 469         case 5:
 470                 return 6;
 471         case 6:
 472                 return 10;
 473         case 7:
 474                 return 12;
 475         case 8:
 476                 return 16;
 477         }
 478 }
 479
 480 struct dce6_wm_params {
 481         u32 dram_channels; /* number of dram channels */
 482         u32 yclk;          /* bandwidth per dram data pin in kHz */
 483         u32 sclk;          /* engine clock in kHz */
 484         u32 disp_clk;      /* display clock in kHz */
 485         u32 src_width;     /* viewport width */
 486         u32 active_time;   /* active display time in ns */
 487         u32 blank_time;    /* blank time in ns */
 488         bool interlaced;    /* mode is interlaced */
 489         fixed20_12 vsc;    /* vertical scale ratio */
 490         u32 num_heads;     /* number of active crtcs */
 491         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 492         u32 lb_size;       /* line buffer allocated to pipe */
 493         u32 vtaps;         /* vertical scaler taps */
 494 };
 495
 496 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
 497 {
 498         /* Calculate raw DRAM Bandwidth */
 499         fixed20_12 dram_efficiency; /* 0.7 */
 500         fixed20_12 yclk, dram_channels, bandwidth;
 501         fixed20_12 a;
 502
 503         a.full = dfixed_const(1000);
 504         yclk.full = dfixed_const(wm->yclk);
 505         yclk.full = dfixed_div(yclk, a);
 506         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 507         a.full = dfixed_const(10);
 508         dram_efficiency.full = dfixed_const(7);
 509         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 510         bandwidth.full = dfixed_mul(dram_channels, yclk);
 511         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 512
 513         return dfixed_trunc(bandwidth);
 514 }
 515
 516 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 517 {
 518         /* Calculate DRAM Bandwidth and the part allocated to display. */
 519         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 520         fixed20_12 yclk, dram_channels, bandwidth;
 521         fixed20_12 a;
 522
 523         a.full = dfixed_const(1000);
 524         yclk.full = dfixed_const(wm->yclk);
 525         yclk.full = dfixed_div(yclk, a);
 526         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 527         a.full = dfixed_const(10);
 528         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 529         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 530         bandwidth.full = dfixed_mul(dram_channels, yclk);
 531         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 532
 533         return dfixed_trunc(bandwidth);
 534 }
 535
 536 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
 537 {
 538         /* Calculate the display Data return Bandwidth */
 539         fixed20_12 return_efficiency; /* 0.8 */
 540         fixed20_12 sclk, bandwidth;
 541         fixed20_12 a;
 542
 543         a.full = dfixed_const(1000);
 544         sclk.full = dfixed_const(wm->sclk);
 545         sclk.full = dfixed_div(sclk, a);
 546         a.full = dfixed_const(10);
 547         return_efficiency.full = dfixed_const(8);
 548         return_efficiency.full = dfixed_div(return_efficiency, a);
 549         a.full = dfixed_const(32);
 550         bandwidth.full = dfixed_mul(a, sclk);
 551         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 552
 553         return dfixed_trunc(bandwidth);
 554 }
 555
 556 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
 557 {
 558         return 32;
 559 }
 560
 561 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
 562 {
 563         /* Calculate the DMIF Request Bandwidth */
 564         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 565         fixed20_12 disp_clk, sclk, bandwidth;
 566         fixed20_12 a, b1, b2;
 567         u32 min_bandwidth;
 568
 569         a.full = dfixed_const(1000);
 570         disp_clk.full = dfixed_const(wm->disp_clk);
 571         disp_clk.full = dfixed_div(disp_clk, a);
 572         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
 573         b1.full = dfixed_mul(a, disp_clk);
 574
 575         a.full = dfixed_const(1000);
 576         sclk.full = dfixed_const(wm->sclk);
 577         sclk.full = dfixed_div(sclk, a);
 578         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
 579         b2.full = dfixed_mul(a, sclk);
 580
 581         a.full = dfixed_const(10);
 582         disp_clk_request_efficiency.full = dfixed_const(8);
 583         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 584
 585         min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
 586
 587         a.full = dfixed_const(min_bandwidth);
 588         bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
 589
 590         return dfixed_trunc(bandwidth);
 591 }
 592
 593 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
 594 {
 595         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 596         u32 dram_bandwidth = dce6_dram_bandwidth(wm);
 597         u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
 598         u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
 599
 600         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 601 }
 602
 603 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
 604 {
 605         /* Calculate the display mode Average Bandwidth
 606          * DisplayMode should contain the source and destination dimensions,
 607          * timing, etc.
 608          */
 609         fixed20_12 bpp;
 610         fixed20_12 line_time;
 611         fixed20_12 src_width;
 612         fixed20_12 bandwidth;
 613         fixed20_12 a;
 614
 615         a.full = dfixed_const(1000);
 616         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 617         line_time.full = dfixed_div(line_time, a);
 618         bpp.full = dfixed_const(wm->bytes_per_pixel);
 619         src_width.full = dfixed_const(wm->src_width);
 620         bandwidth.full = dfixed_mul(src_width, bpp);
 621         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 622         bandwidth.full = dfixed_div(bandwidth, line_time);
 623
 624         return dfixed_trunc(bandwidth);
 625 }
 626
 627 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
 628 {
 629         /* First calcualte the latency in ns */
 630         u32 mc_latency = 2000; /* 2000 ns. */
 631         u32 available_bandwidth = dce6_available_bandwidth(wm);
 632         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 633         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 634         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 635         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 636                 (wm->num_heads * cursor_line_pair_return_time);
 637         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 638         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 639         u32 tmp, dmif_size = 12288;
 640         fixed20_12 a, b, c;
 641
 642         if (wm->num_heads == 0)
 643                 return 0;
 644
 645         a.full = dfixed_const(2);
 646         b.full = dfixed_const(1);
 647         if ((wm->vsc.full > a.full) ||
 648             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 649             (wm->vtaps >= 5) ||
 650             ((wm->vsc.full >= a.full) && wm->interlaced))
 651                 max_src_lines_per_dst_line = 4;
 652         else
 653                 max_src_lines_per_dst_line = 2;
 654
 655         a.full = dfixed_const(available_bandwidth);
 656         b.full = dfixed_const(wm->num_heads);
 657         a.full = dfixed_div(a, b);
 658
 659         b.full = dfixed_const(mc_latency + 512);
 660         c.full = dfixed_const(wm->disp_clk);
 661         b.full = dfixed_div(b, c);
 662
 663         c.full = dfixed_const(dmif_size);
 664         b.full = dfixed_div(c, b);
 665
 666         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
 667
 668         b.full = dfixed_const(1000);
 669         c.full = dfixed_const(wm->disp_clk);
 670         b.full = dfixed_div(c, b);
 671         c.full = dfixed_const(wm->bytes_per_pixel);
 672         b.full = dfixed_mul(b, c);
 673
 674         lb_fill_bw = min(tmp, dfixed_trunc(b));
 675
 676         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 677         b.full = dfixed_const(1000);
 678         c.full = dfixed_const(lb_fill_bw);
 679         b.full = dfixed_div(c, b);
 680         a.full = dfixed_div(a, b);
 681         line_fill_time = dfixed_trunc(a);
 682
 683         if (line_fill_time < wm->active_time)
 684                 return latency;
 685         else
 686                 return latency + (line_fill_time - wm->active_time);
 687
 688 }
 689
 690 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 691 {
 692         if (dce6_average_bandwidth(wm) <=
 693             (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
 694                 return true;
 695         else
 696                 return false;
 697 };
 698
 699 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 700 {
 701         if (dce6_average_bandwidth(wm) <=
 702             (dce6_available_bandwidth(wm) / wm->num_heads))
 703                 return true;
 704         else
 705                 return false;
 706 };
 707
 708 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
 709 {
 710         u32 lb_partitions = wm->lb_size / wm->src_width;
 711         u32 line_time = wm->active_time + wm->blank_time;
 712         u32 latency_tolerant_lines;
 713         u32 latency_hiding;
 714         fixed20_12 a;
 715
 716         a.full = dfixed_const(1);
 717         if (wm->vsc.full > a.full)
 718                 latency_tolerant_lines = 1;
 719         else {
 720                 if (lb_partitions <= (wm->vtaps + 1))
 721                         latency_tolerant_lines = 1;
 722                 else
 723                         latency_tolerant_lines = 2;
 724         }
 725
 726         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 727
 728         if (dce6_latency_watermark(wm) <= latency_hiding)
 729                 return true;
 730         else
 731                 return false;
 732 }
 733
 734 static void dce6_program_watermarks(struct radeon_device *rdev,
 735                                          struct radeon_crtc *radeon_crtc,
 736                                          u32 lb_size, u32 num_heads)
 737 {
 738         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 739         struct dce6_wm_params wm;
 740         u32 pixel_period;
 741         u32 line_time = 0;
 742         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 743         u32 priority_a_mark = 0, priority_b_mark = 0;
 744         u32 priority_a_cnt = PRIORITY_OFF;
 745         u32 priority_b_cnt = PRIORITY_OFF;
 746         u32 tmp, arb_control3;
 747         fixed20_12 a, b, c;
 748
 749         if (radeon_crtc->base.enabled && num_heads && mode) {
 750                 pixel_period = 1000000 / (u32)mode->clock;
 751                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 752                 priority_a_cnt = 0;
 753                 priority_b_cnt = 0;
 754
 755                 wm.yclk = rdev->pm.current_mclk * 10;
 756                 wm.sclk = rdev->pm.current_sclk * 10;
 757                 wm.disp_clk = mode->clock;
 758                 wm.src_width = mode->crtc_hdisplay;
 759                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 760                 wm.blank_time = line_time - wm.active_time;
 761                 wm.interlaced = false;
 762                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 763                         wm.interlaced = true;
 764                 wm.vsc = radeon_crtc->vsc;
 765                 wm.vtaps = 1;
 766                 if (radeon_crtc->rmx_type != RMX_OFF)
 767                         wm.vtaps = 2;
 768                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 769                 wm.lb_size = lb_size;
 770                 if (rdev->family == CHIP_ARUBA)
 771                         wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 772                 else
 773                         wm.dram_channels = si_get_number_of_dram_channels(rdev);
 774                 wm.num_heads = num_heads;
 775
 776                 /* set for high clocks */
 777                 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
 778                 /* set for low clocks */
 779                 /* wm.yclk = low clk; wm.sclk = low clk */
 780                 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
 781
 782                 /* possibly force display priority to high */
 783                 /* should really do this at mode validation time... */
 784                 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 785                     !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
 786                     !dce6_check_latency_hiding(&wm) ||
 787                     (rdev->disp_priority == 2)) {
 788                         DRM_DEBUG_KMS("force priority to high\n");
 789                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 790                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 791                 }
 792
 793                 a.full = dfixed_const(1000);
 794                 b.full = dfixed_const(mode->clock);
 795                 b.full = dfixed_div(b, a);
 796                 c.full = dfixed_const(latency_watermark_a);
 797                 c.full = dfixed_mul(c, b);
 798                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 799                 c.full = dfixed_div(c, a);
 800                 a.full = dfixed_const(16);
 801                 c.full = dfixed_div(c, a);
 802                 priority_a_mark = dfixed_trunc(c);
 803                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 804
 805                 a.full = dfixed_const(1000);
 806                 b.full = dfixed_const(mode->clock);
 807                 b.full = dfixed_div(b, a);
 808                 c.full = dfixed_const(latency_watermark_b);
 809                 c.full = dfixed_mul(c, b);
 810                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 811                 c.full = dfixed_div(c, a);
 812                 a.full = dfixed_const(16);
 813                 c.full = dfixed_div(c, a);
 814                 priority_b_mark = dfixed_trunc(c);
 815                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 816         }
 817
 818         /* select wm A */
 819         arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 820         tmp = arb_control3;
 821         tmp &= ~LATENCY_WATERMARK_MASK(3);
 822         tmp |= LATENCY_WATERMARK_MASK(1);
 823         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 824         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 825                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 826                 LATENCY_HIGH_WATERMARK(line_time)));
 827         /* select wm B */
 828         tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 829         tmp &= ~LATENCY_WATERMARK_MASK(3);
 830         tmp |= LATENCY_WATERMARK_MASK(2);
 831         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 832         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 833                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 834                 LATENCY_HIGH_WATERMARK(line_time)));
 835         /* restore original selection */
 836         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
 837
 838         /* write the priority marks */
 839         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 840         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 841
 842 }
 843
 844 void dce6_bandwidth_update(struct radeon_device *rdev)
 845 {
 846         struct drm_display_mode *mode0 = NULL;
 847         struct drm_display_mode *mode1 = NULL;
 848         u32 num_heads = 0, lb_size;
 849         int i;
 850
 851         radeon_update_display_priority(rdev);
 852
 853         for (i = 0; i < rdev->num_crtc; i++) {
 854                 if (rdev->mode_info.crtcs[i]->base.enabled)
 855                         num_heads++;
 856         }
 857         for (i = 0; i < rdev->num_crtc; i += 2) {
 858                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 859                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 860                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 861                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 862                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 863                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 864         }
 865 }
 866
 867 /*
 868  * Core functions
 869  */
 870 static void si_tiling_mode_table_init(struct radeon_device *rdev)
 871 {
 872         const u32 num_tile_mode_states = 32;
 873         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 874
 875         switch (rdev->config.si.mem_row_size_in_kb) {
 876         case 1:
 877                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 878                 break;
 879         case 2:
 880         default:
 881                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 882                 break;
 883         case 4:
 884                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 885                 break;
 886         }
 887
 888         if ((rdev->family == CHIP_TAHITI) ||
 889             (rdev->family == CHIP_PITCAIRN)) {
 890                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 891                         switch (reg_offset) {
 892                         case 0:  /* non-AA compressed depth or any compressed stencil */
 893                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 894                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 895                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 896                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 897                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 898                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 899                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 900                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 901                                 break;
 902                         case 1:  /* 2xAA/4xAA compressed depth only */
 903                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 904                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 905                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 906                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 907                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 908                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 909                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 910                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 911                                 break;
 912                         case 2:  /* 8xAA compressed depth only */
 913                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 914                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 915                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 916                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 917                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 918                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 919                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 920                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 921                                 break;
 922                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 923                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 924                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 925                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 926                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 927                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 928                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 929                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 930                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 931                                 break;
 932                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 933                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 934                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 935                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 936                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 937                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 938                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 939                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 940                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 941                                 break;
 942                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
 943                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 944                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 945                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 946                                                  TILE_SPLIT(split_equal_to_row_size) |
 947                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 948                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 949                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 950                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 951                                 break;
 952                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
 953                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 954                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 955                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 956                                                  TILE_SPLIT(split_equal_to_row_size) |
 957                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 958                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 959                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 960                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 961                                 break;
 962                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
 963                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 964                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 965                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 966                                                  TILE_SPLIT(split_equal_to_row_size) |
 967                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 968                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 969                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 970                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 971                                 break;
 972                         case 8:  /* 1D and 1D Array Surfaces */
 973                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 974                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 975                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 976                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 977                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 978                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 979                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 980                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 981                                 break;
 982                         case 9:  /* Displayable maps. */
 983                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 984                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 985                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 986                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 987                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 988                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 989                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 990                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 991                                 break;
 992                         case 10:  /* Display 8bpp. */
 993                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 994                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 995                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 996                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 997                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 998                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 999                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1000                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1001                                 break;
1002                         case 11:  /* Display 16bpp. */
1003                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1004                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1005                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1006                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1007                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1008                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1009                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1010                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1011                                 break;
1012                         case 12:  /* Display 32bpp. */
1013                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1014                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1015                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1017                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1018                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1019                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1020                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1021                                 break;
1022                         case 13:  /* Thin. */
1023                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1024                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1026                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1027                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1028                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1031                                 break;
1032                         case 14:  /* Thin 8 bpp. */
1033                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1035                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1036                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1037                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1038                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1039                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1040                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1041                                 break;
1042                         case 15:  /* Thin 16 bpp. */
1043                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1045                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1046                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1047                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1048                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1049                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1050                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1051                                 break;
1052                         case 16:  /* Thin 32 bpp. */
1053                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1055                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1056                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1057                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1058                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1060                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1061                                 break;
1062                         case 17:  /* Thin 64 bpp. */
1063                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1065                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1066                                                  TILE_SPLIT(split_equal_to_row_size) |
1067                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1068                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1069                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1070                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1071                                 break;
1072                         case 21:  /* 8 bpp PRT. */
1073                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1074                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1075                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1076                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1077                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1078                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1079                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1081                                 break;
1082                         case 22:  /* 16 bpp PRT */
1083                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1085                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1086                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1087                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1088                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1089                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1090                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1091                                 break;
1092                         case 23:  /* 32 bpp PRT */
1093                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1094                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1095                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1096                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1097                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1098                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1100                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1101                                 break;
1102                         case 24:  /* 64 bpp PRT */
1103                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1105                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1106                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1107                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1108                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1109                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1110                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1111                                 break;
1112                         case 25:  /* 128 bpp PRT */
1113                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1114                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1115                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1116                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1117                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1118                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1119                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1120                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1121                                 break;
1122                         default:
1123                                 gb_tile_moden = 0;
1124                                 break;
1125                         }
1126                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1127                 }
1128         } else if (rdev->family == CHIP_VERDE) {
1129                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1130                         switch (reg_offset) {
1131                         case 0:  /* non-AA compressed depth or any compressed stencil */
1132                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1134                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1135                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1136                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1137                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1138                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1139                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1140                                 break;
1141                         case 1:  /* 2xAA/4xAA compressed depth only */
1142                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1143                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1144                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1145                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1146                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1147                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1149                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1150                                 break;
1151                         case 2:  /* 8xAA compressed depth only */
1152                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1153                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1154                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1155                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1156                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1157                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1160                                 break;
1161                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1162                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1163                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1164                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1165                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1166                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1167                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1169                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1170                                 break;
1171                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1172                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1173                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1174                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1175                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1176                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1177                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1179                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1180                                 break;
1181                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1182                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1183                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1184                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1185                                                  TILE_SPLIT(split_equal_to_row_size) |
1186                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1187                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1189                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1190                                 break;
1191                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1192                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1194                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1195                                                  TILE_SPLIT(split_equal_to_row_size) |
1196                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1197                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1199                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1200                                 break;
1201                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1202                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1204                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1205                                                  TILE_SPLIT(split_equal_to_row_size) |
1206                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1207                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1209                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1210                                 break;
1211                         case 8:  /* 1D and 1D Array Surfaces */
1212                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1213                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1214                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1215                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1216                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1217                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1219                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1220                                 break;
1221                         case 9:  /* Displayable maps. */
1222                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1223                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1224                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1225                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1226                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1227                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1229                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1230                                 break;
1231                         case 10:  /* Display 8bpp. */
1232                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1234                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1236                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1237                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1240                                 break;
1241                         case 11:  /* Display 16bpp. */
1242                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1245                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1246                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1247                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1248                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1249                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1250                                 break;
1251                         case 12:  /* Display 32bpp. */
1252                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1254                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1255                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1256                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1257                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1258                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1259                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1260                                 break;
1261                         case 13:  /* Thin. */
1262                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1263                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1266                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1267                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1269                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1270                                 break;
1271                         case 14:  /* Thin 8 bpp. */
1272                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1274                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1276                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1277                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1279                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1280                                 break;
1281                         case 15:  /* Thin 16 bpp. */
1282                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1283                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1284                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1285                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1286                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1287                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1288                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1289                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1290                                 break;
1291                         case 16:  /* Thin 32 bpp. */
1292                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1293                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1294                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1295                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1296                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1297                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1298                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1299                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1300                                 break;
1301                         case 17:  /* Thin 64 bpp. */
1302                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1303                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1304                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1305                                                  TILE_SPLIT(split_equal_to_row_size) |
1306                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1307                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1309                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1310                                 break;
1311                         case 21:  /* 8 bpp PRT. */
1312                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1314                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1315                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1316                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1317                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1318                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1319                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1320                                 break;
1321                         case 22:  /* 16 bpp PRT */
1322                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1323                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1324                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1325                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1326                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1327                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1329                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1330                                 break;
1331                         case 23:  /* 32 bpp PRT */
1332                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1334                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1335                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1336                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1337                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1339                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1340                                 break;
1341                         case 24:  /* 64 bpp PRT */
1342                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1343                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1344                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1345                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1346                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1347                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1350                                 break;
1351                         case 25:  /* 128 bpp PRT */
1352                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1353                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1354                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1355                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1356                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1357                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1360                                 break;
1361                         default:
1362                                 gb_tile_moden = 0;
1363                                 break;
1364                         }
1365                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1366                 }
1367         } else
1368                 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1369 }
1370
1371 static void si_select_se_sh(struct radeon_device *rdev,
1372                             u32 se_num, u32 sh_num)
1373 {
1374         u32 data = INSTANCE_BROADCAST_WRITES;
1375
1376         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1377                 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1378         else if (se_num == 0xffffffff)
1379                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1380         else if (sh_num == 0xffffffff)
1381                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1382         else
1383                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1384         WREG32(GRBM_GFX_INDEX, data);
1385 }
1386
1387 static u32 si_create_bitmask(u32 bit_width)
1388 {
1389         u32 i, mask = 0;
1390
1391         for (i = 0; i < bit_width; i++) {
1392                 mask <<= 1;
1393                 mask |= 1;
1394         }
1395         return mask;
1396 }
1397
1398 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1399 {
1400         u32 data, mask;
1401
1402         data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1403         if (data & 1)
1404                 data &= INACTIVE_CUS_MASK;
1405         else
1406                 data = 0;
1407         data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1408
1409         data >>= INACTIVE_CUS_SHIFT;
1410
1411         mask = si_create_bitmask(cu_per_sh);
1412
1413         return ~data & mask;
1414 }
1415
1416 static void si_setup_spi(struct radeon_device *rdev,
1417                          u32 se_num, u32 sh_per_se,
1418                          u32 cu_per_sh)
1419 {
1420         int i, j, k;
1421         u32 data, mask, active_cu;
1422
1423         for (i = 0; i < se_num; i++) {
1424                 for (j = 0; j < sh_per_se; j++) {
1425                         si_select_se_sh(rdev, i, j);
1426                         data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1427                         active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1428
1429                         mask = 1;
1430                         for (k = 0; k < 16; k++) {
1431                                 mask <<= k;
1432                                 if (active_cu & mask) {
1433                                         data &= ~mask;
1434                                         WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1435                                         break;
1436                                 }
1437                         }
1438                 }
1439         }
1440         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1441 }
1442
1443 static u32 si_get_rb_disabled(struct radeon_device *rdev,
1444                               u32 max_rb_num, u32 se_num,
1445                               u32 sh_per_se)
1446 {
1447         u32 data, mask;
1448
1449         data = RREG32(CC_RB_BACKEND_DISABLE);
1450         if (data & 1)
1451                 data &= BACKEND_DISABLE_MASK;
1452         else
1453                 data = 0;
1454         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1455
1456         data >>= BACKEND_DISABLE_SHIFT;
1457
1458         mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1459
1460         return data & mask;
1461 }
1462
1463 static void si_setup_rb(struct radeon_device *rdev,
1464                         u32 se_num, u32 sh_per_se,
1465                         u32 max_rb_num)
1466 {
1467         int i, j;
1468         u32 data, mask;
1469         u32 disabled_rbs = 0;
1470         u32 enabled_rbs = 0;
1471
1472         for (i = 0; i < se_num; i++) {
1473                 for (j = 0; j < sh_per_se; j++) {
1474                         si_select_se_sh(rdev, i, j);
1475                         data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1476                         disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1477                 }
1478         }
1479         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1480
1481         mask = 1;
1482         for (i = 0; i < max_rb_num; i++) {
1483                 if (!(disabled_rbs & mask))
1484                         enabled_rbs |= mask;
1485                 mask <<= 1;
1486         }
1487
1488         for (i = 0; i < se_num; i++) {
1489                 si_select_se_sh(rdev, i, 0xffffffff);
1490                 data = 0;
1491                 for (j = 0; j < sh_per_se; j++) {
1492                         switch (enabled_rbs & 3) {
1493                         case 1:
1494                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1495                                 break;
1496                         case 2:
1497                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1498                                 break;
1499                         case 3:
1500                         default:
1501                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1502                                 break;
1503                         }
1504                         enabled_rbs >>= 2;
1505                 }
1506                 WREG32(PA_SC_RASTER_CONFIG, data);
1507         }
1508         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1509 }
1510
1511 static void si_gpu_init(struct radeon_device *rdev)
1512 {
1513         u32 gb_addr_config = 0;
1514         u32 mc_shared_chmap, mc_arb_ramcfg;
1515         u32 sx_debug_1;
1516         u32 hdp_host_path_cntl;
1517         u32 tmp;
1518         int i, j;
1519
1520         switch (rdev->family) {
1521         case CHIP_TAHITI:
1522                 rdev->config.si.max_shader_engines = 2;
1523                 rdev->config.si.max_tile_pipes = 12;
1524                 rdev->config.si.max_cu_per_sh = 8;
1525                 rdev->config.si.max_sh_per_se = 2;
1526                 rdev->config.si.max_backends_per_se = 4;
1527                 rdev->config.si.max_texture_channel_caches = 12;
1528                 rdev->config.si.max_gprs = 256;
1529                 rdev->config.si.max_gs_threads = 32;
1530                 rdev->config.si.max_hw_contexts = 8;
1531
1532                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1533                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1534                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1535                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1536                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1537                 break;
1538         case CHIP_PITCAIRN:
1539                 rdev->config.si.max_shader_engines = 2;
1540                 rdev->config.si.max_tile_pipes = 8;
1541                 rdev->config.si.max_cu_per_sh = 5;
1542                 rdev->config.si.max_sh_per_se = 2;
1543                 rdev->config.si.max_backends_per_se = 4;
1544                 rdev->config.si.max_texture_channel_caches = 8;
1545                 rdev->config.si.max_gprs = 256;
1546                 rdev->config.si.max_gs_threads = 32;
1547                 rdev->config.si.max_hw_contexts = 8;
1548
1549                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1550                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1551                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1552                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1553                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1554                 break;
1555         case CHIP_VERDE:
1556         default:
1557                 rdev->config.si.max_shader_engines = 1;
1558                 rdev->config.si.max_tile_pipes = 4;
1559                 rdev->config.si.max_cu_per_sh = 2;
1560                 rdev->config.si.max_sh_per_se = 2;
1561                 rdev->config.si.max_backends_per_se = 4;
1562                 rdev->config.si.max_texture_channel_caches = 4;
1563                 rdev->config.si.max_gprs = 256;
1564                 rdev->config.si.max_gs_threads = 32;
1565                 rdev->config.si.max_hw_contexts = 8;
1566
1567                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1568                 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1569                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1570                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1571                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1572                 break;
1573         }
1574
1575         /* Initialize HDP */
1576         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1577                 WREG32((0x2c14 + j), 0x00000000);
1578                 WREG32((0x2c18 + j), 0x00000000);
1579                 WREG32((0x2c1c + j), 0x00000000);
1580                 WREG32((0x2c20 + j), 0x00000000);
1581                 WREG32((0x2c24 + j), 0x00000000);
1582         }
1583
1584         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1585
1586         evergreen_fix_pci_max_read_req_size(rdev);
1587
1588         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1589
1590         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1591         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1592
1593         rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1594         rdev->config.si.mem_max_burst_length_bytes = 256;
1595         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1596         rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1597         if (rdev->config.si.mem_row_size_in_kb > 4)
1598                 rdev->config.si.mem_row_size_in_kb = 4;
1599         /* XXX use MC settings? */
1600         rdev->config.si.shader_engine_tile_size = 32;
1601         rdev->config.si.num_gpus = 1;
1602         rdev->config.si.multi_gpu_tile_size = 64;
1603
1604         /* fix up row size */
1605         gb_addr_config &= ~ROW_SIZE_MASK;
1606         switch (rdev->config.si.mem_row_size_in_kb) {
1607         case 1:
1608         default:
1609                 gb_addr_config |= ROW_SIZE(0);
1610                 break;
1611         case 2:
1612                 gb_addr_config |= ROW_SIZE(1);
1613                 break;
1614         case 4:
1615                 gb_addr_config |= ROW_SIZE(2);
1616                 break;
1617         }
1618
1619         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1620          * not have bank info, so create a custom tiling dword.
1621          * bits 3:0   num_pipes
1622          * bits 7:4   num_banks
1623          * bits 11:8  group_size
1624          * bits 15:12 row_size
1625          */
1626         rdev->config.si.tile_config = 0;
1627         switch (rdev->config.si.num_tile_pipes) {
1628         case 1:
1629                 rdev->config.si.tile_config |= (0 << 0);
1630                 break;
1631         case 2:
1632                 rdev->config.si.tile_config |= (1 << 0);
1633                 break;
1634         case 4:
1635                 rdev->config.si.tile_config |= (2 << 0);
1636                 break;
1637         case 8:
1638         default:
1639                 /* XXX what about 12? */
1640                 rdev->config.si.tile_config |= (3 << 0);
1641                 break;
1642         }
1643         if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1644                 rdev->config.si.tile_config |= 1 << 4;
1645         else
1646                 rdev->config.si.tile_config |= 0 << 4;
1647         rdev->config.si.tile_config |=
1648                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1649         rdev->config.si.tile_config |=
1650                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1651
1652         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1653         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1654         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1655
1656         si_tiling_mode_table_init(rdev);
1657
1658         si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1659                     rdev->config.si.max_sh_per_se,
1660                     rdev->config.si.max_backends_per_se);
1661
1662         si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1663                      rdev->config.si.max_sh_per_se,
1664                      rdev->config.si.max_cu_per_sh);
1665
1666
1667         /* set HW defaults for 3D engine */
1668         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1669                                      ROQ_IB2_START(0x2b)));
1670         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1671
1672         sx_debug_1 = RREG32(SX_DEBUG_1);
1673         WREG32(SX_DEBUG_1, sx_debug_1);
1674
1675         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1676
1677         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1678                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1679                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1680                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1681
1682         WREG32(VGT_NUM_INSTANCES, 1);
1683
1684         WREG32(CP_PERFMON_CNTL, 0);
1685
1686         WREG32(SQ_CONFIG, 0);
1687
1688         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1689                                           FORCE_EOV_MAX_REZ_CNT(255)));
1690
1691         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1692                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1693
1694         WREG32(VGT_GS_VERTEX_REUSE, 16);
1695         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1696
1697         WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1698         WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1699         WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1700         WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1701         WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1702         WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1703         WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1704         WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1705
1706         tmp = RREG32(HDP_MISC_CNTL);
1707         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1708         WREG32(HDP_MISC_CNTL, tmp);
1709
1710         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1711         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1712
1713         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1714
1715         udelay(50);
1716 }
1717
1718 /*
1719  * GPU scratch registers helpers function.
1720  */
1721 static void si_scratch_init(struct radeon_device *rdev)
1722 {
1723         int i;
1724
1725         rdev->scratch.num_reg = 7;
1726         rdev->scratch.reg_base = SCRATCH_REG0;
1727         for (i = 0; i < rdev->scratch.num_reg; i++) {
1728                 rdev->scratch.free[i] = true;
1729                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1730         }
1731 }
1732
1733 void si_fence_ring_emit(struct radeon_device *rdev,
1734                         struct radeon_fence *fence)
1735 {
1736         struct radeon_ring *ring = &rdev->ring[fence->ring];
1737         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1738
1739         /* flush read cache over gart */
1740         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1741         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1742         radeon_ring_write(ring, 0);
1743         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1744         radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1745                           PACKET3_TC_ACTION_ENA |
1746                           PACKET3_SH_KCACHE_ACTION_ENA |
1747                           PACKET3_SH_ICACHE_ACTION_ENA);
1748         radeon_ring_write(ring, 0xFFFFFFFF);
1749         radeon_ring_write(ring, 0);
1750         radeon_ring_write(ring, 10); /* poll interval */
1751         /* EVENT_WRITE_EOP - flush caches, send int */
1752         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1753         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1754         radeon_ring_write(ring, addr & 0xffffffff);
1755         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1756         radeon_ring_write(ring, fence->seq);
1757         radeon_ring_write(ring, 0);
1758 }
1759
1760 /*
1761  * IB stuff
1762  */
1763 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1764 {
1765         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1766         u32 header;
1767
1768         if (ib->is_const_ib)
1769                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1770         else
1771                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1772
1773         radeon_ring_write(ring, header);
1774         radeon_ring_write(ring,
1775 #ifdef __BIG_ENDIAN
1776                           (2 << 0) |
1777 #endif
1778                           (ib->gpu_addr & 0xFFFFFFFC));
1779         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1780         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1781
1782         /* flush read cache over gart for this vmid */
1783         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1784         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1785         radeon_ring_write(ring, ib->vm_id);
1786         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1787         radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1788                           PACKET3_TC_ACTION_ENA |
1789                           PACKET3_SH_KCACHE_ACTION_ENA |
1790                           PACKET3_SH_ICACHE_ACTION_ENA);
1791         radeon_ring_write(ring, 0xFFFFFFFF);
1792         radeon_ring_write(ring, 0);
1793         radeon_ring_write(ring, 10); /* poll interval */
1794 }
1795
1796 /*
1797  * CP.
1798  */
1799 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1800 {
1801         if (enable)
1802                 WREG32(CP_ME_CNTL, 0);
1803         else {
1804                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1805                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1806                 WREG32(SCRATCH_UMSK, 0);
1807         }
1808         udelay(50);
1809 }
1810
1811 static int si_cp_load_microcode(struct radeon_device *rdev)
1812 {
1813         const __be32 *fw_data;
1814         int i;
1815
1816         if (!rdev->me_fw || !rdev->pfp_fw)
1817                 return -EINVAL;
1818
1819         si_cp_enable(rdev, false);
1820
1821         /* PFP */
1822         fw_data = (const __be32 *)rdev->pfp_fw->data;
1823         WREG32(CP_PFP_UCODE_ADDR, 0);
1824         for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1825                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1826         WREG32(CP_PFP_UCODE_ADDR, 0);
1827
1828         /* CE */
1829         fw_data = (const __be32 *)rdev->ce_fw->data;
1830         WREG32(CP_CE_UCODE_ADDR, 0);
1831         for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1832                 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1833         WREG32(CP_CE_UCODE_ADDR, 0);
1834
1835         /* ME */
1836         fw_data = (const __be32 *)rdev->me_fw->data;
1837         WREG32(CP_ME_RAM_WADDR, 0);
1838         for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1839                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1840         WREG32(CP_ME_RAM_WADDR, 0);
1841
1842         WREG32(CP_PFP_UCODE_ADDR, 0);
1843         WREG32(CP_CE_UCODE_ADDR, 0);
1844         WREG32(CP_ME_RAM_WADDR, 0);
1845         WREG32(CP_ME_RAM_RADDR, 0);
1846         return 0;
1847 }
1848
1849 static int si_cp_start(struct radeon_device *rdev)
1850 {
1851         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1852         int r, i;
1853
1854         r = radeon_ring_lock(rdev, ring, 7 + 4);
1855         if (r) {
1856                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1857                 return r;
1858         }
1859         /* init the CP */
1860         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1861         radeon_ring_write(ring, 0x1);
1862         radeon_ring_write(ring, 0x0);
1863         radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1864         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1865         radeon_ring_write(ring, 0);
1866         radeon_ring_write(ring, 0);
1867
1868         /* init the CE partitions */
1869         radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1870         radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1871         radeon_ring_write(ring, 0xc000);
1872         radeon_ring_write(ring, 0xe000);
1873         radeon_ring_unlock_commit(rdev, ring);
1874
1875         si_cp_enable(rdev, true);
1876
1877         r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1878         if (r) {
1879                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1880                 return r;
1881         }
1882
1883         /* setup clear context state */
1884         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1885         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1886
1887         for (i = 0; i < si_default_size; i++)
1888                 radeon_ring_write(ring, si_default_state[i]);
1889
1890         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1891         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1892
1893         /* set clear context state */
1894         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1895         radeon_ring_write(ring, 0);
1896
1897         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1898         radeon_ring_write(ring, 0x00000316);
1899         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1900         radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1901
1902         radeon_ring_unlock_commit(rdev, ring);
1903
1904         for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1905                 ring = &rdev->ring[i];
1906                 r = radeon_ring_lock(rdev, ring, 2);
1907
1908                 /* clear the compute context state */
1909                 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1910                 radeon_ring_write(ring, 0);
1911
1912                 radeon_ring_unlock_commit(rdev, ring);
1913         }
1914
1915         return 0;
1916 }
1917
1918 static void si_cp_fini(struct radeon_device *rdev)
1919 {
1920         si_cp_enable(rdev, false);
1921         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1922         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
1923         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
1924 }
1925
1926 static int si_cp_resume(struct radeon_device *rdev)
1927 {
1928         struct radeon_ring *ring;
1929         u32 tmp;
1930         u32 rb_bufsz;
1931         int r;
1932
1933         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1934         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1935                                  SOFT_RESET_PA |
1936                                  SOFT_RESET_VGT |
1937                                  SOFT_RESET_SPI |
1938                                  SOFT_RESET_SX));
1939         RREG32(GRBM_SOFT_RESET);
1940         mdelay(15);
1941         WREG32(GRBM_SOFT_RESET, 0);
1942         RREG32(GRBM_SOFT_RESET);
1943
1944         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1945         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1946
1947         /* Set the write pointer delay */
1948         WREG32(CP_RB_WPTR_DELAY, 0);
1949
1950         WREG32(CP_DEBUG, 0);
1951         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1952
1953         /* ring 0 - compute and gfx */
1954         /* Set ring buffer size */
1955         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1956         rb_bufsz = drm_order(ring->ring_size / 8);
1957         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1958 #ifdef __BIG_ENDIAN
1959         tmp |= BUF_SWAP_32BIT;
1960 #endif
1961         WREG32(CP_RB0_CNTL, tmp);
1962
1963         /* Initialize the ring buffer's read and write pointers */
1964         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1965         ring->wptr = 0;
1966         WREG32(CP_RB0_WPTR, ring->wptr);
1967
1968         /* set the wb address wether it's enabled or not */
1969         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1970         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1971
1972         if (rdev->wb.enabled)
1973                 WREG32(SCRATCH_UMSK, 0xff);
1974         else {
1975                 tmp |= RB_NO_UPDATE;
1976                 WREG32(SCRATCH_UMSK, 0);
1977         }
1978
1979         mdelay(1);
1980         WREG32(CP_RB0_CNTL, tmp);
1981
1982         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1983
1984         ring->rptr = RREG32(CP_RB0_RPTR);
1985
1986         /* ring1  - compute only */
1987         /* Set ring buffer size */
1988         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1989         rb_bufsz = drm_order(ring->ring_size / 8);
1990         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1991 #ifdef __BIG_ENDIAN
1992         tmp |= BUF_SWAP_32BIT;
1993 #endif
1994         WREG32(CP_RB1_CNTL, tmp);
1995
1996         /* Initialize the ring buffer's read and write pointers */
1997         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1998         ring->wptr = 0;
1999         WREG32(CP_RB1_WPTR, ring->wptr);
2000
2001         /* set the wb address wether it's enabled or not */
2002         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2003         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2004
2005         mdelay(1);
2006         WREG32(CP_RB1_CNTL, tmp);
2007
2008         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2009
2010         ring->rptr = RREG32(CP_RB1_RPTR);
2011
2012         /* ring2 - compute only */
2013         /* Set ring buffer size */
2014         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2015         rb_bufsz = drm_order(ring->ring_size / 8);
2016         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2017 #ifdef __BIG_ENDIAN
2018         tmp |= BUF_SWAP_32BIT;
2019 #endif
2020         WREG32(CP_RB2_CNTL, tmp);
2021
2022         /* Initialize the ring buffer's read and write pointers */
2023         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2024         ring->wptr = 0;
2025         WREG32(CP_RB2_WPTR, ring->wptr);
2026
2027         /* set the wb address wether it's enabled or not */
2028         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2029         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2030
2031         mdelay(1);
2032         WREG32(CP_RB2_CNTL, tmp);
2033
2034         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2035
2036         ring->rptr = RREG32(CP_RB2_RPTR);
2037
2038         /* start the rings */
2039         si_cp_start(rdev);
2040         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2041         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2042         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2043         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2044         if (r) {
2045                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2046                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2047                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2048                 return r;
2049         }
2050         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2051         if (r) {
2052                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2053         }
2054         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2055         if (r) {
2056                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2057         }
2058
2059         return 0;
2060 }
2061
2062 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2063 {
2064         u32 srbm_status;
2065         u32 grbm_status, grbm_status2;
2066         u32 grbm_status_se0, grbm_status_se1;
2067
2068         srbm_status = RREG32(SRBM_STATUS);
2069         grbm_status = RREG32(GRBM_STATUS);
2070         grbm_status2 = RREG32(GRBM_STATUS2);
2071         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2072         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2073         if (!(grbm_status & GUI_ACTIVE)) {
2074                 radeon_ring_lockup_update(ring);
2075                 return false;
2076         }
2077         /* force CP activities */
2078         radeon_ring_force_activity(rdev, ring);
2079         return radeon_ring_test_lockup(rdev, ring);
2080 }
2081
2082 static int si_gpu_soft_reset(struct radeon_device *rdev)
2083 {
2084         struct evergreen_mc_save save;
2085         u32 grbm_reset = 0;
2086
2087         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2088                 return 0;
2089
2090         dev_info(rdev->dev, "GPU softreset \n");
2091         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2092                 RREG32(GRBM_STATUS));
2093         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2094                 RREG32(GRBM_STATUS2));
2095         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2096                 RREG32(GRBM_STATUS_SE0));
2097         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2098                 RREG32(GRBM_STATUS_SE1));
2099         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2100                 RREG32(SRBM_STATUS));
2101         evergreen_mc_stop(rdev, &save);
2102         if (radeon_mc_wait_for_idle(rdev)) {
2103                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2104         }
2105         /* Disable CP parsing/prefetching */
2106         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2107
2108         /* reset all the gfx blocks */
2109         grbm_reset = (SOFT_RESET_CP |
2110                       SOFT_RESET_CB |
2111                       SOFT_RESET_DB |
2112                       SOFT_RESET_GDS |
2113                       SOFT_RESET_PA |
2114                       SOFT_RESET_SC |
2115                       SOFT_RESET_BCI |
2116                       SOFT_RESET_SPI |
2117                       SOFT_RESET_SX |
2118                       SOFT_RESET_TC |
2119                       SOFT_RESET_TA |
2120                       SOFT_RESET_VGT |
2121                       SOFT_RESET_IA);
2122
2123         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2124         WREG32(GRBM_SOFT_RESET, grbm_reset);
2125         (void)RREG32(GRBM_SOFT_RESET);
2126         udelay(50);
2127         WREG32(GRBM_SOFT_RESET, 0);
2128         (void)RREG32(GRBM_SOFT_RESET);
2129         /* Wait a little for things to settle down */
2130         udelay(50);
2131         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2132                 RREG32(GRBM_STATUS));
2133         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2134                 RREG32(GRBM_STATUS2));
2135         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2136                 RREG32(GRBM_STATUS_SE0));
2137         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2138                 RREG32(GRBM_STATUS_SE1));
2139         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2140                 RREG32(SRBM_STATUS));
2141         evergreen_mc_resume(rdev, &save);
2142         return 0;
2143 }
2144
2145 int si_asic_reset(struct radeon_device *rdev)
2146 {
2147         return si_gpu_soft_reset(rdev);
2148 }
2149
2150 /* MC */
2151 static void si_mc_program(struct radeon_device *rdev)
2152 {
2153         struct evergreen_mc_save save;
2154         u32 tmp;
2155         int i, j;
2156
2157         /* Initialize HDP */
2158         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2159                 WREG32((0x2c14 + j), 0x00000000);
2160                 WREG32((0x2c18 + j), 0x00000000);
2161                 WREG32((0x2c1c + j), 0x00000000);
2162                 WREG32((0x2c20 + j), 0x00000000);
2163                 WREG32((0x2c24 + j), 0x00000000);
2164         }
2165         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2166
2167         evergreen_mc_stop(rdev, &save);
2168         if (radeon_mc_wait_for_idle(rdev)) {
2169                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2170         }
2171         /* Lockout access through VGA aperture*/
2172         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2173         /* Update configuration */
2174         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2175                rdev->mc.vram_start >> 12);
2176         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2177                rdev->mc.vram_end >> 12);
2178         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2179                rdev->vram_scratch.gpu_addr >> 12);
2180         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2181         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2182         WREG32(MC_VM_FB_LOCATION, tmp);
2183         /* XXX double check these! */
2184         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2185         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2186         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2187         WREG32(MC_VM_AGP_BASE, 0);
2188         WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2189         WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2190         if (radeon_mc_wait_for_idle(rdev)) {
2191                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2192         }
2193         evergreen_mc_resume(rdev, &save);
2194         /* we need to own VRAM, so turn off the VGA renderer here
2195          * to stop it overwriting our objects */
2196         rv515_vga_render_disable(rdev);
2197 }
2198
2199 /* SI MC address space is 40 bits */
2200 static void si_vram_location(struct radeon_device *rdev,
2201                              struct radeon_mc *mc, u64 base)
2202 {
2203         mc->vram_start = base;
2204         if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2205                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2206                 mc->real_vram_size = mc->aper_size;
2207                 mc->mc_vram_size = mc->aper_size;
2208         }
2209         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2210         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2211                         mc->mc_vram_size >> 20, mc->vram_start,
2212                         mc->vram_end, mc->real_vram_size >> 20);
2213 }
2214
2215 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2216 {
2217         u64 size_af, size_bf;
2218
2219         size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2220         size_bf = mc->vram_start & ~mc->gtt_base_align;
2221         if (size_bf > size_af) {
2222                 if (mc->gtt_size > size_bf) {
2223                         dev_warn(rdev->dev, "limiting GTT\n");
2224                         mc->gtt_size = size_bf;
2225                 }
2226                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2227         } else {
2228                 if (mc->gtt_size > size_af) {
2229                         dev_warn(rdev->dev, "limiting GTT\n");
2230                         mc->gtt_size = size_af;
2231                 }
2232                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2233         }
2234         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2235         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2236                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2237 }
2238
2239 static void si_vram_gtt_location(struct radeon_device *rdev,
2240                                  struct radeon_mc *mc)
2241 {
2242         if (mc->mc_vram_size > 0xFFC0000000ULL) {
2243                 /* leave room for at least 1024M GTT */
2244                 dev_warn(rdev->dev, "limiting VRAM\n");
2245                 mc->real_vram_size = 0xFFC0000000ULL;
2246                 mc->mc_vram_size = 0xFFC0000000ULL;
2247         }
2248         si_vram_location(rdev, &rdev->mc, 0);
2249         rdev->mc.gtt_base_align = 0;
2250         si_gtt_location(rdev, mc);
2251 }
2252
2253 static int si_mc_init(struct radeon_device *rdev)
2254 {
2255         u32 tmp;
2256         int chansize, numchan;
2257
2258         /* Get VRAM informations */
2259         rdev->mc.vram_is_ddr = true;
2260         tmp = RREG32(MC_ARB_RAMCFG);
2261         if (tmp & CHANSIZE_OVERRIDE) {
2262                 chansize = 16;
2263         } else if (tmp & CHANSIZE_MASK) {
2264                 chansize = 64;
2265         } else {
2266                 chansize = 32;
2267         }
2268         tmp = RREG32(MC_SHARED_CHMAP);
2269         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2270         case 0:
2271         default:
2272                 numchan = 1;
2273                 break;
2274         case 1:
2275                 numchan = 2;
2276                 break;
2277         case 2:
2278                 numchan = 4;
2279                 break;
2280         case 3:
2281                 numchan = 8;
2282                 break;
2283         case 4:
2284                 numchan = 3;
2285                 break;
2286         case 5:
2287                 numchan = 6;
2288                 break;
2289         case 6:
2290                 numchan = 10;
2291                 break;
2292         case 7:
2293                 numchan = 12;
2294                 break;
2295         case 8:
2296                 numchan = 16;
2297                 break;
2298         }
2299         rdev->mc.vram_width = numchan * chansize;
2300         /* Could aper size report 0 ? */
2301         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2302         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2303         /* size in MB on si */
2304         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2305         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2306         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2307         si_vram_gtt_location(rdev, &rdev->mc);
2308         radeon_update_bandwidth_info(rdev);
2309
2310         return 0;
2311 }
2312
2313 /*
2314  * GART
2315  */
2316 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2317 {
2318         /* flush hdp cache */
2319         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2320
2321         /* bits 0-15 are the VM contexts0-15 */
2322         WREG32(VM_INVALIDATE_REQUEST, 1);
2323 }
2324
2325 int si_pcie_gart_enable(struct radeon_device *rdev)
2326 {
2327         int r, i;
2328
2329         if (rdev->gart.robj == NULL) {
2330                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2331                 return -EINVAL;
2332         }
2333         r = radeon_gart_table_vram_pin(rdev);
2334         if (r)
2335                 return r;
2336         radeon_gart_restore(rdev);
2337         /* Setup TLB control */
2338         WREG32(MC_VM_MX_L1_TLB_CNTL,
2339                (0xA << 7) |
2340                ENABLE_L1_TLB |
2341                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2342                ENABLE_ADVANCED_DRIVER_MODEL |
2343                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2344         /* Setup L2 cache */
2345         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2346                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2347                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2348                EFFECTIVE_L2_QUEUE_SIZE(7) |
2349                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2350         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2351         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2352                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2353         /* setup context0 */
2354         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2355         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2356         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2357         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2358                         (u32)(rdev->dummy_page.addr >> 12));
2359         WREG32(VM_CONTEXT0_CNTL2, 0);
2360         WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2361                                   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2362
2363         WREG32(0x15D4, 0);
2364         WREG32(0x15D8, 0);
2365         WREG32(0x15DC, 0);
2366
2367         /* empty context1-15 */
2368         /* FIXME start with 4G, once using 2 level pt switch to full
2369          * vm size space
2370          */
2371         /* set vm size, must be a multiple of 4 */
2372         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2373         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2374         for (i = 1; i < 16; i++) {
2375                 if (i < 8)
2376                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2377                                rdev->gart.table_addr >> 12);
2378                 else
2379                         WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2380                                rdev->gart.table_addr >> 12);
2381         }
2382
2383         /* enable context1-15 */
2384         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2385                (u32)(rdev->dummy_page.addr >> 12));
2386         WREG32(VM_CONTEXT1_CNTL2, 0);
2387         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2388                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2389
2390         si_pcie_gart_tlb_flush(rdev);
2391         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2392                  (unsigned)(rdev->mc.gtt_size >> 20),
2393                  (unsigned long long)rdev->gart.table_addr);
2394         rdev->gart.ready = true;
2395         return 0;
2396 }
2397
2398 void si_pcie_gart_disable(struct radeon_device *rdev)
2399 {
2400         /* Disable all tables */
2401         WREG32(VM_CONTEXT0_CNTL, 0);
2402         WREG32(VM_CONTEXT1_CNTL, 0);
2403         /* Setup TLB control */
2404         WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2405                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2406         /* Setup L2 cache */
2407         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2408                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2409                EFFECTIVE_L2_QUEUE_SIZE(7) |
2410                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2411         WREG32(VM_L2_CNTL2, 0);
2412         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2413                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2414         radeon_gart_table_vram_unpin(rdev);
2415 }
2416
2417 void si_pcie_gart_fini(struct radeon_device *rdev)
2418 {
2419         si_pcie_gart_disable(rdev);
2420         radeon_gart_table_vram_free(rdev);
2421         radeon_gart_fini(rdev);
2422 }
2423
2424 /* vm parser */
2425 static bool si_vm_reg_valid(u32 reg)
2426 {
2427         /* context regs are fine */
2428         if (reg >= 0x28000)
2429                 return true;
2430
2431         /* check config regs */
2432         switch (reg) {
2433         case GRBM_GFX_INDEX:
2434         case VGT_VTX_VECT_EJECT_REG:
2435         case VGT_CACHE_INVALIDATION:
2436         case VGT_ESGS_RING_SIZE:
2437         case VGT_GSVS_RING_SIZE:
2438         case VGT_GS_VERTEX_REUSE:
2439         case VGT_PRIMITIVE_TYPE:
2440         case VGT_INDEX_TYPE:
2441         case VGT_NUM_INDICES:
2442         case VGT_NUM_INSTANCES:
2443         case VGT_TF_RING_SIZE:
2444         case VGT_HS_OFFCHIP_PARAM:
2445         case VGT_TF_MEMORY_BASE:
2446         case PA_CL_ENHANCE:
2447         case PA_SU_LINE_STIPPLE_VALUE:
2448         case PA_SC_LINE_STIPPLE_STATE:
2449         case PA_SC_ENHANCE:
2450         case SQC_CACHES:
2451         case SPI_STATIC_THREAD_MGMT_1:
2452         case SPI_STATIC_THREAD_MGMT_2:
2453         case SPI_STATIC_THREAD_MGMT_3:
2454         case SPI_PS_MAX_WAVE_ID:
2455         case SPI_CONFIG_CNTL:
2456         case SPI_CONFIG_CNTL_1:
2457         case TA_CNTL_AUX:
2458                 return true;
2459         default:
2460                 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2461                 return false;
2462         }
2463 }
2464
2465 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2466                                   u32 *ib, struct radeon_cs_packet *pkt)
2467 {
2468         switch (pkt->opcode) {
2469         case PACKET3_NOP:
2470         case PACKET3_SET_BASE:
2471         case PACKET3_SET_CE_DE_COUNTERS:
2472         case PACKET3_LOAD_CONST_RAM:
2473         case PACKET3_WRITE_CONST_RAM:
2474         case PACKET3_WRITE_CONST_RAM_OFFSET:
2475         case PACKET3_DUMP_CONST_RAM:
2476         case PACKET3_INCREMENT_CE_COUNTER:
2477         case PACKET3_WAIT_ON_DE_COUNTER:
2478         case PACKET3_CE_WRITE:
2479                 break;
2480         default:
2481                 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2482                 return -EINVAL;
2483         }
2484         return 0;
2485 }
2486
2487 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2488                                    u32 *ib, struct radeon_cs_packet *pkt)
2489 {
2490         u32 idx = pkt->idx + 1;
2491         u32 idx_value = ib[idx];
2492         u32 start_reg, end_reg, reg, i;
2493
2494         switch (pkt->opcode) {
2495         case PACKET3_NOP:
2496         case PACKET3_SET_BASE:
2497         case PACKET3_CLEAR_STATE:
2498         case PACKET3_INDEX_BUFFER_SIZE:
2499         case PACKET3_DISPATCH_DIRECT:
2500         case PACKET3_DISPATCH_INDIRECT:
2501         case PACKET3_ALLOC_GDS:
2502         case PACKET3_WRITE_GDS_RAM:
2503         case PACKET3_ATOMIC_GDS:
2504         case PACKET3_ATOMIC:
2505         case PACKET3_OCCLUSION_QUERY:
2506         case PACKET3_SET_PREDICATION:
2507         case PACKET3_COND_EXEC:
2508         case PACKET3_PRED_EXEC:
2509         case PACKET3_DRAW_INDIRECT:
2510         case PACKET3_DRAW_INDEX_INDIRECT:
2511         case PACKET3_INDEX_BASE:
2512         case PACKET3_DRAW_INDEX_2:
2513         case PACKET3_CONTEXT_CONTROL:
2514         case PACKET3_INDEX_TYPE:
2515         case PACKET3_DRAW_INDIRECT_MULTI:
2516         case PACKET3_DRAW_INDEX_AUTO:
2517         case PACKET3_DRAW_INDEX_IMMD:
2518         case PACKET3_NUM_INSTANCES:
2519         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2520         case PACKET3_STRMOUT_BUFFER_UPDATE:
2521         case PACKET3_DRAW_INDEX_OFFSET_2:
2522         case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2523         case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2524         case PACKET3_MPEG_INDEX:
2525         case PACKET3_WAIT_REG_MEM:
2526         case PACKET3_MEM_WRITE:
2527         case PACKET3_PFP_SYNC_ME:
2528         case PACKET3_SURFACE_SYNC:
2529         case PACKET3_EVENT_WRITE:
2530         case PACKET3_EVENT_WRITE_EOP:
2531         case PACKET3_EVENT_WRITE_EOS:
2532         case PACKET3_SET_CONTEXT_REG:
2533         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2534         case PACKET3_SET_SH_REG:
2535         case PACKET3_SET_SH_REG_OFFSET:
2536         case PACKET3_INCREMENT_DE_COUNTER:
2537         case PACKET3_WAIT_ON_CE_COUNTER:
2538         case PACKET3_WAIT_ON_AVAIL_BUFFER:
2539         case PACKET3_ME_WRITE:
2540                 break;
2541         case PACKET3_COPY_DATA:
2542                 if ((idx_value & 0xf00) == 0) {
2543                         reg = ib[idx + 3] * 4;
2544                         if (!si_vm_reg_valid(reg))
2545                                 return -EINVAL;
2546                 }
2547                 break;
2548         case PACKET3_WRITE_DATA:
2549                 if ((idx_value & 0xf00) == 0) {
2550                         start_reg = ib[idx + 1] * 4;
2551                         if (idx_value & 0x10000) {
2552                                 if (!si_vm_reg_valid(start_reg))
2553                                         return -EINVAL;
2554                         } else {
2555                                 for (i = 0; i < (pkt->count - 2); i++) {
2556                                         reg = start_reg + (4 * i);
2557                                         if (!si_vm_reg_valid(reg))
2558                                                 return -EINVAL;
2559                                 }
2560                         }
2561                 }
2562                 break;
2563         case PACKET3_COND_WRITE:
2564                 if (idx_value & 0x100) {
2565                         reg = ib[idx + 5] * 4;
2566                         if (!si_vm_reg_valid(reg))
2567                                 return -EINVAL;
2568                 }
2569                 break;
2570         case PACKET3_COPY_DW:
2571                 if (idx_value & 0x2) {
2572                         reg = ib[idx + 3] * 4;
2573                         if (!si_vm_reg_valid(reg))
2574                                 return -EINVAL;
2575                 }
2576                 break;
2577         case PACKET3_SET_CONFIG_REG:
2578                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2579                 end_reg = 4 * pkt->count + start_reg - 4;
2580                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2581                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2582                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2583                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2584                         return -EINVAL;
2585                 }
2586                 for (i = 0; i < pkt->count; i++) {
2587                         reg = start_reg + (4 * i);
2588                         if (!si_vm_reg_valid(reg))
2589                                 return -EINVAL;
2590                 }
2591                 break;
2592         default:
2593                 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2594                 return -EINVAL;
2595         }
2596         return 0;
2597 }
2598
2599 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2600                                        u32 *ib, struct radeon_cs_packet *pkt)
2601 {
2602         u32 idx = pkt->idx + 1;
2603         u32 idx_value = ib[idx];
2604         u32 start_reg, reg, i;
2605
2606         switch (pkt->opcode) {
2607         case PACKET3_NOP:
2608         case PACKET3_SET_BASE:
2609         case PACKET3_CLEAR_STATE:
2610         case PACKET3_DISPATCH_DIRECT:
2611         case PACKET3_DISPATCH_INDIRECT:
2612         case PACKET3_ALLOC_GDS:
2613         case PACKET3_WRITE_GDS_RAM:
2614         case PACKET3_ATOMIC_GDS:
2615         case PACKET3_ATOMIC:
2616         case PACKET3_OCCLUSION_QUERY:
2617         case PACKET3_SET_PREDICATION:
2618         case PACKET3_COND_EXEC:
2619         case PACKET3_PRED_EXEC:
2620         case PACKET3_CONTEXT_CONTROL:
2621         case PACKET3_STRMOUT_BUFFER_UPDATE:
2622         case PACKET3_WAIT_REG_MEM:
2623         case PACKET3_MEM_WRITE:
2624         case PACKET3_PFP_SYNC_ME:
2625         case PACKET3_SURFACE_SYNC:
2626         case PACKET3_EVENT_WRITE:
2627         case PACKET3_EVENT_WRITE_EOP:
2628         case PACKET3_EVENT_WRITE_EOS:
2629         case PACKET3_SET_CONTEXT_REG:
2630         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2631         case PACKET3_SET_SH_REG:
2632         case PACKET3_SET_SH_REG_OFFSET:
2633         case PACKET3_INCREMENT_DE_COUNTER:
2634         case PACKET3_WAIT_ON_CE_COUNTER:
2635         case PACKET3_WAIT_ON_AVAIL_BUFFER:
2636         case PACKET3_ME_WRITE:
2637                 break;
2638         case PACKET3_COPY_DATA:
2639                 if ((idx_value & 0xf00) == 0) {
2640                         reg = ib[idx + 3] * 4;
2641                         if (!si_vm_reg_valid(reg))
2642                                 return -EINVAL;
2643                 }
2644                 break;
2645         case PACKET3_WRITE_DATA:
2646                 if ((idx_value & 0xf00) == 0) {
2647                         start_reg = ib[idx + 1] * 4;
2648                         if (idx_value & 0x10000) {
2649                                 if (!si_vm_reg_valid(start_reg))
2650                                         return -EINVAL;
2651                         } else {
2652                                 for (i = 0; i < (pkt->count - 2); i++) {
2653                                         reg = start_reg + (4 * i);
2654                                         if (!si_vm_reg_valid(reg))
2655                                                 return -EINVAL;
2656                                 }
2657                         }
2658                 }
2659                 break;
2660         case PACKET3_COND_WRITE:
2661                 if (idx_value & 0x100) {
2662                         reg = ib[idx + 5] * 4;
2663                         if (!si_vm_reg_valid(reg))
2664                                 return -EINVAL;
2665                 }
2666                 break;
2667         case PACKET3_COPY_DW:
2668                 if (idx_value & 0x2) {
2669                         reg = ib[idx + 3] * 4;
2670                         if (!si_vm_reg_valid(reg))
2671                                 return -EINVAL;
2672                 }
2673                 break;
2674         default:
2675                 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2676                 return -EINVAL;
2677         }
2678         return 0;
2679 }
2680
2681 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2682 {
2683         int ret = 0;
2684         u32 idx = 0;
2685         struct radeon_cs_packet pkt;
2686
2687         do {
2688                 pkt.idx = idx;
2689                 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2690                 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2691                 pkt.one_reg_wr = 0;
2692                 switch (pkt.type) {
2693                 case PACKET_TYPE0:
2694                         dev_err(rdev->dev, "Packet0 not allowed!\n");
2695                         ret = -EINVAL;
2696                         break;
2697                 case PACKET_TYPE2:
2698                         idx += 1;
2699                         break;
2700                 case PACKET_TYPE3:
2701                         pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2702                         if (ib->is_const_ib)
2703                                 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2704                         else {
2705                                 switch (ib->fence->ring) {
2706                                 case RADEON_RING_TYPE_GFX_INDEX:
2707                                         ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2708                                         break;
2709                                 case CAYMAN_RING_TYPE_CP1_INDEX:
2710                                 case CAYMAN_RING_TYPE_CP2_INDEX:
2711                                         ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2712                                         break;
2713                                 default:
2714                                         dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring);
2715                                         ret = -EINVAL;
2716                                         break;
2717                                 }
2718                         }
2719                         idx += pkt.count + 2;
2720                         break;
2721                 default:
2722                         dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2723                         ret = -EINVAL;
2724                         break;
2725                 }
2726                 if (ret)
2727                         break;
2728         } while (idx < ib->length_dw);
2729
2730         return ret;
2731 }
2732
2733 /*
2734  * vm
2735  */
2736 int si_vm_init(struct radeon_device *rdev)
2737 {
2738         /* number of VMs */
2739         rdev->vm_manager.nvm = 16;
2740         /* base offset of vram pages */
2741         rdev->vm_manager.vram_base_offset = 0;
2742
2743         return 0;
2744 }
2745
2746 void si_vm_fini(struct radeon_device *rdev)
2747 {
2748 }
2749
2750 int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
2751 {
2752         if (id < 8)
2753                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
2754         else
2755                 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
2756                        vm->pt_gpu_addr >> 12);
2757         /* flush hdp cache */
2758         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2759         /* bits 0-15 are the VM contexts0-15 */
2760         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
2761         return 0;
2762 }
2763
2764 void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
2765 {
2766         if (vm->id < 8)
2767                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
2768         else
2769                 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
2770         /* flush hdp cache */
2771         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2772         /* bits 0-15 are the VM contexts0-15 */
2773         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2774 }
2775
2776 void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
2777 {
2778         if (vm->id == -1)
2779                 return;
2780
2781         /* flush hdp cache */
2782         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2783         /* bits 0-15 are the VM contexts0-15 */
2784         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2785 }
2786
2787 /*
2788  * RLC
2789  */
2790 void si_rlc_fini(struct radeon_device *rdev)
2791 {
2792         int r;
2793
2794         /* save restore block */
2795         if (rdev->rlc.save_restore_obj) {
2796                 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2797                 if (unlikely(r != 0))
2798                         dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
2799                 radeon_bo_unpin(rdev->rlc.save_restore_obj);
2800                 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2801
2802                 radeon_bo_unref(&rdev->rlc.save_restore_obj);
2803                 rdev->rlc.save_restore_obj = NULL;
2804         }
2805
2806         /* clear state block */
2807         if (rdev->rlc.clear_state_obj) {
2808                 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2809                 if (unlikely(r != 0))
2810                         dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
2811                 radeon_bo_unpin(rdev->rlc.clear_state_obj);
2812                 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
2813
2814                 radeon_bo_unref(&rdev->rlc.clear_state_obj);
2815                 rdev->rlc.clear_state_obj = NULL;
2816         }
2817 }
2818
2819 int si_rlc_init(struct radeon_device *rdev)
2820 {
2821         int r;
2822
2823         /* save restore block */
2824         if (rdev->rlc.save_restore_obj == NULL) {
2825                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
2826                                      RADEON_GEM_DOMAIN_VRAM, NULL,
2827                                      &rdev->rlc.save_restore_obj);
2828                 if (r) {
2829                         dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
2830                         return r;
2831                 }
2832         }
2833
2834         r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2835         if (unlikely(r != 0)) {
2836                 si_rlc_fini(rdev);
2837                 return r;
2838         }
2839         r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
2840                           &rdev->rlc.save_restore_gpu_addr);
2841         radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2842         if (r) {
2843                 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
2844                 si_rlc_fini(rdev);
2845                 return r;
2846         }
2847
2848         /* clear state block */
2849         if (rdev->rlc.clear_state_obj == NULL) {
2850                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
2851                                      RADEON_GEM_DOMAIN_VRAM, NULL,
2852                                      &rdev->rlc.clear_state_obj);
2853                 if (r) {
2854                         dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
2855                         si_rlc_fini(rdev);
2856                         return r;
2857                 }
2858         }
2859         r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2860         if (unlikely(r != 0)) {
2861                 si_rlc_fini(rdev);
2862                 return r;
2863         }
2864         r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
2865                           &rdev->rlc.clear_state_gpu_addr);
2866         radeon_bo_unreserve(rdev->rlc.clear_state_obj);
2867         if (r) {
2868                 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
2869                 si_rlc_fini(rdev);
2870                 return r;
2871         }
2872
2873         return 0;
2874 }
2875
2876 static void si_rlc_stop(struct radeon_device *rdev)
2877 {
2878         WREG32(RLC_CNTL, 0);
2879 }
2880
2881 static void si_rlc_start(struct radeon_device *rdev)
2882 {
2883         WREG32(RLC_CNTL, RLC_ENABLE);
2884 }
2885
2886 static int si_rlc_resume(struct radeon_device *rdev)
2887 {
2888         u32 i;
2889         const __be32 *fw_data;
2890
2891         if (!rdev->rlc_fw)
2892                 return -EINVAL;
2893
2894         si_rlc_stop(rdev);
2895
2896         WREG32(RLC_RL_BASE, 0);
2897         WREG32(RLC_RL_SIZE, 0);
2898         WREG32(RLC_LB_CNTL, 0);
2899         WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2900         WREG32(RLC_LB_CNTR_INIT, 0);
2901
2902         WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2903         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2904
2905         WREG32(RLC_MC_CNTL, 0);
2906         WREG32(RLC_UCODE_CNTL, 0);
2907
2908         fw_data = (const __be32 *)rdev->rlc_fw->data;
2909         for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
2910                 WREG32(RLC_UCODE_ADDR, i);
2911                 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2912         }
2913         WREG32(RLC_UCODE_ADDR, 0);
2914
2915         si_rlc_start(rdev);
2916
2917         return 0;
2918 }
2919
2920 static void si_enable_interrupts(struct radeon_device *rdev)
2921 {
2922         u32 ih_cntl = RREG32(IH_CNTL);
2923         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2924
2925         ih_cntl |= ENABLE_INTR;
2926         ih_rb_cntl |= IH_RB_ENABLE;
2927         WREG32(IH_CNTL, ih_cntl);
2928         WREG32(IH_RB_CNTL, ih_rb_cntl);
2929         rdev->ih.enabled = true;
2930 }
2931
2932 static void si_disable_interrupts(struct radeon_device *rdev)
2933 {
2934         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2935         u32 ih_cntl = RREG32(IH_CNTL);
2936
2937         ih_rb_cntl &= ~IH_RB_ENABLE;
2938         ih_cntl &= ~ENABLE_INTR;
2939         WREG32(IH_RB_CNTL, ih_rb_cntl);
2940         WREG32(IH_CNTL, ih_cntl);
2941         /* set rptr, wptr to 0 */
2942         WREG32(IH_RB_RPTR, 0);
2943         WREG32(IH_RB_WPTR, 0);
2944         rdev->ih.enabled = false;
2945         rdev->ih.wptr = 0;
2946         rdev->ih.rptr = 0;
2947 }
2948
2949 static void si_disable_interrupt_state(struct radeon_device *rdev)
2950 {
2951         u32 tmp;
2952
2953         WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2954         WREG32(CP_INT_CNTL_RING1, 0);
2955         WREG32(CP_INT_CNTL_RING2, 0);
2956         WREG32(GRBM_INT_CNTL, 0);
2957         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2958         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2959         if (rdev->num_crtc >= 4) {
2960                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2961                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2962         }
2963         if (rdev->num_crtc >= 6) {
2964                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2965                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2966         }
2967
2968         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2969         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2970         if (rdev->num_crtc >= 4) {
2971                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2972                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2973         }
2974         if (rdev->num_crtc >= 6) {
2975                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2976                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2977         }
2978
2979         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2980
2981         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2982         WREG32(DC_HPD1_INT_CONTROL, tmp);
2983         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2984         WREG32(DC_HPD2_INT_CONTROL, tmp);
2985         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2986         WREG32(DC_HPD3_INT_CONTROL, tmp);
2987         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2988         WREG32(DC_HPD4_INT_CONTROL, tmp);
2989         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2990         WREG32(DC_HPD5_INT_CONTROL, tmp);
2991         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2992         WREG32(DC_HPD6_INT_CONTROL, tmp);
2993
2994 }
2995
2996 static int si_irq_init(struct radeon_device *rdev)
2997 {
2998         int ret = 0;
2999         int rb_bufsz;
3000         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3001
3002         /* allocate ring */
3003         ret = r600_ih_ring_alloc(rdev);
3004         if (ret)
3005                 return ret;
3006
3007         /* disable irqs */
3008         si_disable_interrupts(rdev);
3009
3010         /* init rlc */
3011         ret = si_rlc_resume(rdev);
3012         if (ret) {
3013                 r600_ih_ring_fini(rdev);
3014                 return ret;
3015         }
3016
3017         /* setup interrupt control */
3018         /* set dummy read address to ring address */
3019         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3020         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3021         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3022          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3023          */
3024         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3025         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3026         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3027         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3028
3029         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3030         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3031
3032         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3033                       IH_WPTR_OVERFLOW_CLEAR |
3034                       (rb_bufsz << 1));
3035
3036         if (rdev->wb.enabled)
3037                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3038
3039         /* set the writeback address whether it's enabled or not */
3040         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3041         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3042
3043         WREG32(IH_RB_CNTL, ih_rb_cntl);
3044
3045         /* set rptr, wptr to 0 */
3046         WREG32(IH_RB_RPTR, 0);
3047         WREG32(IH_RB_WPTR, 0);
3048
3049         /* Default settings for IH_CNTL (disabled at first) */
3050         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3051         /* RPTR_REARM only works if msi's are enabled */
3052         if (rdev->msi_enabled)
3053                 ih_cntl |= RPTR_REARM;
3054         WREG32(IH_CNTL, ih_cntl);
3055
3056         /* force the active interrupt state to all disabled */
3057         si_disable_interrupt_state(rdev);
3058
3059         pci_set_master(rdev->pdev);
3060
3061         /* enable irqs */
3062         si_enable_interrupts(rdev);
3063
3064         return ret;
3065 }
3066
3067 int si_irq_set(struct radeon_device *rdev)
3068 {
3069         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3070         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3071         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3072         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3073         u32 grbm_int_cntl = 0;
3074         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3075
3076         if (!rdev->irq.installed) {
3077                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3078                 return -EINVAL;
3079         }
3080         /* don't enable anything if the ih is disabled */
3081         if (!rdev->ih.enabled) {
3082                 si_disable_interrupts(rdev);
3083                 /* force the active interrupt state to all disabled */
3084                 si_disable_interrupt_state(rdev);
3085                 return 0;
3086         }
3087
3088         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3089         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3090         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3091         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3092         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3093         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3094
3095         /* enable CP interrupts on all rings */
3096         if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3097                 DRM_DEBUG("si_irq_set: sw int gfx\n");
3098                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3099         }
3100         if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
3101                 DRM_DEBUG("si_irq_set: sw int cp1\n");
3102                 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3103         }
3104         if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
3105                 DRM_DEBUG("si_irq_set: sw int cp2\n");
3106                 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3107         }
3108         if (rdev->irq.crtc_vblank_int[0] ||
3109             rdev->irq.pflip[0]) {
3110                 DRM_DEBUG("si_irq_set: vblank 0\n");
3111                 crtc1 |= VBLANK_INT_MASK;
3112         }
3113         if (rdev->irq.crtc_vblank_int[1] ||
3114             rdev->irq.pflip[1]) {
3115                 DRM_DEBUG("si_irq_set: vblank 1\n");
3116                 crtc2 |= VBLANK_INT_MASK;
3117         }
3118         if (rdev->irq.crtc_vblank_int[2] ||
3119             rdev->irq.pflip[2]) {
3120                 DRM_DEBUG("si_irq_set: vblank 2\n");
3121                 crtc3 |= VBLANK_INT_MASK;
3122         }
3123         if (rdev->irq.crtc_vblank_int[3] ||
3124             rdev->irq.pflip[3]) {
3125                 DRM_DEBUG("si_irq_set: vblank 3\n");
3126                 crtc4 |= VBLANK_INT_MASK;
3127         }
3128         if (rdev->irq.crtc_vblank_int[4] ||
3129             rdev->irq.pflip[4]) {
3130                 DRM_DEBUG("si_irq_set: vblank 4\n");
3131                 crtc5 |= VBLANK_INT_MASK;
3132         }
3133         if (rdev->irq.crtc_vblank_int[5] ||
3134             rdev->irq.pflip[5]) {
3135                 DRM_DEBUG("si_irq_set: vblank 5\n");
3136                 crtc6 |= VBLANK_INT_MASK;
3137         }
3138         if (rdev->irq.hpd[0]) {
3139                 DRM_DEBUG("si_irq_set: hpd 1\n");
3140                 hpd1 |= DC_HPDx_INT_EN;
3141         }
3142         if (rdev->irq.hpd[1]) {
3143                 DRM_DEBUG("si_irq_set: hpd 2\n");
3144                 hpd2 |= DC_HPDx_INT_EN;
3145         }
3146         if (rdev->irq.hpd[2]) {
3147                 DRM_DEBUG("si_irq_set: hpd 3\n");
3148                 hpd3 |= DC_HPDx_INT_EN;
3149         }
3150         if (rdev->irq.hpd[3]) {
3151                 DRM_DEBUG("si_irq_set: hpd 4\n");
3152                 hpd4 |= DC_HPDx_INT_EN;
3153         }
3154         if (rdev->irq.hpd[4]) {
3155                 DRM_DEBUG("si_irq_set: hpd 5\n");
3156                 hpd5 |= DC_HPDx_INT_EN;
3157         }
3158         if (rdev->irq.hpd[5]) {
3159                 DRM_DEBUG("si_irq_set: hpd 6\n");
3160                 hpd6 |= DC_HPDx_INT_EN;
3161         }
3162         if (rdev->irq.gui_idle) {
3163                 DRM_DEBUG("gui idle\n");
3164                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3165         }
3166
3167         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3168         WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3169         WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3170
3171         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3172
3173         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3174         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3175         if (rdev->num_crtc >= 4) {
3176                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3177                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3178         }
3179         if (rdev->num_crtc >= 6) {
3180                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3181                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3182         }
3183
3184         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3185         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3186         if (rdev->num_crtc >= 4) {
3187                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3188                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3189         }
3190         if (rdev->num_crtc >= 6) {
3191                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3192                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3193         }
3194
3195         WREG32(DC_HPD1_INT_CONTROL, hpd1);
3196         WREG32(DC_HPD2_INT_CONTROL, hpd2);
3197         WREG32(DC_HPD3_INT_CONTROL, hpd3);
3198         WREG32(DC_HPD4_INT_CONTROL, hpd4);
3199         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3200         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3201
3202         return 0;
3203 }
3204
3205 static inline void si_irq_ack(struct radeon_device *rdev)
3206 {
3207         u32 tmp;
3208
3209         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3210         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3211         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3212         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3213         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3214         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3215         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3216         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3217         if (rdev->num_crtc >= 4) {
3218                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3219                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3220         }
3221         if (rdev->num_crtc >= 6) {
3222                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3223                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3224         }
3225
3226         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3227                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3228         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3229                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3230         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3231                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3232         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3233                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3234         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3235                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3236         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3237                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3238
3239         if (rdev->num_crtc >= 4) {
3240                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3241                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3242                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3243                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3244                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3245                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3246                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3247                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3248                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3249                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3250                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3251                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3252         }
3253
3254         if (rdev->num_crtc >= 6) {
3255                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3256                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3257                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3258                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3259                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3260                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3261                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3262                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3263                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3264                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3265                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3266                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3267         }
3268
3269         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3270                 tmp = RREG32(DC_HPD1_INT_CONTROL);
3271                 tmp |= DC_HPDx_INT_ACK;
3272                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3273         }
3274         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3275                 tmp = RREG32(DC_HPD2_INT_CONTROL);
3276                 tmp |= DC_HPDx_INT_ACK;
3277                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3278         }
3279         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3280                 tmp = RREG32(DC_HPD3_INT_CONTROL);
3281                 tmp |= DC_HPDx_INT_ACK;
3282                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3283         }
3284         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3285                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3286                 tmp |= DC_HPDx_INT_ACK;
3287                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3288         }
3289         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3290                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3291                 tmp |= DC_HPDx_INT_ACK;
3292                 WREG32(DC_HPD5_INT_CONTROL, tmp);
3293         }
3294         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3295                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3296                 tmp |= DC_HPDx_INT_ACK;
3297                 WREG32(DC_HPD6_INT_CONTROL, tmp);
3298         }
3299 }
3300
3301 static void si_irq_disable(struct radeon_device *rdev)
3302 {
3303         si_disable_interrupts(rdev);
3304         /* Wait and acknowledge irq */
3305         mdelay(1);
3306         si_irq_ack(rdev);
3307         si_disable_interrupt_state(rdev);
3308 }
3309
3310 static void si_irq_suspend(struct radeon_device *rdev)
3311 {
3312         si_irq_disable(rdev);
3313         si_rlc_stop(rdev);
3314 }
3315
3316 static void si_irq_fini(struct radeon_device *rdev)
3317 {
3318         si_irq_suspend(rdev);
3319         r600_ih_ring_fini(rdev);
3320 }
3321
3322 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3323 {
3324         u32 wptr, tmp;
3325
3326         if (rdev->wb.enabled)
3327                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3328         else
3329                 wptr = RREG32(IH_RB_WPTR);
3330
3331         if (wptr & RB_OVERFLOW) {
3332                 /* When a ring buffer overflow happen start parsing interrupt
3333                  * from the last not overwritten vector (wptr + 16). Hopefully
3334                  * this should allow us to catchup.
3335                  */
3336                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3337                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3338                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3339                 tmp = RREG32(IH_RB_CNTL);
3340                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3341                 WREG32(IH_RB_CNTL, tmp);
3342         }
3343         return (wptr & rdev->ih.ptr_mask);
3344 }
3345
3346 /*        SI IV Ring
3347  * Each IV ring entry is 128 bits:
3348  * [7:0]    - interrupt source id
3349  * [31:8]   - reserved
3350  * [59:32]  - interrupt source data
3351  * [63:60]  - reserved
3352  * [71:64]  - RINGID
3353  * [79:72]  - VMID
3354  * [127:80] - reserved
3355  */
3356 int si_irq_process(struct radeon_device *rdev)
3357 {
3358         u32 wptr;
3359         u32 rptr;
3360         u32 src_id, src_data, ring_id;
3361         u32 ring_index;
3362         unsigned long flags;
3363         bool queue_hotplug = false;
3364
3365         if (!rdev->ih.enabled || rdev->shutdown)
3366                 return IRQ_NONE;
3367
3368         wptr = si_get_ih_wptr(rdev);
3369         rptr = rdev->ih.rptr;
3370         DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3371
3372         spin_lock_irqsave(&rdev->ih.lock, flags);
3373         if (rptr == wptr) {
3374                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3375                 return IRQ_NONE;
3376         }
3377 restart_ih:
3378         /* Order reading of wptr vs. reading of IH ring data */
3379         rmb();
3380
3381         /* display interrupts */
3382         si_irq_ack(rdev);
3383
3384         rdev->ih.wptr = wptr;
3385         while (rptr != wptr) {
3386                 /* wptr/rptr are in bytes! */
3387                 ring_index = rptr / 4;
3388                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3389                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3390                 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3391
3392                 switch (src_id) {
3393                 case 1: /* D1 vblank/vline */
3394                         switch (src_data) {
3395                         case 0: /* D1 vblank */
3396                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3397                                         if (rdev->irq.crtc_vblank_int[0]) {
3398                                                 drm_handle_vblank(rdev->ddev, 0);
3399                                                 rdev->pm.vblank_sync = true;
3400                                                 wake_up(&rdev->irq.vblank_queue);
3401                                         }
3402                                         if (rdev->irq.pflip[0])
3403                                                 radeon_crtc_handle_flip(rdev, 0);
3404                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3405                                         DRM_DEBUG("IH: D1 vblank\n");
3406                                 }
3407                                 break;
3408                         case 1: /* D1 vline */
3409                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3410                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3411                                         DRM_DEBUG("IH: D1 vline\n");
3412                                 }
3413                                 break;
3414                         default:
3415                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3416                                 break;
3417                         }
3418                         break;
3419                 case 2: /* D2 vblank/vline */
3420                         switch (src_data) {
3421                         case 0: /* D2 vblank */
3422                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3423                                         if (rdev->irq.crtc_vblank_int[1]) {
3424                                                 drm_handle_vblank(rdev->ddev, 1);
3425                                                 rdev->pm.vblank_sync = true;
3426                                                 wake_up(&rdev->irq.vblank_queue);
3427                                         }
3428                                         if (rdev->irq.pflip[1])
3429                                                 radeon_crtc_handle_flip(rdev, 1);
3430                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3431                                         DRM_DEBUG("IH: D2 vblank\n");
3432                                 }
3433                                 break;
3434                         case 1: /* D2 vline */
3435                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3436                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3437                                         DRM_DEBUG("IH: D2 vline\n");
3438                                 }
3439                                 break;
3440                         default:
3441                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3442                                 break;
3443                         }
3444                         break;
3445                 case 3: /* D3 vblank/vline */
3446                         switch (src_data) {
3447                         case 0: /* D3 vblank */
3448                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3449                                         if (rdev->irq.crtc_vblank_int[2]) {
3450                                                 drm_handle_vblank(rdev->ddev, 2);
3451                                                 rdev->pm.vblank_sync = true;
3452                                                 wake_up(&rdev->irq.vblank_queue);
3453                                         }
3454                                         if (rdev->irq.pflip[2])
3455                                                 radeon_crtc_handle_flip(rdev, 2);
3456                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3457                                         DRM_DEBUG("IH: D3 vblank\n");
3458                                 }
3459                                 break;
3460                         case 1: /* D3 vline */
3461                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3462                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3463                                         DRM_DEBUG("IH: D3 vline\n");
3464                                 }
3465                                 break;
3466                         default:
3467                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3468                                 break;
3469                         }
3470                         break;
3471                 case 4: /* D4 vblank/vline */
3472                         switch (src_data) {
3473                         case 0: /* D4 vblank */
3474                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3475                                         if (rdev->irq.crtc_vblank_int[3]) {
3476                                                 drm_handle_vblank(rdev->ddev, 3);
3477                                                 rdev->pm.vblank_sync = true;
3478                                                 wake_up(&rdev->irq.vblank_queue);
3479                                         }
3480                                         if (rdev->irq.pflip[3])
3481                                                 radeon_crtc_handle_flip(rdev, 3);
3482                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3483                                         DRM_DEBUG("IH: D4 vblank\n");
3484                                 }
3485                                 break;
3486                         case 1: /* D4 vline */
3487                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3488                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3489                                         DRM_DEBUG("IH: D4 vline\n");
3490                                 }
3491                                 break;
3492                         default:
3493                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3494                                 break;
3495                         }
3496                         break;
3497                 case 5: /* D5 vblank/vline */
3498                         switch (src_data) {
3499                         case 0: /* D5 vblank */
3500                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3501                                         if (rdev->irq.crtc_vblank_int[4]) {
3502                                                 drm_handle_vblank(rdev->ddev, 4);
3503                                                 rdev->pm.vblank_sync = true;
3504                                                 wake_up(&rdev->irq.vblank_queue);
3505                                         }
3506                                         if (rdev->irq.pflip[4])
3507                                                 radeon_crtc_handle_flip(rdev, 4);
3508                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3509                                         DRM_DEBUG("IH: D5 vblank\n");
3510                                 }
3511                                 break;
3512                         case 1: /* D5 vline */
3513                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3514                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3515                                         DRM_DEBUG("IH: D5 vline\n");
3516                                 }
3517                                 break;
3518                         default:
3519                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3520                                 break;
3521                         }
3522                         break;
3523                 case 6: /* D6 vblank/vline */
3524                         switch (src_data) {
3525                         case 0: /* D6 vblank */
3526                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3527                                         if (rdev->irq.crtc_vblank_int[5]) {
3528                                                 drm_handle_vblank(rdev->ddev, 5);
3529                                                 rdev->pm.vblank_sync = true;
3530                                                 wake_up(&rdev->irq.vblank_queue);
3531                                         }
3532                                         if (rdev->irq.pflip[5])
3533                                                 radeon_crtc_handle_flip(rdev, 5);
3534                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3535                                         DRM_DEBUG("IH: D6 vblank\n");
3536                                 }
3537                                 break;
3538                         case 1: /* D6 vline */
3539                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3540                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3541                                         DRM_DEBUG("IH: D6 vline\n");
3542                                 }
3543                                 break;
3544                         default:
3545                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3546                                 break;
3547                         }
3548                         break;
3549                 case 42: /* HPD hotplug */
3550                         switch (src_data) {
3551                         case 0:
3552                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3553                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3554                                         queue_hotplug = true;
3555                                         DRM_DEBUG("IH: HPD1\n");
3556                                 }
3557                                 break;
3558                         case 1:
3559                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3560                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3561                                         queue_hotplug = true;
3562                                         DRM_DEBUG("IH: HPD2\n");
3563                                 }
3564                                 break;
3565                         case 2:
3566                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3567                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3568                                         queue_hotplug = true;
3569                                         DRM_DEBUG("IH: HPD3\n");
3570                                 }
3571                                 break;
3572                         case 3:
3573                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3574                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3575                                         queue_hotplug = true;
3576                                         DRM_DEBUG("IH: HPD4\n");
3577                                 }
3578                                 break;
3579                         case 4:
3580                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3581                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3582                                         queue_hotplug = true;
3583                                         DRM_DEBUG("IH: HPD5\n");
3584                                 }
3585                                 break;
3586                         case 5:
3587                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3588                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3589                                         queue_hotplug = true;
3590                                         DRM_DEBUG("IH: HPD6\n");
3591                                 }
3592                                 break;
3593                         default:
3594                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3595                                 break;
3596                         }
3597                         break;
3598                 case 176: /* RINGID0 CP_INT */
3599                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3600                         break;
3601                 case 177: /* RINGID1 CP_INT */
3602                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3603                         break;
3604                 case 178: /* RINGID2 CP_INT */
3605                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3606                         break;
3607                 case 181: /* CP EOP event */
3608                         DRM_DEBUG("IH: CP EOP\n");
3609                         switch (ring_id) {
3610                         case 0:
3611                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3612                                 break;
3613                         case 1:
3614                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3615                                 break;
3616                         case 2:
3617                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3618                                 break;
3619                         }
3620                         break;
3621                 case 233: /* GUI IDLE */
3622                         DRM_DEBUG("IH: GUI idle\n");
3623                         rdev->pm.gui_idle = true;
3624                         wake_up(&rdev->irq.idle_queue);
3625                         break;
3626                 default:
3627                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3628                         break;
3629                 }
3630
3631                 /* wptr/rptr are in bytes! */
3632                 rptr += 16;
3633                 rptr &= rdev->ih.ptr_mask;
3634         }
3635         /* make sure wptr hasn't changed while processing */
3636         wptr = si_get_ih_wptr(rdev);
3637         if (wptr != rdev->ih.wptr)
3638                 goto restart_ih;
3639         if (queue_hotplug)
3640                 schedule_work(&rdev->hotplug_work);
3641         rdev->ih.rptr = rptr;
3642         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3643         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3644         return IRQ_HANDLED;
3645 }
3646
3647 /*
3648  * startup/shutdown callbacks
3649  */
3650 static int si_startup(struct radeon_device *rdev)
3651 {
3652         struct radeon_ring *ring;
3653         int r;
3654
3655         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
3656             !rdev->rlc_fw || !rdev->mc_fw) {
3657                 r = si_init_microcode(rdev);
3658                 if (r) {
3659                         DRM_ERROR("Failed to load firmware!\n");
3660                         return r;
3661                 }
3662         }
3663
3664         r = si_mc_load_microcode(rdev);
3665         if (r) {
3666                 DRM_ERROR("Failed to load MC firmware!\n");
3667                 return r;
3668         }
3669
3670         r = r600_vram_scratch_init(rdev);
3671         if (r)
3672                 return r;
3673
3674         si_mc_program(rdev);
3675         r = si_pcie_gart_enable(rdev);
3676         if (r)
3677                 return r;
3678         si_gpu_init(rdev);
3679
3680 #if 0
3681         r = evergreen_blit_init(rdev);
3682         if (r) {
3683                 r600_blit_fini(rdev);
3684                 rdev->asic->copy = NULL;
3685                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3686         }
3687 #endif
3688         /* allocate rlc buffers */
3689         r = si_rlc_init(rdev);
3690         if (r) {
3691                 DRM_ERROR("Failed to init rlc BOs!\n");
3692                 return r;
3693         }
3694
3695         /* allocate wb buffer */
3696         r = radeon_wb_init(rdev);
3697         if (r)
3698                 return r;
3699
3700         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3701         if (r) {
3702                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3703                 return r;
3704         }
3705
3706         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3707         if (r) {
3708                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3709                 return r;
3710         }
3711
3712         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3713         if (r) {
3714                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3715                 return r;
3716         }
3717
3718         /* Enable IRQ */
3719         r = si_irq_init(rdev);
3720         if (r) {
3721                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3722                 radeon_irq_kms_fini(rdev);
3723                 return r;
3724         }
3725         si_irq_set(rdev);
3726
3727         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3728         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3729                              CP_RB0_RPTR, CP_RB0_WPTR,
3730                              0, 0xfffff, RADEON_CP_PACKET2);
3731         if (r)
3732                 return r;
3733
3734         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3735         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
3736                              CP_RB1_RPTR, CP_RB1_WPTR,
3737                              0, 0xfffff, RADEON_CP_PACKET2);
3738         if (r)
3739                 return r;
3740
3741         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3742         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
3743                              CP_RB2_RPTR, CP_RB2_WPTR,
3744                              0, 0xfffff, RADEON_CP_PACKET2);
3745         if (r)
3746                 return r;
3747
3748         r = si_cp_load_microcode(rdev);
3749         if (r)
3750                 return r;
3751         r = si_cp_resume(rdev);
3752         if (r)
3753                 return r;
3754
3755         r = radeon_ib_pool_start(rdev);
3756         if (r)
3757                 return r;
3758
3759         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3760         if (r) {
3761                 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r);
3762                 rdev->accel_working = false;
3763                 return r;
3764         }
3765
3766         r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3767         if (r) {
3768                 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r);
3769                 rdev->accel_working = false;
3770                 return r;
3771         }
3772
3773         r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3774         if (r) {
3775                 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r);
3776                 rdev->accel_working = false;
3777                 return r;
3778         }
3779
3780         r = radeon_vm_manager_start(rdev);
3781         if (r)
3782                 return r;
3783
3784         return 0;
3785 }
3786
3787 int si_resume(struct radeon_device *rdev)
3788 {
3789         int r;
3790
3791         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3792          * posting will perform necessary task to bring back GPU into good
3793          * shape.
3794          */
3795         /* post card */
3796         atom_asic_init(rdev->mode_info.atom_context);
3797
3798         rdev->accel_working = true;
3799         r = si_startup(rdev);
3800         if (r) {
3801                 DRM_ERROR("si startup failed on resume\n");
3802                 rdev->accel_working = false;
3803                 return r;
3804         }
3805
3806         return r;
3807
3808 }
3809
3810 int si_suspend(struct radeon_device *rdev)
3811 {
3812         /* FIXME: we should wait for ring to be empty */
3813         radeon_ib_pool_suspend(rdev);
3814         radeon_vm_manager_suspend(rdev);
3815 #if 0
3816         r600_blit_suspend(rdev);
3817 #endif
3818         si_cp_enable(rdev, false);
3819         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3820         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3821         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3822         si_irq_suspend(rdev);
3823         radeon_wb_disable(rdev);
3824         si_pcie_gart_disable(rdev);
3825         return 0;
3826 }
3827
3828 /* Plan is to move initialization in that function and use
3829  * helper function so that radeon_device_init pretty much
3830  * do nothing more than calling asic specific function. This
3831  * should also allow to remove a bunch of callback function
3832  * like vram_info.
3833  */
3834 int si_init(struct radeon_device *rdev)
3835 {
3836         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3837         int r;
3838
3839         /* Read BIOS */
3840         if (!radeon_get_bios(rdev)) {
3841                 if (ASIC_IS_AVIVO(rdev))
3842                         return -EINVAL;
3843         }
3844         /* Must be an ATOMBIOS */
3845         if (!rdev->is_atom_bios) {
3846                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
3847                 return -EINVAL;
3848         }
3849         r = radeon_atombios_init(rdev);
3850         if (r)
3851                 return r;
3852
3853         /* Post card if necessary */
3854         if (!radeon_card_posted(rdev)) {
3855                 if (!rdev->bios) {
3856                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3857                         return -EINVAL;
3858                 }
3859                 DRM_INFO("GPU not posted. posting now...\n");
3860                 atom_asic_init(rdev->mode_info.atom_context);
3861         }
3862         /* Initialize scratch registers */
3863         si_scratch_init(rdev);
3864         /* Initialize surface registers */
3865         radeon_surface_init(rdev);
3866         /* Initialize clocks */
3867         radeon_get_clock_info(rdev->ddev);
3868
3869         /* Fence driver */
3870         r = radeon_fence_driver_init(rdev);
3871         if (r)
3872                 return r;
3873
3874         /* initialize memory controller */
3875         r = si_mc_init(rdev);
3876         if (r)
3877                 return r;
3878         /* Memory manager */
3879         r = radeon_bo_init(rdev);
3880         if (r)
3881                 return r;
3882
3883         r = radeon_irq_kms_init(rdev);
3884         if (r)
3885                 return r;
3886
3887         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3888         ring->ring_obj = NULL;
3889         r600_ring_init(rdev, ring, 1024 * 1024);
3890
3891         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3892         ring->ring_obj = NULL;
3893         r600_ring_init(rdev, ring, 1024 * 1024);
3894
3895         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3896         ring->ring_obj = NULL;
3897         r600_ring_init(rdev, ring, 1024 * 1024);
3898
3899         rdev->ih.ring_obj = NULL;
3900         r600_ih_ring_init(rdev, 64 * 1024);
3901
3902         r = r600_pcie_gart_init(rdev);
3903         if (r)
3904                 return r;
3905
3906         r = radeon_ib_pool_init(rdev);
3907         rdev->accel_working = true;
3908         if (r) {
3909                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3910                 rdev->accel_working = false;
3911         }
3912         r = radeon_vm_manager_init(rdev);
3913         if (r) {
3914                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
3915         }
3916
3917         r = si_startup(rdev);
3918         if (r) {
3919                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3920                 si_cp_fini(rdev);
3921                 si_irq_fini(rdev);
3922                 si_rlc_fini(rdev);
3923                 radeon_wb_fini(rdev);
3924                 r100_ib_fini(rdev);
3925                 radeon_vm_manager_fini(rdev);
3926                 radeon_irq_kms_fini(rdev);
3927                 si_pcie_gart_fini(rdev);
3928                 rdev->accel_working = false;
3929         }
3930
3931         /* Don't start up if the MC ucode is missing.
3932          * The default clocks and voltages before the MC ucode
3933          * is loaded are not suffient for advanced operations.
3934          */
3935         if (!rdev->mc_fw) {
3936                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3937                 return -EINVAL;
3938         }
3939
3940         return 0;
3941 }
3942
3943 void si_fini(struct radeon_device *rdev)
3944 {
3945 #if 0
3946         r600_blit_fini(rdev);
3947 #endif
3948         si_cp_fini(rdev);
3949         si_irq_fini(rdev);
3950         si_rlc_fini(rdev);
3951         radeon_wb_fini(rdev);
3952         radeon_vm_manager_fini(rdev);
3953         r100_ib_fini(rdev);
3954         radeon_irq_kms_fini(rdev);
3955         si_pcie_gart_fini(rdev);
3956         r600_vram_scratch_fini(rdev);
3957         radeon_gem_fini(rdev);
3958         radeon_fence_driver_fini(rdev);
3959         radeon_bo_fini(rdev);
3960         radeon_atombios_fini(rdev);
3961         kfree(rdev->bios);
3962         rdev->bios = NULL;
3963 }
3964