2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
39 #define SMC_RAM_END 0x20000
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
108 static const struct si_cac_config_reg lcac_tahiti[] =
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
200 static const struct si_cac_config_reg cac_override_tahiti[] =
205 static const struct si_powertune_data powertune_data_tahiti =
236 static const struct si_dte_data dte_data_tahiti =
238 { 1159409, 0, 0, 0, 0 },
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
254 static const struct si_dte_data dte_data_tahiti_le =
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
272 static const struct si_dte_data dte_data_tahiti_pro =
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
290 static const struct si_dte_data dte_data_new_zealand =
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
308 static const struct si_dte_data dte_data_aruba_pro =
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
326 static const struct si_dte_data dte_data_malta =
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
344 struct si_cac_config_reg cac_weights_pitcairn[] =
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
409 static const struct si_cac_config_reg lcac_pitcairn[] =
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
505 static const struct si_powertune_data powertune_data_pitcairn =
536 static const struct si_dte_data dte_data_pitcairn =
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
554 static const struct si_dte_data dte_data_curacao_xt =
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
572 static const struct si_dte_data dte_data_curacao_pro =
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
590 static const struct si_dte_data dte_data_neptune_xt =
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
933 static const struct si_cac_config_reg lcac_cape_verde[] =
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
997 static const struct si_powertune_data powertune_data_cape_verde =
999 ((1 << 16) | 0x6993),
1028 static const struct si_dte_data dte_data_cape_verde =
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1046 static const struct si_dte_data dte_data_venus_xtx =
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1064 static const struct si_dte_data dte_data_venus_xt =
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1082 static const struct si_dte_data dte_data_venus_pro =
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1100 struct si_cac_config_reg cac_weights_oland[] =
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1425 static const struct si_cac_config_reg lcac_oland[] =
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519 static const struct si_cac_config_reg cac_override_oland[] =
1524 static const struct si_powertune_data powertune_data_oland =
1526 ((1 << 16) | 0x6993),
1555 static const struct si_powertune_data powertune_data_mars_pro =
1557 ((1 << 16) | 0x6993),
1586 static const struct si_dte_data dte_data_oland =
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1604 static const struct si_dte_data dte_data_mars_pro =
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1622 static const struct si_dte_data dte_data_sun_xt =
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1706 static const struct si_powertune_data powertune_data_hainan =
1708 ((1 << 16) | 0x6993),
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1850 for (i = 0; i < k; i++) {
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1879 switch (rdev->pdev->device) {
1881 si_pi->dte_data.enable_dte_by_default = true;
1884 si_pi->dte_data = dte_data_new_zealand;
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1948 switch (rdev->pdev->device) {
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2070 ni_pi->enable_sq_ramping = true;
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2101 u32 cac_window_size;
2103 xclk = radeon_get_xclk(rdev);
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2111 wintime = (cac_window_size * 100) / xclk;
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2118 return power_in_watts;
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2125 u32 *near_tdp_limit)
2127 u32 adjustment_delta, max_tdp_limit;
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2143 *near_tdp_limit = 0;
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2169 if (scaling_factor == 0)
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2176 rdev->pm.dpm.tdp_adjustment,
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2210 sizeof(PP_SIslands_PAPMParameters),
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2270 return (u16)pwr_efficiency_ratio;
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2299 u16 pwr_efficiency_ratio;
2301 bool disable_uvd_power_tune;
2304 if (ni_pi->enable_power_containment == false)
2307 if (state->performance_level_count == 0)
2310 if (smc_state->levelCount != state->performance_level_count)
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2329 if (prev_sclk > max_sclk)
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2389 if (state->performance_level_count == 0)
2392 if (smc_state->levelCount != state->performance_level_count)
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2444 if (ni_pi->enable_power_containment) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2450 ni_pi->pc_enabled = false;
2452 ni_pi->pc_enabled = true;
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2459 ni_pi->pc_enabled = false;
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2479 if (si_pi->enable_dte == false)
2482 if (dte_data->k <= 0)
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2491 table_size = dte_data->k;
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2516 dte_tables->Tdep_count = tdep_count;
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2559 if (v0_loadline > 0xFFFFUL)
2562 *min = (u16)v0_loadline;
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2601 si_pi->dyn_powertune_data.cac_leakage,
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2636 si_pi->dyn_powertune_data.cac_leakage,
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2658 u32 load_line_slope, reg;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2662 if (ni_pi->enable_cac == false)
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2752 data = RREG32(config_regs->offset << 2);
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2766 WREG32(config_regs->offset << 2, data);
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2806 if (ni_pi->enable_cac) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2818 ni_pi->cac_enabled = false;
2820 ni_pi->cac_enabled = true;
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2835 ni_pi->cac_enabled = false;
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2857 if (si_pi->spll_table_start == 0)
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2874 fb_div &= ~0x00001FFF;
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2908 ni_pi->enable_power_containment = false;
2915 struct si_dpm_quirk {
2924 /* cards with dpm stability problems */
2925 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2930 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2938 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2941 u16 highest_leakage = 0;
2942 struct si_power_info *si_pi = si_get_pi(rdev);
2945 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2946 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2947 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2950 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2951 return highest_leakage;
2956 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2957 u32 evclk, u32 ecclk, u16 *voltage)
2961 struct radeon_vce_clock_voltage_dependency_table *table =
2962 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2964 if (((evclk == 0) && (ecclk == 0)) ||
2965 (table && (table->count == 0))) {
2970 for (i = 0; i < table->count; i++) {
2971 if ((evclk <= table->entries[i].evclk) &&
2972 (ecclk <= table->entries[i].ecclk)) {
2973 *voltage = table->entries[i].v;
2979 /* if no match return the highest voltage */
2981 *voltage = table->entries[table->count - 1].v;
2983 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2988 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2989 struct radeon_ps *rps)
2991 struct ni_ps *ps = ni_get_ps(rps);
2992 struct radeon_clock_and_voltage_limits *max_limits;
2993 bool disable_mclk_switching = false;
2994 bool disable_sclk_switching = false;
2996 u16 vddc, vddci, min_vce_voltage = 0;
2997 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2998 u32 max_sclk = 0, max_mclk = 0;
3000 struct si_dpm_quirk *p = si_dpm_quirk_list;
3002 /* limit all SI kickers */
3003 if (rdev->family == CHIP_PITCAIRN) {
3004 if ((rdev->pdev->revision == 0x81) ||
3005 (rdev->pdev->device == 0x6810) ||
3006 (rdev->pdev->device == 0x6811) ||
3007 (rdev->pdev->device == 0x6816) ||
3008 (rdev->pdev->device == 0x6817) ||
3009 (rdev->pdev->device == 0x6806))
3011 } else if (rdev->family == CHIP_VERDE) {
3012 if ((rdev->pdev->revision == 0x81) ||
3013 (rdev->pdev->revision == 0x83) ||
3014 (rdev->pdev->revision == 0x87) ||
3015 (rdev->pdev->device == 0x6820) ||
3016 (rdev->pdev->device == 0x6821) ||
3017 (rdev->pdev->device == 0x6822) ||
3018 (rdev->pdev->device == 0x6823) ||
3019 (rdev->pdev->device == 0x682A) ||
3020 (rdev->pdev->device == 0x682B)) {
3024 } else if (rdev->family == CHIP_OLAND) {
3025 if ((rdev->pdev->revision == 0xC7) ||
3026 (rdev->pdev->revision == 0x80) ||
3027 (rdev->pdev->revision == 0x81) ||
3028 (rdev->pdev->revision == 0x83) ||
3029 (rdev->pdev->revision == 0x87) ||
3030 (rdev->pdev->device == 0x6604) ||
3031 (rdev->pdev->device == 0x6605)) {
3035 } else if (rdev->family == CHIP_HAINAN) {
3036 if ((rdev->pdev->revision == 0x81) ||
3037 (rdev->pdev->revision == 0x83) ||
3038 (rdev->pdev->revision == 0xC3) ||
3039 (rdev->pdev->device == 0x6664) ||
3040 (rdev->pdev->device == 0x6665) ||
3041 (rdev->pdev->device == 0x6667)) {
3046 /* Apply dpm quirks */
3047 while (p && p->chip_device != 0) {
3048 if (rdev->pdev->vendor == p->chip_vendor &&
3049 rdev->pdev->device == p->chip_device &&
3050 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3051 rdev->pdev->subsystem_device == p->subsys_device) {
3052 max_sclk = p->max_sclk;
3053 max_mclk = p->max_mclk;
3059 if (rps->vce_active) {
3060 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3061 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3062 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3069 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3070 ni_dpm_vblank_too_short(rdev))
3071 disable_mclk_switching = true;
3073 if (rps->vclk || rps->dclk) {
3074 disable_mclk_switching = true;
3075 disable_sclk_switching = true;
3078 if (rdev->pm.dpm.ac_power)
3079 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3081 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3083 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3084 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3085 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3087 if (rdev->pm.dpm.ac_power == false) {
3088 for (i = 0; i < ps->performance_level_count; i++) {
3089 if (ps->performance_levels[i].mclk > max_limits->mclk)
3090 ps->performance_levels[i].mclk = max_limits->mclk;
3091 if (ps->performance_levels[i].sclk > max_limits->sclk)
3092 ps->performance_levels[i].sclk = max_limits->sclk;
3093 if (ps->performance_levels[i].vddc > max_limits->vddc)
3094 ps->performance_levels[i].vddc = max_limits->vddc;
3095 if (ps->performance_levels[i].vddci > max_limits->vddci)
3096 ps->performance_levels[i].vddci = max_limits->vddci;
3100 /* limit clocks to max supported clocks based on voltage dependency tables */
3101 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3103 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3105 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3108 for (i = 0; i < ps->performance_level_count; i++) {
3109 if (max_sclk_vddc) {
3110 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3111 ps->performance_levels[i].sclk = max_sclk_vddc;
3113 if (max_mclk_vddci) {
3114 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3115 ps->performance_levels[i].mclk = max_mclk_vddci;
3117 if (max_mclk_vddc) {
3118 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3119 ps->performance_levels[i].mclk = max_mclk_vddc;
3122 if (ps->performance_levels[i].mclk > max_mclk)
3123 ps->performance_levels[i].mclk = max_mclk;
3126 if (ps->performance_levels[i].sclk > max_sclk)
3127 ps->performance_levels[i].sclk = max_sclk;
3131 /* XXX validate the min clocks required for display */
3133 if (disable_mclk_switching) {
3134 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3135 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3137 mclk = ps->performance_levels[0].mclk;
3138 vddci = ps->performance_levels[0].vddci;
3141 if (disable_sclk_switching) {
3142 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3143 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3145 sclk = ps->performance_levels[0].sclk;
3146 vddc = ps->performance_levels[0].vddc;
3149 if (rps->vce_active) {
3150 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3151 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3152 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3153 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3156 /* adjusted low state */
3157 ps->performance_levels[0].sclk = sclk;
3158 ps->performance_levels[0].mclk = mclk;
3159 ps->performance_levels[0].vddc = vddc;
3160 ps->performance_levels[0].vddci = vddci;
3162 if (disable_sclk_switching) {
3163 sclk = ps->performance_levels[0].sclk;
3164 for (i = 1; i < ps->performance_level_count; i++) {
3165 if (sclk < ps->performance_levels[i].sclk)
3166 sclk = ps->performance_levels[i].sclk;
3168 for (i = 0; i < ps->performance_level_count; i++) {
3169 ps->performance_levels[i].sclk = sclk;
3170 ps->performance_levels[i].vddc = vddc;
3173 for (i = 1; i < ps->performance_level_count; i++) {
3174 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3175 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3176 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3177 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3181 if (disable_mclk_switching) {
3182 mclk = ps->performance_levels[0].mclk;
3183 for (i = 1; i < ps->performance_level_count; i++) {
3184 if (mclk < ps->performance_levels[i].mclk)
3185 mclk = ps->performance_levels[i].mclk;
3187 for (i = 0; i < ps->performance_level_count; i++) {
3188 ps->performance_levels[i].mclk = mclk;
3189 ps->performance_levels[i].vddci = vddci;
3192 for (i = 1; i < ps->performance_level_count; i++) {
3193 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3194 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3195 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3196 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3200 for (i = 0; i < ps->performance_level_count; i++)
3201 btc_adjust_clock_combinations(rdev, max_limits,
3202 &ps->performance_levels[i]);
3204 for (i = 0; i < ps->performance_level_count; i++) {
3205 if (ps->performance_levels[i].vddc < min_vce_voltage)
3206 ps->performance_levels[i].vddc = min_vce_voltage;
3207 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3208 ps->performance_levels[i].sclk,
3209 max_limits->vddc, &ps->performance_levels[i].vddc);
3210 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3211 ps->performance_levels[i].mclk,
3212 max_limits->vddci, &ps->performance_levels[i].vddci);
3213 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3214 ps->performance_levels[i].mclk,
3215 max_limits->vddc, &ps->performance_levels[i].vddc);
3216 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3217 rdev->clock.current_dispclk,
3218 max_limits->vddc, &ps->performance_levels[i].vddc);
3221 for (i = 0; i < ps->performance_level_count; i++) {
3222 btc_apply_voltage_delta_rules(rdev,
3223 max_limits->vddc, max_limits->vddci,
3224 &ps->performance_levels[i].vddc,
3225 &ps->performance_levels[i].vddci);
3228 ps->dc_compatible = true;
3229 for (i = 0; i < ps->performance_level_count; i++) {
3230 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3231 ps->dc_compatible = false;
3236 static int si_read_smc_soft_register(struct radeon_device *rdev,
3237 u16 reg_offset, u32 *value)
3239 struct si_power_info *si_pi = si_get_pi(rdev);
3241 return si_read_smc_sram_dword(rdev,
3242 si_pi->soft_regs_start + reg_offset, value,
3247 static int si_write_smc_soft_register(struct radeon_device *rdev,
3248 u16 reg_offset, u32 value)
3250 struct si_power_info *si_pi = si_get_pi(rdev);
3252 return si_write_smc_sram_dword(rdev,
3253 si_pi->soft_regs_start + reg_offset,
3254 value, si_pi->sram_end);
3257 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3260 u32 tmp, width, row, column, bank, density;
3261 bool is_memory_gddr5, is_special;
3263 tmp = RREG32(MC_SEQ_MISC0);
3264 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3265 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3266 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3268 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3269 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3271 tmp = RREG32(MC_ARB_RAMCFG);
3272 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3273 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3274 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3276 density = (1 << (row + column - 20 + bank)) * width;
3278 if ((rdev->pdev->device == 0x6819) &&
3279 is_memory_gddr5 && is_special && (density == 0x400))
3285 static void si_get_leakage_vddc(struct radeon_device *rdev)
3287 struct si_power_info *si_pi = si_get_pi(rdev);
3288 u16 vddc, count = 0;
3291 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3292 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3294 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3295 si_pi->leakage_voltage.entries[count].voltage = vddc;
3296 si_pi->leakage_voltage.entries[count].leakage_index =
3297 SISLANDS_LEAKAGE_INDEX0 + i;
3301 si_pi->leakage_voltage.count = count;
3304 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3305 u32 index, u16 *leakage_voltage)
3307 struct si_power_info *si_pi = si_get_pi(rdev);
3310 if (leakage_voltage == NULL)
3313 if ((index & 0xff00) != 0xff00)
3316 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3319 if (index < SISLANDS_LEAKAGE_INDEX0)
3322 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3323 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3324 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3331 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3333 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3334 bool want_thermal_protection;
3335 enum radeon_dpm_event_src dpm_event_src;
3340 want_thermal_protection = false;
3342 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3343 want_thermal_protection = true;
3344 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3346 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3347 want_thermal_protection = true;
3348 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3350 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3351 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3352 want_thermal_protection = true;
3353 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3357 if (want_thermal_protection) {
3358 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3359 if (pi->thermal_protection)
3360 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3362 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3366 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3367 enum radeon_dpm_auto_throttle_src source,
3370 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3373 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3374 pi->active_auto_throttle_sources |= 1 << source;
3375 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3378 if (pi->active_auto_throttle_sources & (1 << source)) {
3379 pi->active_auto_throttle_sources &= ~(1 << source);
3380 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3385 static void si_start_dpm(struct radeon_device *rdev)
3387 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3390 static void si_stop_dpm(struct radeon_device *rdev)
3392 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3395 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3398 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3400 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3405 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3410 if (thermal_level == 0) {
3411 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3412 if (ret == PPSMC_Result_OK)
3420 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3422 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3427 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3430 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3437 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3438 PPSMC_Msg msg, u32 parameter)
3440 WREG32(SMC_SCRATCH0, parameter);
3441 return si_send_msg_to_smc(rdev, msg);
3444 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3446 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3449 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3453 int si_dpm_force_performance_level(struct radeon_device *rdev,
3454 enum radeon_dpm_forced_level level)
3456 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3457 struct ni_ps *ps = ni_get_ps(rps);
3458 u32 levels = ps->performance_level_count;
3460 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3461 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3464 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3466 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3467 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3470 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3472 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3473 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3476 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3480 rdev->pm.dpm.forced_level = level;
3486 static int si_set_boot_state(struct radeon_device *rdev)
3488 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3493 static int si_set_sw_state(struct radeon_device *rdev)
3495 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3499 static int si_halt_smc(struct radeon_device *rdev)
3501 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3504 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3508 static int si_resume_smc(struct radeon_device *rdev)
3510 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3513 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3517 static void si_dpm_start_smc(struct radeon_device *rdev)
3519 si_program_jump_on_start(rdev);
3521 si_start_smc_clock(rdev);
3524 static void si_dpm_stop_smc(struct radeon_device *rdev)
3527 si_stop_smc_clock(rdev);
3530 static int si_process_firmware_header(struct radeon_device *rdev)
3532 struct si_power_info *si_pi = si_get_pi(rdev);
3536 ret = si_read_smc_sram_dword(rdev,
3537 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3538 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3539 &tmp, si_pi->sram_end);
3543 si_pi->state_table_start = tmp;
3545 ret = si_read_smc_sram_dword(rdev,
3546 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3547 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3548 &tmp, si_pi->sram_end);
3552 si_pi->soft_regs_start = tmp;
3554 ret = si_read_smc_sram_dword(rdev,
3555 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3556 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3557 &tmp, si_pi->sram_end);
3561 si_pi->mc_reg_table_start = tmp;
3563 ret = si_read_smc_sram_dword(rdev,
3564 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3565 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3566 &tmp, si_pi->sram_end);
3570 si_pi->fan_table_start = tmp;
3572 ret = si_read_smc_sram_dword(rdev,
3573 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3574 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3575 &tmp, si_pi->sram_end);
3579 si_pi->arb_table_start = tmp;
3581 ret = si_read_smc_sram_dword(rdev,
3582 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3583 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3584 &tmp, si_pi->sram_end);
3588 si_pi->cac_table_start = tmp;
3590 ret = si_read_smc_sram_dword(rdev,
3591 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3592 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3593 &tmp, si_pi->sram_end);
3597 si_pi->dte_table_start = tmp;
3599 ret = si_read_smc_sram_dword(rdev,
3600 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3601 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3602 &tmp, si_pi->sram_end);
3606 si_pi->spll_table_start = tmp;
3608 ret = si_read_smc_sram_dword(rdev,
3609 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3610 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3611 &tmp, si_pi->sram_end);
3615 si_pi->papm_cfg_table_start = tmp;
3620 static void si_read_clock_registers(struct radeon_device *rdev)
3622 struct si_power_info *si_pi = si_get_pi(rdev);
3624 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3625 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3626 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3627 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3628 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3629 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3630 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3631 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3632 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3633 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3634 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3635 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3636 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3637 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3638 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3641 static void si_enable_thermal_protection(struct radeon_device *rdev,
3645 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3647 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3650 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3652 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3656 static int si_enter_ulp_state(struct radeon_device *rdev)
3658 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3665 static int si_exit_ulp_state(struct radeon_device *rdev)
3669 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3673 for (i = 0; i < rdev->usec_timeout; i++) {
3674 if (RREG32(SMC_RESP_0) == 1)
3683 static int si_notify_smc_display_change(struct radeon_device *rdev,
3686 PPSMC_Msg msg = has_display ?
3687 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3689 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3693 static void si_program_response_times(struct radeon_device *rdev)
3695 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3696 u32 vddc_dly, acpi_dly, vbi_dly;
3697 u32 reference_clock;
3699 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3701 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3702 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3704 if (voltage_response_time == 0)
3705 voltage_response_time = 1000;
3707 acpi_delay_time = 15000;
3708 vbi_time_out = 100000;
3710 reference_clock = radeon_get_xclk(rdev);
3712 vddc_dly = (voltage_response_time * reference_clock) / 100;
3713 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3714 vbi_dly = (vbi_time_out * reference_clock) / 100;
3716 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3717 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3718 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3719 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3722 static void si_program_ds_registers(struct radeon_device *rdev)
3724 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3725 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3727 if (eg_pi->sclk_deep_sleep) {
3728 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3729 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3730 ~AUTOSCALE_ON_SS_CLEAR);
3734 static void si_program_display_gap(struct radeon_device *rdev)
3739 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3740 if (rdev->pm.dpm.new_active_crtc_count > 0)
3741 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3743 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3745 if (rdev->pm.dpm.new_active_crtc_count > 1)
3746 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3748 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3750 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3752 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3753 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3755 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3756 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3757 /* find the first active crtc */
3758 for (i = 0; i < rdev->num_crtc; i++) {
3759 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3762 if (i == rdev->num_crtc)
3767 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3768 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3769 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3772 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3773 * This can be a problem on PowerXpress systems or if you want to use the card
3774 * for offscreen rendering or compute if there are no crtcs enabled.
3776 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3779 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3781 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3785 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3787 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3788 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3792 static void si_setup_bsp(struct radeon_device *rdev)
3794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3795 u32 xclk = radeon_get_xclk(rdev);
3797 r600_calculate_u_and_p(pi->asi,
3803 r600_calculate_u_and_p(pi->pasi,
3810 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3811 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3813 WREG32(CG_BSP, pi->dsp);
3816 static void si_program_git(struct radeon_device *rdev)
3818 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3821 static void si_program_tp(struct radeon_device *rdev)
3824 enum r600_td td = R600_TD_DFLT;
3826 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3827 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3829 if (td == R600_TD_AUTO)
3830 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3832 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3834 if (td == R600_TD_UP)
3835 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3837 if (td == R600_TD_DOWN)
3838 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3841 static void si_program_tpp(struct radeon_device *rdev)
3843 WREG32(CG_TPC, R600_TPC_DFLT);
3846 static void si_program_sstp(struct radeon_device *rdev)
3848 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3851 static void si_enable_display_gap(struct radeon_device *rdev)
3853 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3855 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3856 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3857 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3859 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3860 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3861 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3862 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3865 static void si_program_vc(struct radeon_device *rdev)
3867 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3869 WREG32(CG_FTV, pi->vrc);
3872 static void si_clear_vc(struct radeon_device *rdev)
3877 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3881 if (memory_clock < 10000)
3883 else if (memory_clock >= 80000)
3884 mc_para_index = 0x0f;
3886 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3887 return mc_para_index;
3890 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3895 if (memory_clock < 12500)
3896 mc_para_index = 0x00;
3897 else if (memory_clock > 47500)
3898 mc_para_index = 0x0f;
3900 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3902 if (memory_clock < 65000)
3903 mc_para_index = 0x00;
3904 else if (memory_clock > 135000)
3905 mc_para_index = 0x0f;
3907 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3909 return mc_para_index;
3912 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3914 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3915 bool strobe_mode = false;
3918 if (mclk <= pi->mclk_strobe_mode_threshold)
3922 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3924 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3927 result |= SISLANDS_SMC_STROBE_ENABLE;
3932 static int si_upload_firmware(struct radeon_device *rdev)
3934 struct si_power_info *si_pi = si_get_pi(rdev);
3938 si_stop_smc_clock(rdev);
3940 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3945 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3946 const struct atom_voltage_table *table,
3947 const struct radeon_phase_shedding_limits_table *limits)
3949 u32 data, num_bits, num_levels;
3951 if ((table == NULL) || (limits == NULL))
3954 data = table->mask_low;
3956 num_bits = hweight32(data);
3961 num_levels = (1 << num_bits);
3963 if (table->count != num_levels)
3966 if (limits->count != (num_levels - 1))
3972 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3973 u32 max_voltage_steps,
3974 struct atom_voltage_table *voltage_table)
3976 unsigned int i, diff;
3978 if (voltage_table->count <= max_voltage_steps)
3981 diff = voltage_table->count - max_voltage_steps;
3983 for (i= 0; i < max_voltage_steps; i++)
3984 voltage_table->entries[i] = voltage_table->entries[i + diff];
3986 voltage_table->count = max_voltage_steps;
3989 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3990 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3991 struct atom_voltage_table *voltage_table)
3995 if (voltage_dependency_table == NULL)
3998 voltage_table->mask_low = 0;
3999 voltage_table->phase_delay = 0;
4001 voltage_table->count = voltage_dependency_table->count;
4002 for (i = 0; i < voltage_table->count; i++) {
4003 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4004 voltage_table->entries[i].smio_low = 0;
4010 static int si_construct_voltage_tables(struct radeon_device *rdev)
4012 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4013 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4014 struct si_power_info *si_pi = si_get_pi(rdev);
4017 if (pi->voltage_control) {
4018 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4019 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4023 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4024 si_trim_voltage_table_to_fit_state_table(rdev,
4025 SISLANDS_MAX_NO_VREG_STEPS,
4026 &eg_pi->vddc_voltage_table);
4027 } else if (si_pi->voltage_control_svi2) {
4028 ret = si_get_svi2_voltage_table(rdev,
4029 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4030 &eg_pi->vddc_voltage_table);
4037 if (eg_pi->vddci_control) {
4038 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4039 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4043 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4044 si_trim_voltage_table_to_fit_state_table(rdev,
4045 SISLANDS_MAX_NO_VREG_STEPS,
4046 &eg_pi->vddci_voltage_table);
4048 if (si_pi->vddci_control_svi2) {
4049 ret = si_get_svi2_voltage_table(rdev,
4050 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4051 &eg_pi->vddci_voltage_table);
4056 if (pi->mvdd_control) {
4057 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4058 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4061 pi->mvdd_control = false;
4065 if (si_pi->mvdd_voltage_table.count == 0) {
4066 pi->mvdd_control = false;
4070 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4071 si_trim_voltage_table_to_fit_state_table(rdev,
4072 SISLANDS_MAX_NO_VREG_STEPS,
4073 &si_pi->mvdd_voltage_table);
4076 if (si_pi->vddc_phase_shed_control) {
4077 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4078 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4080 si_pi->vddc_phase_shed_control = false;
4082 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4083 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4084 si_pi->vddc_phase_shed_control = false;
4090 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4091 const struct atom_voltage_table *voltage_table,
4092 SISLANDS_SMC_STATETABLE *table)
4096 for (i = 0; i < voltage_table->count; i++)
4097 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4100 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4101 SISLANDS_SMC_STATETABLE *table)
4103 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4104 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4105 struct si_power_info *si_pi = si_get_pi(rdev);
4108 if (si_pi->voltage_control_svi2) {
4109 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4110 si_pi->svc_gpio_id);
4111 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4112 si_pi->svd_gpio_id);
4113 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4116 if (eg_pi->vddc_voltage_table.count) {
4117 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4118 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4119 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4121 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4122 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4123 table->maxVDDCIndexInPPTable = i;
4129 if (eg_pi->vddci_voltage_table.count) {
4130 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4132 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4133 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4137 if (si_pi->mvdd_voltage_table.count) {
4138 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4140 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4141 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4144 if (si_pi->vddc_phase_shed_control) {
4145 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4146 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4147 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4149 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4150 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4152 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4153 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4155 si_pi->vddc_phase_shed_control = false;
4163 static int si_populate_voltage_value(struct radeon_device *rdev,
4164 const struct atom_voltage_table *table,
4165 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4169 for (i = 0; i < table->count; i++) {
4170 if (value <= table->entries[i].value) {
4171 voltage->index = (u8)i;
4172 voltage->value = cpu_to_be16(table->entries[i].value);
4177 if (i >= table->count)
4183 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4184 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4186 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4187 struct si_power_info *si_pi = si_get_pi(rdev);
4189 if (pi->mvdd_control) {
4190 if (mclk <= pi->mvdd_split_frequency)
4193 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4195 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4200 static int si_get_std_voltage_value(struct radeon_device *rdev,
4201 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4205 bool voltage_found = false;
4206 *std_voltage = be16_to_cpu(voltage->value);
4208 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4209 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4210 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4213 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4214 if (be16_to_cpu(voltage->value) ==
4215 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4216 voltage_found = true;
4217 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4219 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4222 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4227 if (!voltage_found) {
4228 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4229 if (be16_to_cpu(voltage->value) <=
4230 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4231 voltage_found = true;
4232 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4234 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4237 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4243 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4244 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4251 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4252 u16 value, u8 index,
4253 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4255 voltage->index = index;
4256 voltage->value = cpu_to_be16(value);
4261 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4262 const struct radeon_phase_shedding_limits_table *limits,
4263 u16 voltage, u32 sclk, u32 mclk,
4264 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4268 for (i = 0; i < limits->count; i++) {
4269 if ((voltage <= limits->entries[i].voltage) &&
4270 (sclk <= limits->entries[i].sclk) &&
4271 (mclk <= limits->entries[i].mclk))
4275 smc_voltage->phase_settings = (u8)i;
4280 static int si_init_arb_table_index(struct radeon_device *rdev)
4282 struct si_power_info *si_pi = si_get_pi(rdev);
4286 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4291 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4293 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4296 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4298 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4301 static int si_reset_to_default(struct radeon_device *rdev)
4303 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4307 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4309 struct si_power_info *si_pi = si_get_pi(rdev);
4313 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4314 &tmp, si_pi->sram_end);
4318 tmp = (tmp >> 24) & 0xff;
4320 if (tmp == MC_CG_ARB_FREQ_F0)
4323 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4326 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4330 u32 dram_refresh_rate;
4331 u32 mc_arb_rfsh_rate;
4332 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4337 dram_rows = 1 << (tmp + 10);
4339 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4340 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4342 return mc_arb_rfsh_rate;
4345 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4346 struct rv7xx_pl *pl,
4347 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4353 arb_regs->mc_arb_rfsh_rate =
4354 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4356 radeon_atom_set_engine_dram_timings(rdev,
4360 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4361 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4362 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4364 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4365 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4366 arb_regs->mc_arb_burst_time = (u8)burst_time;
4371 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4372 struct radeon_ps *radeon_state,
4373 unsigned int first_arb_set)
4375 struct si_power_info *si_pi = si_get_pi(rdev);
4376 struct ni_ps *state = ni_get_ps(radeon_state);
4377 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4380 for (i = 0; i < state->performance_level_count; i++) {
4381 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4384 ret = si_copy_bytes_to_smc(rdev,
4385 si_pi->arb_table_start +
4386 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4387 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4389 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4398 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4399 struct radeon_ps *radeon_new_state)
4401 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4402 SISLANDS_DRIVER_STATE_ARB_INDEX);
4405 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4406 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4408 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4409 struct si_power_info *si_pi = si_get_pi(rdev);
4411 if (pi->mvdd_control)
4412 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4413 si_pi->mvdd_bootup_value, voltage);
4418 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4419 struct radeon_ps *radeon_initial_state,
4420 SISLANDS_SMC_STATETABLE *table)
4422 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4423 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4424 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4425 struct si_power_info *si_pi = si_get_pi(rdev);
4429 table->initialState.levels[0].mclk.vDLL_CNTL =
4430 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4431 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4432 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4433 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4434 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4435 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4436 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4437 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4438 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4439 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4440 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4441 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4442 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4443 table->initialState.levels[0].mclk.vMPLL_SS =
4444 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4445 table->initialState.levels[0].mclk.vMPLL_SS2 =
4446 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4448 table->initialState.levels[0].mclk.mclk_value =
4449 cpu_to_be32(initial_state->performance_levels[0].mclk);
4451 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4452 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4453 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4454 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4455 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4456 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4457 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4458 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4459 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4460 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4461 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4462 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4464 table->initialState.levels[0].sclk.sclk_value =
4465 cpu_to_be32(initial_state->performance_levels[0].sclk);
4467 table->initialState.levels[0].arbRefreshState =
4468 SISLANDS_INITIAL_STATE_ARB_INDEX;
4470 table->initialState.levels[0].ACIndex = 0;
4472 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4473 initial_state->performance_levels[0].vddc,
4474 &table->initialState.levels[0].vddc);
4479 ret = si_get_std_voltage_value(rdev,
4480 &table->initialState.levels[0].vddc,
4483 si_populate_std_voltage_value(rdev, std_vddc,
4484 table->initialState.levels[0].vddc.index,
4485 &table->initialState.levels[0].std_vddc);
4488 if (eg_pi->vddci_control)
4489 si_populate_voltage_value(rdev,
4490 &eg_pi->vddci_voltage_table,
4491 initial_state->performance_levels[0].vddci,
4492 &table->initialState.levels[0].vddci);
4494 if (si_pi->vddc_phase_shed_control)
4495 si_populate_phase_shedding_value(rdev,
4496 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4497 initial_state->performance_levels[0].vddc,
4498 initial_state->performance_levels[0].sclk,
4499 initial_state->performance_levels[0].mclk,
4500 &table->initialState.levels[0].vddc);
4502 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4504 reg = CG_R(0xffff) | CG_L(0);
4505 table->initialState.levels[0].aT = cpu_to_be32(reg);
4507 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4509 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4511 if (pi->mem_gddr5) {
4512 table->initialState.levels[0].strobeMode =
4513 si_get_strobe_mode_settings(rdev,
4514 initial_state->performance_levels[0].mclk);
4516 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4517 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4519 table->initialState.levels[0].mcFlags = 0;
4522 table->initialState.levelCount = 1;
4524 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4526 table->initialState.levels[0].dpm2.MaxPS = 0;
4527 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4528 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4529 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4530 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4532 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4533 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4535 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4536 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4541 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4542 SISLANDS_SMC_STATETABLE *table)
4544 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4545 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4546 struct si_power_info *si_pi = si_get_pi(rdev);
4547 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4548 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4549 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4550 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4551 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4552 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4553 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4554 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4555 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4556 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4557 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4561 table->ACPIState = table->initialState;
4563 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4565 if (pi->acpi_vddc) {
4566 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4567 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4571 ret = si_get_std_voltage_value(rdev,
4572 &table->ACPIState.levels[0].vddc, &std_vddc);
4574 si_populate_std_voltage_value(rdev, std_vddc,
4575 table->ACPIState.levels[0].vddc.index,
4576 &table->ACPIState.levels[0].std_vddc);
4578 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4580 if (si_pi->vddc_phase_shed_control) {
4581 si_populate_phase_shedding_value(rdev,
4582 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4586 &table->ACPIState.levels[0].vddc);
4589 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4590 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4594 ret = si_get_std_voltage_value(rdev,
4595 &table->ACPIState.levels[0].vddc, &std_vddc);
4598 si_populate_std_voltage_value(rdev, std_vddc,
4599 table->ACPIState.levels[0].vddc.index,
4600 &table->ACPIState.levels[0].std_vddc);
4602 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4603 si_pi->sys_pcie_mask,
4604 si_pi->boot_pcie_gen,
4607 if (si_pi->vddc_phase_shed_control)
4608 si_populate_phase_shedding_value(rdev,
4609 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4610 pi->min_vddc_in_table,
4613 &table->ACPIState.levels[0].vddc);
4616 if (pi->acpi_vddc) {
4617 if (eg_pi->acpi_vddci)
4618 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4620 &table->ACPIState.levels[0].vddci);
4623 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4624 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4626 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4628 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4629 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4631 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4632 cpu_to_be32(dll_cntl);
4633 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4634 cpu_to_be32(mclk_pwrmgt_cntl);
4635 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4636 cpu_to_be32(mpll_ad_func_cntl);
4637 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4638 cpu_to_be32(mpll_dq_func_cntl);
4639 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4640 cpu_to_be32(mpll_func_cntl);
4641 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4642 cpu_to_be32(mpll_func_cntl_1);
4643 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4644 cpu_to_be32(mpll_func_cntl_2);
4645 table->ACPIState.levels[0].mclk.vMPLL_SS =
4646 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4647 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4648 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4650 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4651 cpu_to_be32(spll_func_cntl);
4652 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4653 cpu_to_be32(spll_func_cntl_2);
4654 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4655 cpu_to_be32(spll_func_cntl_3);
4656 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4657 cpu_to_be32(spll_func_cntl_4);
4659 table->ACPIState.levels[0].mclk.mclk_value = 0;
4660 table->ACPIState.levels[0].sclk.sclk_value = 0;
4662 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4664 if (eg_pi->dynamic_ac_timing)
4665 table->ACPIState.levels[0].ACIndex = 0;
4667 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4668 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4669 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4670 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4671 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4673 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4674 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4676 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4677 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4682 static int si_populate_ulv_state(struct radeon_device *rdev,
4683 SISLANDS_SMC_SWSTATE *state)
4685 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4686 struct si_power_info *si_pi = si_get_pi(rdev);
4687 struct si_ulv_param *ulv = &si_pi->ulv;
4688 u32 sclk_in_sr = 1350; /* ??? */
4691 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4694 if (eg_pi->sclk_deep_sleep) {
4695 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4696 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4698 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4700 if (ulv->one_pcie_lane_in_ulv)
4701 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4702 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4703 state->levels[0].ACIndex = 1;
4704 state->levels[0].std_vddc = state->levels[0].vddc;
4705 state->levelCount = 1;
4707 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4713 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4715 struct si_power_info *si_pi = si_get_pi(rdev);
4716 struct si_ulv_param *ulv = &si_pi->ulv;
4717 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4720 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4725 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4726 ulv->volt_change_delay);
4728 ret = si_copy_bytes_to_smc(rdev,
4729 si_pi->arb_table_start +
4730 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4731 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4733 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4739 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4741 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4743 pi->mvdd_split_frequency = 30000;
4746 static int si_init_smc_table(struct radeon_device *rdev)
4748 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4749 struct si_power_info *si_pi = si_get_pi(rdev);
4750 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4751 const struct si_ulv_param *ulv = &si_pi->ulv;
4752 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4757 si_populate_smc_voltage_tables(rdev, table);
4759 switch (rdev->pm.int_thermal_type) {
4760 case THERMAL_TYPE_SI:
4761 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4762 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4764 case THERMAL_TYPE_NONE:
4765 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4768 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4772 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4773 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4775 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4776 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4777 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4780 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4781 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4784 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4786 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4787 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4789 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4790 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4791 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4792 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4796 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4800 ret = si_populate_smc_acpi_state(rdev, table);
4804 table->driverState = table->initialState;
4806 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4807 SISLANDS_INITIAL_STATE_ARB_INDEX);
4811 if (ulv->supported && ulv->pl.vddc) {
4812 ret = si_populate_ulv_state(rdev, &table->ULVState);
4816 ret = si_program_ulv_memory_timing_parameters(rdev);
4820 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4821 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4823 lane_width = radeon_get_pcie_lanes(rdev);
4824 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4826 table->ULVState = table->initialState;
4829 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4830 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4834 static int si_calculate_sclk_params(struct radeon_device *rdev,
4836 SISLANDS_SMC_SCLK_VALUE *sclk)
4838 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4839 struct si_power_info *si_pi = si_get_pi(rdev);
4840 struct atom_clock_dividers dividers;
4841 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4842 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4843 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4844 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4845 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4846 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4848 u32 reference_clock = rdev->clock.spll.reference_freq;
4849 u32 reference_divider;
4853 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4854 engine_clock, false, ÷rs);
4858 reference_divider = 1 + dividers.ref_div;
4860 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4861 do_div(tmp, reference_clock);
4864 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4865 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4866 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4868 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4869 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4871 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4872 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4873 spll_func_cntl_3 |= SPLL_DITHEN;
4876 struct radeon_atom_ss ss;
4877 u32 vco_freq = engine_clock * dividers.post_div;
4879 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4880 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4881 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4882 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4884 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4885 cg_spll_spread_spectrum |= CLK_S(clk_s);
4886 cg_spll_spread_spectrum |= SSEN;
4888 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4889 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4893 sclk->sclk_value = engine_clock;
4894 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4895 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4896 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4897 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4898 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4899 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4904 static int si_populate_sclk_value(struct radeon_device *rdev,
4906 SISLANDS_SMC_SCLK_VALUE *sclk)
4908 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4911 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4913 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4914 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4915 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4916 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4917 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4918 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4919 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4925 static int si_populate_mclk_value(struct radeon_device *rdev,
4928 SISLANDS_SMC_MCLK_VALUE *mclk,
4932 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4933 struct si_power_info *si_pi = si_get_pi(rdev);
4934 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4935 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4936 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4937 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4938 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4939 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4940 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4941 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4942 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4943 struct atom_mpll_param mpll_param;
4946 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4950 mpll_func_cntl &= ~BWCTRL_MASK;
4951 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4953 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4954 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4955 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4957 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4958 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4960 if (pi->mem_gddr5) {
4961 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4962 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4963 YCLK_POST_DIV(mpll_param.post_div);
4967 struct radeon_atom_ss ss;
4970 u32 reference_clock = rdev->clock.mpll.reference_freq;
4973 freq_nom = memory_clock * 4;
4975 freq_nom = memory_clock * 2;
4977 tmp = freq_nom / reference_clock;
4979 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4980 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4981 u32 clks = reference_clock * 5 / ss.rate;
4982 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4984 mpll_ss1 &= ~CLKV_MASK;
4985 mpll_ss1 |= CLKV(clkv);
4987 mpll_ss2 &= ~CLKS_MASK;
4988 mpll_ss2 |= CLKS(clks);
4992 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4993 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4996 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4998 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5000 mclk->mclk_value = cpu_to_be32(memory_clock);
5001 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5002 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5003 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5004 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5005 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5006 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5007 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5008 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5009 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5014 static void si_populate_smc_sp(struct radeon_device *rdev,
5015 struct radeon_ps *radeon_state,
5016 SISLANDS_SMC_SWSTATE *smc_state)
5018 struct ni_ps *ps = ni_get_ps(radeon_state);
5019 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5022 for (i = 0; i < ps->performance_level_count - 1; i++)
5023 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5025 smc_state->levels[ps->performance_level_count - 1].bSP =
5026 cpu_to_be32(pi->psp);
5029 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5030 struct rv7xx_pl *pl,
5031 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5033 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5034 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5035 struct si_power_info *si_pi = si_get_pi(rdev);
5039 bool gmc_pg = false;
5041 if (eg_pi->pcie_performance_request &&
5042 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5043 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5045 level->gen2PCIE = (u8)pl->pcie_gen;
5047 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5053 if (pi->mclk_stutter_mode_threshold &&
5054 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5055 !eg_pi->uvd_enabled &&
5056 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5057 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5058 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5061 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5064 if (pi->mem_gddr5) {
5065 if (pl->mclk > pi->mclk_edc_enable_threshold)
5066 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5068 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5069 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5071 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5073 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5074 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5075 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5076 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5078 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5080 dll_state_on = false;
5083 level->strobeMode = si_get_strobe_mode_settings(rdev,
5086 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5089 ret = si_populate_mclk_value(rdev,
5093 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5097 ret = si_populate_voltage_value(rdev,
5098 &eg_pi->vddc_voltage_table,
5099 pl->vddc, &level->vddc);
5104 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5108 ret = si_populate_std_voltage_value(rdev, std_vddc,
5109 level->vddc.index, &level->std_vddc);
5113 if (eg_pi->vddci_control) {
5114 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5115 pl->vddci, &level->vddci);
5120 if (si_pi->vddc_phase_shed_control) {
5121 ret = si_populate_phase_shedding_value(rdev,
5122 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5131 level->MaxPoweredUpCU = si_pi->max_cu;
5133 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5138 static int si_populate_smc_t(struct radeon_device *rdev,
5139 struct radeon_ps *radeon_state,
5140 SISLANDS_SMC_SWSTATE *smc_state)
5142 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5143 struct ni_ps *state = ni_get_ps(radeon_state);
5149 if (state->performance_level_count >= 9)
5152 if (state->performance_level_count < 2) {
5153 a_t = CG_R(0xffff) | CG_L(0);
5154 smc_state->levels[0].aT = cpu_to_be32(a_t);
5158 smc_state->levels[0].aT = cpu_to_be32(0);
5160 for (i = 0; i <= state->performance_level_count - 2; i++) {
5161 ret = r600_calculate_at(
5162 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5164 state->performance_levels[i + 1].sclk,
5165 state->performance_levels[i].sclk,
5170 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5171 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5174 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5175 a_t |= CG_R(t_l * pi->bsp / 20000);
5176 smc_state->levels[i].aT = cpu_to_be32(a_t);
5178 high_bsp = (i == state->performance_level_count - 2) ?
5180 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5181 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5187 static int si_disable_ulv(struct radeon_device *rdev)
5189 struct si_power_info *si_pi = si_get_pi(rdev);
5190 struct si_ulv_param *ulv = &si_pi->ulv;
5193 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5199 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5200 struct radeon_ps *radeon_state)
5202 const struct si_power_info *si_pi = si_get_pi(rdev);
5203 const struct si_ulv_param *ulv = &si_pi->ulv;
5204 const struct ni_ps *state = ni_get_ps(radeon_state);
5207 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5210 /* XXX validate against display requirements! */
5212 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5213 if (rdev->clock.current_dispclk <=
5214 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5216 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5221 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5227 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5228 struct radeon_ps *radeon_new_state)
5230 const struct si_power_info *si_pi = si_get_pi(rdev);
5231 const struct si_ulv_param *ulv = &si_pi->ulv;
5233 if (ulv->supported) {
5234 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5235 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5241 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5242 struct radeon_ps *radeon_state,
5243 SISLANDS_SMC_SWSTATE *smc_state)
5245 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5246 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5247 struct si_power_info *si_pi = si_get_pi(rdev);
5248 struct ni_ps *state = ni_get_ps(radeon_state);
5251 u32 sclk_in_sr = 1350; /* ??? */
5253 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5256 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5258 if (radeon_state->vclk && radeon_state->dclk) {
5259 eg_pi->uvd_enabled = true;
5260 if (eg_pi->smu_uvd_hs)
5261 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5263 eg_pi->uvd_enabled = false;
5266 if (state->dc_compatible)
5267 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5269 smc_state->levelCount = 0;
5270 for (i = 0; i < state->performance_level_count; i++) {
5271 if (eg_pi->sclk_deep_sleep) {
5272 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5273 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5274 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5276 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5280 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5281 &smc_state->levels[i]);
5282 smc_state->levels[i].arbRefreshState =
5283 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5288 if (ni_pi->enable_power_containment)
5289 smc_state->levels[i].displayWatermark =
5290 (state->performance_levels[i].sclk < threshold) ?
5291 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5293 smc_state->levels[i].displayWatermark = (i < 2) ?
5294 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5296 if (eg_pi->dynamic_ac_timing)
5297 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5299 smc_state->levels[i].ACIndex = 0;
5301 smc_state->levelCount++;
5304 si_write_smc_soft_register(rdev,
5305 SI_SMC_SOFT_REGISTER_watermark_threshold,
5308 si_populate_smc_sp(rdev, radeon_state, smc_state);
5310 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5312 ni_pi->enable_power_containment = false;
5314 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5316 ni_pi->enable_sq_ramping = false;
5318 return si_populate_smc_t(rdev, radeon_state, smc_state);
5321 static int si_upload_sw_state(struct radeon_device *rdev,
5322 struct radeon_ps *radeon_new_state)
5324 struct si_power_info *si_pi = si_get_pi(rdev);
5325 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5327 u32 address = si_pi->state_table_start +
5328 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5329 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5330 ((new_state->performance_level_count - 1) *
5331 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5332 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5334 memset(smc_state, 0, state_size);
5336 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5340 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5341 state_size, si_pi->sram_end);
5346 static int si_upload_ulv_state(struct radeon_device *rdev)
5348 struct si_power_info *si_pi = si_get_pi(rdev);
5349 struct si_ulv_param *ulv = &si_pi->ulv;
5352 if (ulv->supported && ulv->pl.vddc) {
5353 u32 address = si_pi->state_table_start +
5354 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5355 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5356 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5358 memset(smc_state, 0, state_size);
5360 ret = si_populate_ulv_state(rdev, smc_state);
5362 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5363 state_size, si_pi->sram_end);
5369 static int si_upload_smc_data(struct radeon_device *rdev)
5371 struct radeon_crtc *radeon_crtc = NULL;
5374 if (rdev->pm.dpm.new_active_crtc_count == 0)
5377 for (i = 0; i < rdev->num_crtc; i++) {
5378 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5379 radeon_crtc = rdev->mode_info.crtcs[i];
5384 if (radeon_crtc == NULL)
5387 if (radeon_crtc->line_time <= 0)
5390 if (si_write_smc_soft_register(rdev,
5391 SI_SMC_SOFT_REGISTER_crtc_index,
5392 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5395 if (si_write_smc_soft_register(rdev,
5396 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5397 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5400 if (si_write_smc_soft_register(rdev,
5401 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5402 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5408 static int si_set_mc_special_registers(struct radeon_device *rdev,
5409 struct si_mc_reg_table *table)
5411 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5415 for (i = 0, j = table->last; i < table->last; i++) {
5416 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5418 switch (table->mc_reg_address[i].s1 << 2) {
5420 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5421 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5422 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5423 for (k = 0; k < table->num_entries; k++)
5424 table->mc_reg_table_entry[k].mc_data[j] =
5425 ((temp_reg & 0xffff0000)) |
5426 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5428 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5431 temp_reg = RREG32(MC_PMG_CMD_MRS);
5432 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5433 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5434 for (k = 0; k < table->num_entries; k++) {
5435 table->mc_reg_table_entry[k].mc_data[j] =
5436 (temp_reg & 0xffff0000) |
5437 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5439 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5442 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5445 if (!pi->mem_gddr5) {
5446 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5447 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5448 for (k = 0; k < table->num_entries; k++)
5449 table->mc_reg_table_entry[k].mc_data[j] =
5450 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5452 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5456 case MC_SEQ_RESERVE_M:
5457 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5458 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5459 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5460 for(k = 0; k < table->num_entries; k++)
5461 table->mc_reg_table_entry[k].mc_data[j] =
5462 (temp_reg & 0xffff0000) |
5463 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5465 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5478 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5483 case MC_SEQ_RAS_TIMING >> 2:
5484 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5486 case MC_SEQ_CAS_TIMING >> 2:
5487 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5489 case MC_SEQ_MISC_TIMING >> 2:
5490 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5492 case MC_SEQ_MISC_TIMING2 >> 2:
5493 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5495 case MC_SEQ_RD_CTL_D0 >> 2:
5496 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5498 case MC_SEQ_RD_CTL_D1 >> 2:
5499 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5501 case MC_SEQ_WR_CTL_D0 >> 2:
5502 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5504 case MC_SEQ_WR_CTL_D1 >> 2:
5505 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5507 case MC_PMG_CMD_EMRS >> 2:
5508 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5510 case MC_PMG_CMD_MRS >> 2:
5511 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5513 case MC_PMG_CMD_MRS1 >> 2:
5514 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5516 case MC_SEQ_PMG_TIMING >> 2:
5517 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5519 case MC_PMG_CMD_MRS2 >> 2:
5520 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5522 case MC_SEQ_WR_CTL_2 >> 2:
5523 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5533 static void si_set_valid_flag(struct si_mc_reg_table *table)
5537 for (i = 0; i < table->last; i++) {
5538 for (j = 1; j < table->num_entries; j++) {
5539 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5540 table->valid_flag |= 1 << i;
5547 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5552 for (i = 0; i < table->last; i++)
5553 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5554 address : table->mc_reg_address[i].s1;
5558 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5559 struct si_mc_reg_table *si_table)
5563 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5565 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5568 for (i = 0; i < table->last; i++)
5569 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5570 si_table->last = table->last;
5572 for (i = 0; i < table->num_entries; i++) {
5573 si_table->mc_reg_table_entry[i].mclk_max =
5574 table->mc_reg_table_entry[i].mclk_max;
5575 for (j = 0; j < table->last; j++) {
5576 si_table->mc_reg_table_entry[i].mc_data[j] =
5577 table->mc_reg_table_entry[i].mc_data[j];
5580 si_table->num_entries = table->num_entries;
5585 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5587 struct si_power_info *si_pi = si_get_pi(rdev);
5588 struct atom_mc_reg_table *table;
5589 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5590 u8 module_index = rv770_get_memory_module_index(rdev);
5593 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5597 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5598 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5599 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5600 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5601 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5602 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5603 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5604 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5605 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5606 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5607 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5608 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5609 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5610 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5612 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5616 ret = si_copy_vbios_mc_reg_table(table, si_table);
5620 si_set_s0_mc_reg_index(si_table);
5622 ret = si_set_mc_special_registers(rdev, si_table);
5626 si_set_valid_flag(si_table);
5635 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5636 SMC_SIslands_MCRegisters *mc_reg_table)
5638 struct si_power_info *si_pi = si_get_pi(rdev);
5641 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5642 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5643 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5645 mc_reg_table->address[i].s0 =
5646 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5647 mc_reg_table->address[i].s1 =
5648 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5652 mc_reg_table->last = (u8)i;
5655 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5656 SMC_SIslands_MCRegisterSet *data,
5657 u32 num_entries, u32 valid_flag)
5661 for(i = 0, j = 0; j < num_entries; j++) {
5662 if (valid_flag & (1 << j)) {
5663 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5669 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5670 struct rv7xx_pl *pl,
5671 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5673 struct si_power_info *si_pi = si_get_pi(rdev);
5676 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5677 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5681 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5684 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5685 mc_reg_table_data, si_pi->mc_reg_table.last,
5686 si_pi->mc_reg_table.valid_flag);
5689 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5690 struct radeon_ps *radeon_state,
5691 SMC_SIslands_MCRegisters *mc_reg_table)
5693 struct ni_ps *state = ni_get_ps(radeon_state);
5696 for (i = 0; i < state->performance_level_count; i++) {
5697 si_convert_mc_reg_table_entry_to_smc(rdev,
5698 &state->performance_levels[i],
5699 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5703 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5704 struct radeon_ps *radeon_boot_state)
5706 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5707 struct si_power_info *si_pi = si_get_pi(rdev);
5708 struct si_ulv_param *ulv = &si_pi->ulv;
5709 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5711 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5713 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5715 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5717 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5718 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5720 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5721 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5722 si_pi->mc_reg_table.last,
5723 si_pi->mc_reg_table.valid_flag);
5725 if (ulv->supported && ulv->pl.vddc != 0)
5726 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5727 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5729 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5730 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5731 si_pi->mc_reg_table.last,
5732 si_pi->mc_reg_table.valid_flag);
5734 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5736 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5737 (u8 *)smc_mc_reg_table,
5738 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5741 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5742 struct radeon_ps *radeon_new_state)
5744 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5745 struct si_power_info *si_pi = si_get_pi(rdev);
5746 u32 address = si_pi->mc_reg_table_start +
5747 offsetof(SMC_SIslands_MCRegisters,
5748 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5749 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5751 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5753 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5756 return si_copy_bytes_to_smc(rdev, address,
5757 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5758 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5763 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5766 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5768 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5771 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5772 struct radeon_ps *radeon_state)
5774 struct ni_ps *state = ni_get_ps(radeon_state);
5776 u16 pcie_speed, max_speed = 0;
5778 for (i = 0; i < state->performance_level_count; i++) {
5779 pcie_speed = state->performance_levels[i].pcie_gen;
5780 if (max_speed < pcie_speed)
5781 max_speed = pcie_speed;
5786 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5790 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5791 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5793 return (u16)speed_cntl;
5796 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5797 struct radeon_ps *radeon_new_state,
5798 struct radeon_ps *radeon_current_state)
5800 struct si_power_info *si_pi = si_get_pi(rdev);
5801 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5802 enum radeon_pcie_gen current_link_speed;
5804 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5805 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5807 current_link_speed = si_pi->force_pcie_gen;
5809 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5810 si_pi->pspp_notify_required = false;
5811 if (target_link_speed > current_link_speed) {
5812 switch (target_link_speed) {
5813 #if defined(CONFIG_ACPI)
5814 case RADEON_PCIE_GEN3:
5815 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5817 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5818 if (current_link_speed == RADEON_PCIE_GEN2)
5820 case RADEON_PCIE_GEN2:
5821 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5825 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5829 if (target_link_speed < current_link_speed)
5830 si_pi->pspp_notify_required = true;
5834 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5835 struct radeon_ps *radeon_new_state,
5836 struct radeon_ps *radeon_current_state)
5838 struct si_power_info *si_pi = si_get_pi(rdev);
5839 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5842 if (si_pi->pspp_notify_required) {
5843 if (target_link_speed == RADEON_PCIE_GEN3)
5844 request = PCIE_PERF_REQ_PECI_GEN3;
5845 else if (target_link_speed == RADEON_PCIE_GEN2)
5846 request = PCIE_PERF_REQ_PECI_GEN2;
5848 request = PCIE_PERF_REQ_PECI_GEN1;
5850 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5851 (si_get_current_pcie_speed(rdev) > 0))
5854 #if defined(CONFIG_ACPI)
5855 radeon_acpi_pcie_performance_request(rdev, request, false);
5861 static int si_ds_request(struct radeon_device *rdev,
5862 bool ds_status_on, u32 count_write)
5864 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5866 if (eg_pi->sclk_deep_sleep) {
5868 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5872 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5873 PPSMC_Result_OK) ? 0 : -EINVAL;
5879 static void si_set_max_cu_value(struct radeon_device *rdev)
5881 struct si_power_info *si_pi = si_get_pi(rdev);
5883 if (rdev->family == CHIP_VERDE) {
5884 switch (rdev->pdev->device) {
5920 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5921 struct radeon_clock_voltage_dependency_table *table)
5925 u16 leakage_voltage;
5928 for (i = 0; i < table->count; i++) {
5929 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5930 table->entries[i].v,
5931 &leakage_voltage)) {
5933 table->entries[i].v = leakage_voltage;
5943 for (j = (table->count - 2); j >= 0; j--) {
5944 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5945 table->entries[j].v : table->entries[j + 1].v;
5951 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5955 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5957 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5958 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5959 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5960 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5964 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5965 struct radeon_ps *radeon_new_state,
5966 struct radeon_ps *radeon_current_state)
5969 u32 new_lane_width =
5970 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5971 u32 current_lane_width =
5972 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5974 if (new_lane_width != current_lane_width) {
5975 radeon_set_pcie_lanes(rdev, new_lane_width);
5976 lane_width = radeon_get_pcie_lanes(rdev);
5977 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5981 static void si_set_vce_clock(struct radeon_device *rdev,
5982 struct radeon_ps *new_rps,
5983 struct radeon_ps *old_rps)
5985 if ((old_rps->evclk != new_rps->evclk) ||
5986 (old_rps->ecclk != new_rps->ecclk)) {
5987 /* turn the clocks on when encoding, off otherwise */
5988 if (new_rps->evclk || new_rps->ecclk)
5989 vce_v1_0_enable_mgcg(rdev, false);
5991 vce_v1_0_enable_mgcg(rdev, true);
5992 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5996 void si_dpm_setup_asic(struct radeon_device *rdev)
6000 r = si_mc_load_microcode(rdev);
6002 DRM_ERROR("Failed to load MC firmware!\n");
6003 rv770_get_memory_type(rdev);
6004 si_read_clock_registers(rdev);
6005 si_enable_acpi_power_management(rdev);
6008 static int si_thermal_enable_alert(struct radeon_device *rdev,
6011 u32 thermal_int = RREG32(CG_THERMAL_INT);
6014 PPSMC_Result result;
6016 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6017 WREG32(CG_THERMAL_INT, thermal_int);
6018 rdev->irq.dpm_thermal = false;
6019 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6020 if (result != PPSMC_Result_OK) {
6021 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6025 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6026 WREG32(CG_THERMAL_INT, thermal_int);
6027 rdev->irq.dpm_thermal = true;
6033 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6034 int min_temp, int max_temp)
6036 int low_temp = 0 * 1000;
6037 int high_temp = 255 * 1000;
6039 if (low_temp < min_temp)
6040 low_temp = min_temp;
6041 if (high_temp > max_temp)
6042 high_temp = max_temp;
6043 if (high_temp < low_temp) {
6044 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6048 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6049 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6050 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6052 rdev->pm.dpm.thermal.min_temp = low_temp;
6053 rdev->pm.dpm.thermal.max_temp = high_temp;
6058 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6060 struct si_power_info *si_pi = si_get_pi(rdev);
6063 if (si_pi->fan_ctrl_is_in_default_mode) {
6064 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6065 si_pi->fan_ctrl_default_mode = tmp;
6066 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6068 si_pi->fan_ctrl_is_in_default_mode = false;
6071 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6073 WREG32(CG_FDO_CTRL2, tmp);
6075 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6076 tmp |= FDO_PWM_MODE(mode);
6077 WREG32(CG_FDO_CTRL2, tmp);
6080 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6082 struct si_power_info *si_pi = si_get_pi(rdev);
6083 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6085 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6086 u16 fdo_min, slope1, slope2;
6087 u32 reference_clock, tmp;
6091 if (!si_pi->fan_table_start) {
6092 rdev->pm.dpm.fan.ucode_fan_control = false;
6096 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6099 rdev->pm.dpm.fan.ucode_fan_control = false;
6103 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6104 do_div(tmp64, 10000);
6105 fdo_min = (u16)tmp64;
6107 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6108 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6110 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6111 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6113 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6114 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6116 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6117 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6118 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6120 fan_table.slope1 = cpu_to_be16(slope1);
6121 fan_table.slope2 = cpu_to_be16(slope2);
6123 fan_table.fdo_min = cpu_to_be16(fdo_min);
6125 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6127 fan_table.hys_up = cpu_to_be16(1);
6129 fan_table.hys_slope = cpu_to_be16(1);
6131 fan_table.temp_resp_lim = cpu_to_be16(5);
6133 reference_clock = radeon_get_xclk(rdev);
6135 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6136 reference_clock) / 1600);
6138 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6140 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6141 fan_table.temp_src = (uint8_t)tmp;
6143 ret = si_copy_bytes_to_smc(rdev,
6144 si_pi->fan_table_start,
6150 DRM_ERROR("Failed to load fan table to the SMC.");
6151 rdev->pm.dpm.fan.ucode_fan_control = false;
6157 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6159 struct si_power_info *si_pi = si_get_pi(rdev);
6162 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6163 if (ret == PPSMC_Result_OK) {
6164 si_pi->fan_is_controlled_by_smc = true;
6171 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6173 struct si_power_info *si_pi = si_get_pi(rdev);
6176 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6178 if (ret == PPSMC_Result_OK) {
6179 si_pi->fan_is_controlled_by_smc = false;
6186 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6192 if (rdev->pm.no_fan)
6195 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6196 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6201 tmp64 = (u64)duty * 100;
6202 do_div(tmp64, duty100);
6203 *speed = (u32)tmp64;
6211 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6214 struct si_power_info *si_pi = si_get_pi(rdev);
6219 if (rdev->pm.no_fan)
6222 if (si_pi->fan_is_controlled_by_smc)
6228 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6233 tmp64 = (u64)speed * duty100;
6237 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6238 tmp |= FDO_STATIC_DUTY(duty);
6239 WREG32(CG_FDO_CTRL0, tmp);
6244 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6247 /* stop auto-manage */
6248 if (rdev->pm.dpm.fan.ucode_fan_control)
6249 si_fan_ctrl_stop_smc_fan_control(rdev);
6250 si_fan_ctrl_set_static_mode(rdev, mode);
6252 /* restart auto-manage */
6253 if (rdev->pm.dpm.fan.ucode_fan_control)
6254 si_thermal_start_smc_fan_control(rdev);
6256 si_fan_ctrl_set_default_mode(rdev);
6260 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6262 struct si_power_info *si_pi = si_get_pi(rdev);
6265 if (si_pi->fan_is_controlled_by_smc)
6268 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6269 return (tmp >> FDO_PWM_MODE_SHIFT);
6273 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6277 u32 xclk = radeon_get_xclk(rdev);
6279 if (rdev->pm.no_fan)
6282 if (rdev->pm.fan_pulses_per_revolution == 0)
6285 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6286 if (tach_period == 0)
6289 *speed = 60 * xclk * 10000 / tach_period;
6294 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6297 u32 tach_period, tmp;
6298 u32 xclk = radeon_get_xclk(rdev);
6300 if (rdev->pm.no_fan)
6303 if (rdev->pm.fan_pulses_per_revolution == 0)
6306 if ((speed < rdev->pm.fan_min_rpm) ||
6307 (speed > rdev->pm.fan_max_rpm))
6310 if (rdev->pm.dpm.fan.ucode_fan_control)
6311 si_fan_ctrl_stop_smc_fan_control(rdev);
6313 tach_period = 60 * xclk * 10000 / (8 * speed);
6314 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6315 tmp |= TARGET_PERIOD(tach_period);
6316 WREG32(CG_TACH_CTRL, tmp);
6318 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6324 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6326 struct si_power_info *si_pi = si_get_pi(rdev);
6329 if (!si_pi->fan_ctrl_is_in_default_mode) {
6330 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6331 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6332 WREG32(CG_FDO_CTRL2, tmp);
6334 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6335 tmp |= TMIN(si_pi->t_min);
6336 WREG32(CG_FDO_CTRL2, tmp);
6337 si_pi->fan_ctrl_is_in_default_mode = true;
6341 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6343 if (rdev->pm.dpm.fan.ucode_fan_control) {
6344 si_fan_ctrl_start_smc_fan_control(rdev);
6345 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6349 static void si_thermal_initialize(struct radeon_device *rdev)
6353 if (rdev->pm.fan_pulses_per_revolution) {
6354 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6355 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6356 WREG32(CG_TACH_CTRL, tmp);
6359 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6360 tmp |= TACH_PWM_RESP_RATE(0x28);
6361 WREG32(CG_FDO_CTRL2, tmp);
6364 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6368 si_thermal_initialize(rdev);
6369 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6372 ret = si_thermal_enable_alert(rdev, true);
6375 if (rdev->pm.dpm.fan.ucode_fan_control) {
6376 ret = si_halt_smc(rdev);
6379 ret = si_thermal_setup_fan_table(rdev);
6382 ret = si_resume_smc(rdev);
6385 si_thermal_start_smc_fan_control(rdev);
6391 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6393 if (!rdev->pm.no_fan) {
6394 si_fan_ctrl_set_default_mode(rdev);
6395 si_fan_ctrl_stop_smc_fan_control(rdev);
6399 int si_dpm_enable(struct radeon_device *rdev)
6401 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6402 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6403 struct si_power_info *si_pi = si_get_pi(rdev);
6404 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6407 if (si_is_smc_running(rdev))
6409 if (pi->voltage_control || si_pi->voltage_control_svi2)
6410 si_enable_voltage_control(rdev, true);
6411 if (pi->mvdd_control)
6412 si_get_mvdd_configuration(rdev);
6413 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6414 ret = si_construct_voltage_tables(rdev);
6416 DRM_ERROR("si_construct_voltage_tables failed\n");
6420 if (eg_pi->dynamic_ac_timing) {
6421 ret = si_initialize_mc_reg_table(rdev);
6423 eg_pi->dynamic_ac_timing = false;
6426 si_enable_spread_spectrum(rdev, true);
6427 if (pi->thermal_protection)
6428 si_enable_thermal_protection(rdev, true);
6430 si_program_git(rdev);
6431 si_program_tp(rdev);
6432 si_program_tpp(rdev);
6433 si_program_sstp(rdev);
6434 si_enable_display_gap(rdev);
6435 si_program_vc(rdev);
6436 ret = si_upload_firmware(rdev);
6438 DRM_ERROR("si_upload_firmware failed\n");
6441 ret = si_process_firmware_header(rdev);
6443 DRM_ERROR("si_process_firmware_header failed\n");
6446 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6448 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6451 ret = si_init_smc_table(rdev);
6453 DRM_ERROR("si_init_smc_table failed\n");
6456 ret = si_init_smc_spll_table(rdev);
6458 DRM_ERROR("si_init_smc_spll_table failed\n");
6461 ret = si_init_arb_table_index(rdev);
6463 DRM_ERROR("si_init_arb_table_index failed\n");
6466 if (eg_pi->dynamic_ac_timing) {
6467 ret = si_populate_mc_reg_table(rdev, boot_ps);
6469 DRM_ERROR("si_populate_mc_reg_table failed\n");
6473 ret = si_initialize_smc_cac_tables(rdev);
6475 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6478 ret = si_initialize_hardware_cac_manager(rdev);
6480 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6483 ret = si_initialize_smc_dte_tables(rdev);
6485 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6488 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6490 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6493 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6495 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6498 si_program_response_times(rdev);
6499 si_program_ds_registers(rdev);
6500 si_dpm_start_smc(rdev);
6501 ret = si_notify_smc_display_change(rdev, false);
6503 DRM_ERROR("si_notify_smc_display_change failed\n");
6506 si_enable_sclk_control(rdev, true);
6509 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6511 si_thermal_start_thermal_controller(rdev);
6513 ni_update_current_ps(rdev, boot_ps);
6518 static int si_set_temperature_range(struct radeon_device *rdev)
6522 ret = si_thermal_enable_alert(rdev, false);
6525 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6528 ret = si_thermal_enable_alert(rdev, true);
6535 int si_dpm_late_enable(struct radeon_device *rdev)
6539 ret = si_set_temperature_range(rdev);
6546 void si_dpm_disable(struct radeon_device *rdev)
6548 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6549 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6551 if (!si_is_smc_running(rdev))
6553 si_thermal_stop_thermal_controller(rdev);
6554 si_disable_ulv(rdev);
6556 if (pi->thermal_protection)
6557 si_enable_thermal_protection(rdev, false);
6558 si_enable_power_containment(rdev, boot_ps, false);
6559 si_enable_smc_cac(rdev, boot_ps, false);
6560 si_enable_spread_spectrum(rdev, false);
6561 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6563 si_reset_to_default(rdev);
6564 si_dpm_stop_smc(rdev);
6565 si_force_switch_to_arb_f0(rdev);
6567 ni_update_current_ps(rdev, boot_ps);
6570 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6572 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6573 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6574 struct radeon_ps *new_ps = &requested_ps;
6576 ni_update_requested_ps(rdev, new_ps);
6578 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6583 static int si_power_control_set_level(struct radeon_device *rdev)
6585 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6588 ret = si_restrict_performance_levels_before_switch(rdev);
6591 ret = si_halt_smc(rdev);
6594 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6597 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6600 ret = si_resume_smc(rdev);
6603 ret = si_set_sw_state(rdev);
6609 int si_dpm_set_power_state(struct radeon_device *rdev)
6611 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6612 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6613 struct radeon_ps *old_ps = &eg_pi->current_rps;
6616 ret = si_disable_ulv(rdev);
6618 DRM_ERROR("si_disable_ulv failed\n");
6621 ret = si_restrict_performance_levels_before_switch(rdev);
6623 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6626 if (eg_pi->pcie_performance_request)
6627 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6628 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6629 ret = si_enable_power_containment(rdev, new_ps, false);
6631 DRM_ERROR("si_enable_power_containment failed\n");
6634 ret = si_enable_smc_cac(rdev, new_ps, false);
6636 DRM_ERROR("si_enable_smc_cac failed\n");
6639 ret = si_halt_smc(rdev);
6641 DRM_ERROR("si_halt_smc failed\n");
6644 ret = si_upload_sw_state(rdev, new_ps);
6646 DRM_ERROR("si_upload_sw_state failed\n");
6649 ret = si_upload_smc_data(rdev);
6651 DRM_ERROR("si_upload_smc_data failed\n");
6654 ret = si_upload_ulv_state(rdev);
6656 DRM_ERROR("si_upload_ulv_state failed\n");
6659 if (eg_pi->dynamic_ac_timing) {
6660 ret = si_upload_mc_reg_table(rdev, new_ps);
6662 DRM_ERROR("si_upload_mc_reg_table failed\n");
6666 ret = si_program_memory_timing_parameters(rdev, new_ps);
6668 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6671 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6673 ret = si_resume_smc(rdev);
6675 DRM_ERROR("si_resume_smc failed\n");
6678 ret = si_set_sw_state(rdev);
6680 DRM_ERROR("si_set_sw_state failed\n");
6683 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6684 si_set_vce_clock(rdev, new_ps, old_ps);
6685 if (eg_pi->pcie_performance_request)
6686 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6687 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6689 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6692 ret = si_enable_smc_cac(rdev, new_ps, true);
6694 DRM_ERROR("si_enable_smc_cac failed\n");
6697 ret = si_enable_power_containment(rdev, new_ps, true);
6699 DRM_ERROR("si_enable_power_containment failed\n");
6703 ret = si_power_control_set_level(rdev);
6705 DRM_ERROR("si_power_control_set_level failed\n");
6712 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6714 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6715 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6717 ni_update_current_ps(rdev, new_ps);
6721 void si_dpm_reset_asic(struct radeon_device *rdev)
6723 si_restrict_performance_levels_before_switch(rdev);
6724 si_disable_ulv(rdev);
6725 si_set_boot_state(rdev);
6729 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6731 si_program_display_gap(rdev);
6735 struct _ATOM_POWERPLAY_INFO info;
6736 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6737 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6738 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6739 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6740 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6743 union pplib_clock_info {
6744 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6745 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6746 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6747 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6748 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6751 union pplib_power_state {
6752 struct _ATOM_PPLIB_STATE v1;
6753 struct _ATOM_PPLIB_STATE_V2 v2;
6756 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6757 struct radeon_ps *rps,
6758 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6761 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6762 rps->class = le16_to_cpu(non_clock_info->usClassification);
6763 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6765 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6766 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6767 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6768 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6769 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6770 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6776 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6777 rdev->pm.dpm.boot_ps = rps;
6778 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6779 rdev->pm.dpm.uvd_ps = rps;
6782 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6783 struct radeon_ps *rps, int index,
6784 union pplib_clock_info *clock_info)
6786 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6787 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6788 struct si_power_info *si_pi = si_get_pi(rdev);
6789 struct ni_ps *ps = ni_get_ps(rps);
6790 u16 leakage_voltage;
6791 struct rv7xx_pl *pl = &ps->performance_levels[index];
6794 ps->performance_level_count = index + 1;
6796 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6797 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6798 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6799 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6801 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6802 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6803 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6804 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6805 si_pi->sys_pcie_mask,
6806 si_pi->boot_pcie_gen,
6807 clock_info->si.ucPCIEGen);
6809 /* patch up vddc if necessary */
6810 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6813 pl->vddc = leakage_voltage;
6815 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6816 pi->acpi_vddc = pl->vddc;
6817 eg_pi->acpi_vddci = pl->vddci;
6818 si_pi->acpi_pcie_gen = pl->pcie_gen;
6821 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6823 /* XXX disable for A0 tahiti */
6824 si_pi->ulv.supported = false;
6825 si_pi->ulv.pl = *pl;
6826 si_pi->ulv.one_pcie_lane_in_ulv = false;
6827 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6828 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6829 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6832 if (pi->min_vddc_in_table > pl->vddc)
6833 pi->min_vddc_in_table = pl->vddc;
6835 if (pi->max_vddc_in_table < pl->vddc)
6836 pi->max_vddc_in_table = pl->vddc;
6838 /* patch up boot state */
6839 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6840 u16 vddc, vddci, mvdd;
6841 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6842 pl->mclk = rdev->clock.default_mclk;
6843 pl->sclk = rdev->clock.default_sclk;
6846 si_pi->mvdd_bootup_value = mvdd;
6849 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6850 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6851 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6852 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6853 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6854 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6858 static int si_parse_power_table(struct radeon_device *rdev)
6860 struct radeon_mode_info *mode_info = &rdev->mode_info;
6861 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6862 union pplib_power_state *power_state;
6863 int i, j, k, non_clock_array_index, clock_array_index;
6864 union pplib_clock_info *clock_info;
6865 struct _StateArray *state_array;
6866 struct _ClockInfoArray *clock_info_array;
6867 struct _NonClockInfoArray *non_clock_info_array;
6868 union power_info *power_info;
6869 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6872 u8 *power_state_offset;
6875 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6876 &frev, &crev, &data_offset))
6878 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6880 state_array = (struct _StateArray *)
6881 (mode_info->atom_context->bios + data_offset +
6882 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6883 clock_info_array = (struct _ClockInfoArray *)
6884 (mode_info->atom_context->bios + data_offset +
6885 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6886 non_clock_info_array = (struct _NonClockInfoArray *)
6887 (mode_info->atom_context->bios + data_offset +
6888 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6890 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6891 state_array->ucNumEntries, GFP_KERNEL);
6892 if (!rdev->pm.dpm.ps)
6894 power_state_offset = (u8 *)state_array->states;
6895 for (i = 0; i < state_array->ucNumEntries; i++) {
6897 power_state = (union pplib_power_state *)power_state_offset;
6898 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6899 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6900 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6901 if (!rdev->pm.power_state[i].clock_info)
6903 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6905 kfree(rdev->pm.dpm.ps);
6908 rdev->pm.dpm.ps[i].ps_priv = ps;
6909 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6911 non_clock_info_array->ucEntrySize);
6913 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6914 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6915 clock_array_index = idx[j];
6916 if (clock_array_index >= clock_info_array->ucNumEntries)
6918 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6920 clock_info = (union pplib_clock_info *)
6921 ((u8 *)&clock_info_array->clockInfo[0] +
6922 (clock_array_index * clock_info_array->ucEntrySize));
6923 si_parse_pplib_clock_info(rdev,
6924 &rdev->pm.dpm.ps[i], k,
6928 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6930 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6932 /* fill in the vce power states */
6933 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6935 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6936 clock_info = (union pplib_clock_info *)
6937 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6938 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6939 sclk |= clock_info->si.ucEngineClockHigh << 16;
6940 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6941 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6942 rdev->pm.dpm.vce_states[i].sclk = sclk;
6943 rdev->pm.dpm.vce_states[i].mclk = mclk;
6949 int si_dpm_init(struct radeon_device *rdev)
6951 struct rv7xx_power_info *pi;
6952 struct evergreen_power_info *eg_pi;
6953 struct ni_power_info *ni_pi;
6954 struct si_power_info *si_pi;
6955 struct atom_clock_dividers dividers;
6959 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6962 rdev->pm.dpm.priv = si_pi;
6967 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6969 si_pi->sys_pcie_mask = 0;
6971 si_pi->sys_pcie_mask = mask;
6972 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6973 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6975 si_set_max_cu_value(rdev);
6977 rv770_get_max_vddc(rdev);
6978 si_get_leakage_vddc(rdev);
6979 si_patch_dependency_tables_based_on_leakage(rdev);
6982 eg_pi->acpi_vddci = 0;
6983 pi->min_vddc_in_table = 0;
6984 pi->max_vddc_in_table = 0;
6986 ret = r600_get_platform_caps(rdev);
6990 ret = r600_parse_extended_power_table(rdev);
6994 ret = si_parse_power_table(rdev);
6998 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6999 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
7000 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7001 r600_free_extended_power_table(rdev);
7004 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7005 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7006 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7007 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7008 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7009 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7010 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7011 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7012 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7014 if (rdev->pm.dpm.voltage_response_time == 0)
7015 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7016 if (rdev->pm.dpm.backbias_response_time == 0)
7017 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7019 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
7020 0, false, ÷rs);
7022 pi->ref_div = dividers.ref_div + 1;
7024 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7026 eg_pi->smu_uvd_hs = false;
7028 pi->mclk_strobe_mode_threshold = 40000;
7029 if (si_is_special_1gb_platform(rdev))
7030 pi->mclk_stutter_mode_threshold = 0;
7032 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7033 pi->mclk_edc_enable_threshold = 40000;
7034 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7036 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7038 pi->voltage_control =
7039 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7040 VOLTAGE_OBJ_GPIO_LUT);
7041 if (!pi->voltage_control) {
7042 si_pi->voltage_control_svi2 =
7043 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7045 if (si_pi->voltage_control_svi2)
7046 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7047 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7051 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7052 VOLTAGE_OBJ_GPIO_LUT);
7054 eg_pi->vddci_control =
7055 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7056 VOLTAGE_OBJ_GPIO_LUT);
7057 if (!eg_pi->vddci_control)
7058 si_pi->vddci_control_svi2 =
7059 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7062 si_pi->vddc_phase_shed_control =
7063 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7064 VOLTAGE_OBJ_PHASE_LUT);
7066 rv770_get_engine_memory_ss(rdev);
7068 pi->asi = RV770_ASI_DFLT;
7069 pi->pasi = CYPRESS_HASI_DFLT;
7070 pi->vrc = SISLANDS_VRC_DFLT;
7072 pi->gfx_clock_gating = true;
7074 eg_pi->sclk_deep_sleep = true;
7075 si_pi->sclk_deep_sleep_above_low = false;
7077 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7078 pi->thermal_protection = true;
7080 pi->thermal_protection = false;
7082 eg_pi->dynamic_ac_timing = true;
7084 eg_pi->light_sleep = true;
7085 #if defined(CONFIG_ACPI)
7086 eg_pi->pcie_performance_request =
7087 radeon_acpi_is_pcie_performance_request_supported(rdev);
7089 eg_pi->pcie_performance_request = false;
7092 si_pi->sram_end = SMC_RAM_END;
7094 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7095 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7096 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7097 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7098 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7099 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7100 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7102 si_initialize_powertune_defaults(rdev);
7104 /* make sure dc limits are valid */
7105 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7106 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7107 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7108 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7110 si_pi->fan_ctrl_is_in_default_mode = true;
7115 void si_dpm_fini(struct radeon_device *rdev)
7119 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7120 kfree(rdev->pm.dpm.ps[i].ps_priv);
7122 kfree(rdev->pm.dpm.ps);
7123 kfree(rdev->pm.dpm.priv);
7124 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7125 r600_free_extended_power_table(rdev);
7128 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7131 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7132 struct radeon_ps *rps = &eg_pi->current_rps;
7133 struct ni_ps *ps = ni_get_ps(rps);
7134 struct rv7xx_pl *pl;
7136 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7137 CURRENT_STATE_INDEX_SHIFT;
7139 if (current_index >= ps->performance_level_count) {
7140 seq_printf(m, "invalid dpm profile %d\n", current_index);
7142 pl = &ps->performance_levels[current_index];
7143 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7144 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7145 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7149 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7151 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7152 struct radeon_ps *rps = &eg_pi->current_rps;
7153 struct ni_ps *ps = ni_get_ps(rps);
7154 struct rv7xx_pl *pl;
7156 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7157 CURRENT_STATE_INDEX_SHIFT;
7159 if (current_index >= ps->performance_level_count) {
7162 pl = &ps->performance_levels[current_index];
7167 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7169 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7170 struct radeon_ps *rps = &eg_pi->current_rps;
7171 struct ni_ps *ps = ni_get_ps(rps);
7172 struct rv7xx_pl *pl;
7174 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7175 CURRENT_STATE_INDEX_SHIFT;
7177 if (current_index >= ps->performance_level_count) {
7180 pl = &ps->performance_levels[current_index];