2 * Copyright 2013 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU7_DISCRETE_H
25 #define SMU7_DISCRETE_H
31 #define SMU7_DTE_ITERATIONS 5
32 #define SMU7_DTE_SOURCES 3
33 #define SMU7_DTE_SINKS 1
34 #define SMU7_NUM_CPU_TES 0
35 #define SMU7_NUM_GPU_TES 1
36 #define SMU7_NUM_NON_TES 2
38 struct SMU7_SoftRegisters
40 uint32_t RefClockFrequency;
42 uint32_t FeatureEnables;
43 uint32_t PreVBlankGap;
44 uint32_t VBlankTimeout;
45 uint32_t TrainTimeGap;
47 uint32_t MvddSwitchTime;
48 uint32_t LongestAcpiTrainTime;
51 uint32_t DelayMpllPwron;
52 uint32_t VoltageChangeTimeout;
53 uint32_t HandshakeDisables;
55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
65 uint32_t AverageGraphicsA;
66 uint32_t AverageMemoryA;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
71 uint8_t LClkDpmEnabledLevels;
72 uint8_t PCIeDpmEnabledLevels;
74 uint8_t UVDDpmEnabledLevels;
75 uint8_t SAMUDpmEnabledLevels;
76 uint8_t ACPDpmEnabledLevels;
77 uint8_t VCEDpmEnabledLevels;
79 uint32_t DRAM_LOG_ADDR_H;
80 uint32_t DRAM_LOG_ADDR_L;
81 uint32_t DRAM_LOG_PHY_ADDR_H;
82 uint32_t DRAM_LOG_PHY_ADDR_L;
83 uint32_t DRAM_LOG_BUFF_SIZE;
90 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
92 struct SMU7_Discrete_VoltageLevel
95 uint16_t StdVoltageHiSidd;
96 uint16_t StdVoltageLoSidd;
101 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
103 struct SMU7_Discrete_GraphicsLevel
107 uint32_t MinVddcPhases;
109 uint32_t SclkFrequency;
112 uint16_t ActivityLevel;
114 uint32_t CgSpllFuncCntl3;
115 uint32_t CgSpllFuncCntl4;
116 uint32_t SpllSpreadSpectrum;
117 uint32_t SpllSpreadSpectrum2;
119 uint32_t CcPwrDynRm1;
121 uint8_t DisplayWatermark;
122 uint8_t EnabledForActivity;
123 uint8_t EnabledForThrottle;
126 uint8_t VoltageDownH;
127 uint8_t PowerThrottle;
128 uint8_t DeepSleepDivId;
132 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
134 struct SMU7_Discrete_ACPILevel
138 uint32_t MinVddcPhases;
139 uint32_t SclkFrequency;
141 uint8_t DisplayWatermark;
142 uint8_t DeepSleepDivId;
144 uint32_t CgSpllFuncCntl;
145 uint32_t CgSpllFuncCntl2;
146 uint32_t CgSpllFuncCntl3;
147 uint32_t CgSpllFuncCntl4;
148 uint32_t SpllSpreadSpectrum;
149 uint32_t SpllSpreadSpectrum2;
151 uint32_t CcPwrDynRm1;
154 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
156 struct SMU7_Discrete_Ulv
159 uint32_t CcPwrDynRm1;
161 uint8_t VddcOffsetVid;
166 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
168 struct SMU7_Discrete_MemoryLevel
171 uint32_t MinVddcPhases;
175 uint32_t MclkFrequency;
177 uint8_t EdcReadEnable;
178 uint8_t EdcWriteEnable;
180 uint8_t StutterEnable;
182 uint8_t StrobeEnable;
184 uint8_t EnabledForThrottle;
185 uint8_t EnabledForActivity;
189 uint8_t VoltageDownH;
192 uint16_t ActivityLevel;
193 uint8_t DisplayWatermark;
196 uint32_t MpllFuncCntl;
197 uint32_t MpllFuncCntl_1;
198 uint32_t MpllFuncCntl_2;
199 uint32_t MpllAdFuncCntl;
200 uint32_t MpllDqFuncCntl;
201 uint32_t MclkPwrmgtCntl;
207 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
209 struct SMU7_Discrete_LinkLevel
211 uint8_t PcieGenSpeed;
212 uint8_t PcieLaneCount;
213 uint8_t EnabledForActivity;
220 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
223 struct SMU7_Discrete_MCArbDramTimingTableEntry
225 uint32_t McArbDramTiming;
226 uint32_t McArbDramTiming2;
227 uint8_t McArbBurstTime;
231 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
233 struct SMU7_Discrete_MCArbDramTimingTable
235 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
238 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
240 struct SMU7_Discrete_UvdLevel
242 uint32_t VclkFrequency;
243 uint32_t DclkFrequency;
245 uint8_t MinVddcPhases;
251 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
253 struct SMU7_Discrete_ExtClkLevel
261 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
263 struct SMU7_Discrete_StateInfo
265 uint32_t SclkFrequency;
266 uint32_t MclkFrequency;
267 uint32_t VclkFrequency;
268 uint32_t DclkFrequency;
269 uint32_t SamclkFrequency;
270 uint32_t AclkFrequency;
271 uint32_t EclkFrequency;
272 uint16_t MvddVoltage;
274 uint8_t DisplayWatermark;
285 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
288 struct SMU7_Discrete_DpmTable
290 SMU7_PIDController GraphicsPIDController;
291 SMU7_PIDController MemoryPIDController;
292 SMU7_PIDController LinkPIDController;
294 uint32_t SystemFlags;
297 uint32_t SmioMaskVddcVid;
298 uint32_t SmioMaskVddcPhase;
299 uint32_t SmioMaskVddciVid;
300 uint32_t SmioMaskMvddVid;
302 uint32_t VddcLevelCount;
303 uint32_t VddciLevelCount;
304 uint32_t MvddLevelCount;
306 SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC];
307 // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC];
308 SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI];
309 SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD];
311 uint8_t GraphicsDpmLevelCount;
312 uint8_t MemoryDpmLevelCount;
313 uint8_t LinkLevelCount;
314 uint8_t UvdLevelCount;
315 uint8_t VceLevelCount;
316 uint8_t AcpLevelCount;
317 uint8_t SamuLevelCount;
318 uint8_t MasterDeepSleepControl;
319 uint32_t Reserved[5];
320 // uint32_t SamuDefaultLevel;
322 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
323 SMU7_Discrete_MemoryLevel MemoryACPILevel;
324 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY];
325 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
326 SMU7_Discrete_ACPILevel ACPILevel;
327 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
328 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
329 SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
330 SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU];
331 SMU7_Discrete_Ulv Ulv;
333 uint32_t SclkStepSize;
334 uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];
336 uint8_t UvdBootLevel;
337 uint8_t VceBootLevel;
338 uint8_t AcpBootLevel;
339 uint8_t SamuBootLevel;
344 uint8_t SAMUInterval;
346 uint8_t GraphicsBootLevel;
347 uint8_t GraphicsVoltageChangeEnable;
348 uint8_t GraphicsThermThrottleEnable;
349 uint8_t GraphicsInterval;
351 uint8_t VoltageInterval;
352 uint8_t ThermalInterval;
353 uint16_t TemperatureLimitHigh;
355 uint16_t TemperatureLimitLow;
356 uint8_t MemoryBootLevel;
357 uint8_t MemoryVoltageChangeEnable;
359 uint8_t MemoryInterval;
360 uint8_t MemoryThermThrottleEnable;
361 uint16_t VddcVddciDelta;
363 uint16_t VoltageResponseTime;
364 uint16_t PhaseResponseTime;
366 uint8_t PCIeBootLinkLevel;
367 uint8_t PCIeGenInterval;
376 uint16_t PPM_PkgPwrLimit;
377 uint16_t PPM_TemperatureLimit;
385 uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
386 uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
388 uint8_t DTEAmbientTempBase;
399 uint32_t BAPM_TEMP_GRADIENT;
401 uint32_t LowSclkInterruptT;
404 typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
406 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
407 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
409 struct SMU7_Discrete_MCRegisterAddress
415 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
417 struct SMU7_Discrete_MCRegisterSet
419 uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
422 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
424 struct SMU7_Discrete_MCRegisters
428 SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
429 SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
432 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
434 struct SMU7_Discrete_FanTable
450 uint32_t RefreshPeriod;
456 typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
459 struct SMU7_Discrete_PmFuses {
461 uint8_t BapmVddCVidHiSidd[8];
464 uint8_t BapmVddCVidLoSidd[8];
470 uint8_t SviLoadLineEn;
471 uint8_t SviLoadLineVddC;
472 uint8_t SviLoadLineTrimVddC;
473 uint8_t SviLoadLineOffsetVddC;
476 uint16_t TDC_VDDC_PkgLimit;
477 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
481 uint8_t TdcWaterfallCtl;
482 uint8_t LPMLTemperatureMin;
483 uint8_t LPMLTemperatureMax;
487 uint8_t BapmVddCVidHiSidd2[8];
490 int16_t FuzzyFan_ErrorSetDelta;
491 int16_t FuzzyFan_ErrorRateSetDelta;
492 int16_t FuzzyFan_PwmSetDelta;
493 uint16_t CalcMeasPowerBlend;
499 uint8_t GnbLPMLMaxVid;
500 uint8_t GnbLPMLMinVid;
501 uint8_t Reserved1[2];
504 uint16_t BapmVddCBaseLeakageHiSidd;
505 uint16_t BapmVddCBaseLeakageLoSidd;
508 typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;