2 * rcar_du_group.c -- R-Car Display Unit Channels Pair
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
16 * unit, timings generator, ...) and device-global resources (start/stop
17 * control, planes, ...) shared between the two CRTCs.
19 * The R8A7790 introduced a third CRTC with its own set of global resources.
20 * This would be modeled as two separate DU device instances if it wasn't for
21 * a handful or resources that are shared between the three CRTCs (mostly
22 * related to input and output routing). For this reason the R8A7790 DU must be
23 * modeled as a single device with three CRTCs, two sets of "semi-global"
24 * resources, and a few device-global resources.
26 * The rcar_du_group object is a driver specific object, without any real
27 * counterpart in the DU documentation, that models those semi-global resources.
30 #include <linux/clk.h>
33 #include "rcar_du_drv.h"
34 #include "rcar_du_group.h"
35 #include "rcar_du_regs.h"
37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
39 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
44 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
47 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
49 u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
51 /* The DEFR8 register for the first group also controls RGB output
55 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
57 rcar_du_group_write(rgrp, DEFR8, defr8);
60 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
62 /* Enable extended features */
63 rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
64 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
65 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
66 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
67 rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
69 if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS))
70 rcar_du_group_setup_defr8(rgrp);
72 /* Use DS1PR and DS2PR to configure planes priorities and connects the
73 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
75 rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
79 * rcar_du_group_get - Acquire a reference to the DU channels group
81 * Acquiring the first reference setups core registers. A reference must be held
82 * before accessing any hardware registers.
84 * This function must be called with the DRM mode_config lock held.
86 * Return 0 in case of success or a negative error code otherwise.
88 int rcar_du_group_get(struct rcar_du_group *rgrp)
93 rcar_du_group_setup(rgrp);
101 * rcar_du_group_put - Release a reference to the DU
103 * This function must be called with the DRM mode_config lock held.
105 void rcar_du_group_put(struct rcar_du_group *rgrp)
110 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
112 rcar_du_group_write(rgrp, DSYSR,
113 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
114 (start ? DSYSR_DEN : DSYSR_DRES));
117 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
119 /* Many of the configuration bits are only updated when the display
120 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
121 * of those bits could be pre-configured, but others (especially the
122 * bits related to plane assignment to display timing controllers) need
123 * to be modified at runtime.
125 * Restart the display controller if a start is requested. Sorry for the
126 * flicker. It should be possible to move most of the "DRES-update" bits
127 * setup to driver initialization time and minimize the number of cases
128 * when the display controller will have to be restarted.
131 if (rgrp->used_crtcs++ != 0)
132 __rcar_du_group_start_stop(rgrp, false);
133 __rcar_du_group_start_stop(rgrp, true);
135 if (--rgrp->used_crtcs == 0)
136 __rcar_du_group_start_stop(rgrp, false);
140 void rcar_du_group_restart(struct rcar_du_group *rgrp)
142 __rcar_du_group_start_stop(rgrp, false);
143 __rcar_du_group_start_stop(rgrp, true);
146 static int rcar_du_set_dpad0_routing(struct rcar_du_device *rcdu)
150 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
153 /* RGB output routing to DPAD0 is configured in the DEFR8 register of
154 * the first group. As this function can be called with the DU0 and DU1
155 * CRTCs disabled, we need to enable the first group clock before
156 * accessing the register.
158 ret = clk_prepare_enable(rcdu->crtcs[0].clock);
162 rcar_du_group_setup_defr8(&rcdu->groups[0]);
164 clk_disable_unprepare(rcdu->crtcs[0].clock);
169 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
171 struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
172 u32 dorcr = rcar_du_group_read(rgrp, DORCR);
174 dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
176 /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
177 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
180 if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
181 dorcr |= DORCR_PG2D_DS1;
183 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
185 rcar_du_group_write(rgrp, DORCR, dorcr);
187 return rcar_du_set_dpad0_routing(rgrp->dev);