drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

   1 /*
   2  * rcar_du_lvdsenc.c  --  R-Car Display Unit LVDS Encoder
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #include "rcar_du_drv.h"
  21 #include "rcar_du_encoder.h"
  22 #include "rcar_du_lvdsenc.h"
  23 #include "rcar_lvds_regs.h"
  24
  25 struct rcar_du_lvdsenc {
  26         struct rcar_du_device *dev;
  27
  28         unsigned int index;
  29         void __iomem *mmio;
  30         struct clk *clock;
  31         bool enabled;
  32
  33         enum rcar_lvds_input input;
  34 };
  35
  36 static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
  37 {
  38         iowrite32(data, lvds->mmio + reg);
  39 }
  40
  41 static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
  42                                        struct rcar_du_crtc *rcrtc)
  43 {
  44         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  45         unsigned int freq = mode->clock;
  46         u32 lvdcr0;
  47         u32 pllcr;
  48
  49         /* PLL clock configuration */
  50         if (freq < 39000)
  51                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
  52         else if (freq < 61000)
  53                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
  54         else if (freq < 121000)
  55                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
  56         else
  57                 pllcr = LVDPLLCR_PLLDLYCNT_150M;
  58
  59         rcar_lvds_write(lvds, LVDPLLCR, pllcr);
  60
  61         /* Select the input, hardcode mode 0, enable LVDS operation and turn
  62          * bias circuitry on.
  63          */
  64         lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
  65         if (rcrtc->index == 2)
  66                 lvdcr0 |= LVDCR0_DUSEL;
  67         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  68
  69         /* Turn all the channels on. */
  70         rcar_lvds_write(lvds, LVDCR1,
  71                         LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
  72                         LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
  73                         LVDCR1_CLKSTBY_GEN2);
  74
  75         /* Turn the PLL on, wait for the startup delay, and turn the output
  76          * on.
  77          */
  78         lvdcr0 |= LVDCR0_PLLON;
  79         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  80
  81         usleep_range(100, 150);
  82
  83         lvdcr0 |= LVDCR0_LVRES;
  84         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  85 }
  86
  87 static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
  88                                        struct rcar_du_crtc *rcrtc)
  89 {
  90         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  91         unsigned int freq = mode->clock;
  92         u32 lvdcr0;
  93         u32 pllcr;
  94
  95         /* PLL clock configuration */
  96         if (freq < 42000)
  97                 pllcr = LVDPLLCR_PLLDIVCNT_42M;
  98         else if (freq < 85000)
  99                 pllcr = LVDPLLCR_PLLDIVCNT_85M;
 100         else if (freq < 128000)
 101                 pllcr = LVDPLLCR_PLLDIVCNT_128M;
 102         else
 103                 pllcr = LVDPLLCR_PLLDIVCNT_148M;
 104
 105         rcar_lvds_write(lvds, LVDPLLCR, pllcr);
 106
 107         /* Turn all the channels on. */
 108         rcar_lvds_write(lvds, LVDCR1,
 109                         LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
 110                         LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
 111                         LVDCR1_CLKSTBY_GEN3);
 112
 113         /*
 114          * Turn the PLL on, set it to LVDS normal mode, wait for the startup
 115          * delay and turn the output on.
 116          */
 117         lvdcr0 = LVDCR0_PLLON;
 118         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 119
 120         lvdcr0 |= LVDCR0_PWD;
 121         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 122
 123         usleep_range(100, 150);
 124
 125         lvdcr0 |= LVDCR0_LVRES;
 126         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 127 }
 128
 129 static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
 130                                  struct rcar_du_crtc *rcrtc)
 131 {
 132         u32 lvdhcr;
 133         int ret;
 134
 135         if (lvds->enabled)
 136                 return 0;
 137
 138         ret = clk_prepare_enable(lvds->clock);
 139         if (ret < 0)
 140                 return ret;
 141
 142         /* Hardcode the channels and control signals routing for now.
 143          *
 144          * HSYNC -> CTRL0
 145          * VSYNC -> CTRL1
 146          * DISP  -> CTRL2
 147          * 0     -> CTRL3
 148          */
 149         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 150                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 151                         LVDCTRCR_CTR0SEL_HSYNC);
 152
 153         if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES))
 154                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 155                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 156         else
 157                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 158                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 159
 160         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 161
 162         /* Perform generation-specific initialization. */
 163         if (lvds->dev->info->gen < 3)
 164                 rcar_du_lvdsenc_start_gen2(lvds, rcrtc);
 165         else
 166                 rcar_du_lvdsenc_start_gen3(lvds, rcrtc);
 167
 168         lvds->enabled = true;
 169
 170         return 0;
 171 }
 172
 173 static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
 174 {
 175         if (!lvds->enabled)
 176                 return;
 177
 178         rcar_lvds_write(lvds, LVDCR0, 0);
 179         rcar_lvds_write(lvds, LVDCR1, 0);
 180
 181         clk_disable_unprepare(lvds->clock);
 182
 183         lvds->enabled = false;
 184 }
 185
 186 int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
 187                            bool enable)
 188 {
 189         if (!enable) {
 190                 rcar_du_lvdsenc_stop(lvds);
 191                 return 0;
 192         } else if (crtc) {
 193                 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 194                 return rcar_du_lvdsenc_start(lvds, rcrtc);
 195         } else
 196                 return -EINVAL;
 197 }
 198
 199 void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
 200                                   struct drm_display_mode *mode)
 201 {
 202         struct rcar_du_device *rcdu = lvds->dev;
 203
 204         /* The internal LVDS encoder has a restricted clock frequency operating
 205          * range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
 206          * the clock accordingly.
 207          */
 208         if (rcdu->info->gen < 3)
 209                 mode->clock = clamp(mode->clock, 30000, 150000);
 210         else
 211                 mode->clock = clamp(mode->clock, 25175, 148500);
 212 }
 213
 214 static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
 215                                          struct platform_device *pdev)
 216 {
 217         struct resource *mem;
 218         char name[7];
 219
 220         sprintf(name, "lvds.%u", lvds->index);
 221
 222         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 223         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 224         if (IS_ERR(lvds->mmio))
 225                 return PTR_ERR(lvds->mmio);
 226
 227         lvds->clock = devm_clk_get(&pdev->dev, name);
 228         if (IS_ERR(lvds->clock)) {
 229                 dev_err(&pdev->dev, "failed to get clock for %s\n", name);
 230                 return PTR_ERR(lvds->clock);
 231         }
 232
 233         return 0;
 234 }
 235
 236 int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
 237 {
 238         struct platform_device *pdev = to_platform_device(rcdu->dev);
 239         struct rcar_du_lvdsenc *lvds;
 240         unsigned int i;
 241         int ret;
 242
 243         for (i = 0; i < rcdu->info->num_lvds; ++i) {
 244                 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 245                 if (lvds == NULL)
 246                         return -ENOMEM;
 247
 248                 lvds->dev = rcdu;
 249                 lvds->index = i;
 250                 lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
 251                 lvds->enabled = false;
 252
 253                 ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
 254                 if (ret < 0)
 255                         return ret;
 256
 257                 rcdu->lvds[i] = lvds;
 258         }
 259
 260         return 0;
 261 }