2 * rcar_du_regs.h -- R-Car Display Unit Registers Definitions
4 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
13 #ifndef __RCAR_DU_REGS_H__
14 #define __RCAR_DU_REGS_H__
16 #define DISP2_REG_OFFSET 0x30000
18 /* -----------------------------------------------------------------------------
19 * Display Control Registers
22 #define DSYSR 0x00000 /* display 1 */
23 #define D2SYSR 0x30000 /* display 2 */
24 #define DSYSR_ILTS (1 << 29)
25 #define DSYSR_DSEC (1 << 20)
26 #define DSYSR_IUPD (1 << 16)
27 #define DSYSR_DRES (1 << 9)
28 #define DSYSR_DEN (1 << 8)
29 #define DSYSR_TVM_MASTER (0 << 6)
30 #define DSYSR_TVM_SWITCH (1 << 6)
31 #define DSYSR_TVM_TVSYNC (2 << 6)
32 #define DSYSR_TVM_MASK (3 << 6)
33 #define DSYSR_SCM_INT_NONE (0 << 4)
34 #define DSYSR_SCM_INT_SYNC (2 << 4)
35 #define DSYSR_SCM_INT_VIDEO (3 << 4)
39 #define DSMR_VSPM (1 << 28)
40 #define DSMR_ODPM (1 << 27)
41 #define DSMR_DIPM_DISP (0 << 25)
42 #define DSMR_DIPM_CSYNC (1 << 25)
43 #define DSMR_DIPM_DE (3 << 25)
44 #define DSMR_DIPM_MASK (3 << 25)
45 #define DSMR_CSPM (1 << 24)
46 #define DSMR_DIL (1 << 19)
47 #define DSMR_VSL (1 << 18)
48 #define DSMR_HSL (1 << 17)
49 #define DSMR_DDIS (1 << 16)
50 #define DSMR_CDEL (1 << 15)
51 #define DSMR_CDEM_CDE (0 << 13)
52 #define DSMR_CDEM_LOW (2 << 13)
53 #define DSMR_CDEM_HIGH (3 << 13)
54 #define DSMR_CDEM_MASK (3 << 13)
55 #define DSMR_CDED (1 << 12)
56 #define DSMR_ODEV (1 << 8)
57 #define DSMR_CSY_VH_OR (0 << 6)
58 #define DSMR_CSY_333 (2 << 6)
59 #define DSMR_CSY_222 (3 << 6)
60 #define DSMR_CSY_MASK (3 << 6)
64 #define DSSR_VC1FB_DSA0 (0 << 30)
65 #define DSSR_VC1FB_DSA1 (1 << 30)
66 #define DSSR_VC1FB_DSA2 (2 << 30)
67 #define DSSR_VC1FB_INIT (3 << 30)
68 #define DSSR_VC1FB_MASK (3 << 30)
69 #define DSSR_VC0FB_DSA0 (0 << 28)
70 #define DSSR_VC0FB_DSA1 (1 << 28)
71 #define DSSR_VC0FB_DSA2 (2 << 28)
72 #define DSSR_VC0FB_INIT (3 << 28)
73 #define DSSR_VC0FB_MASK (3 << 28)
74 #define DSSR_DFB(n) (1 << ((n)+15))
75 #define DSSR_TVR (1 << 15)
76 #define DSSR_FRM (1 << 14)
77 #define DSSR_VBK (1 << 11)
78 #define DSSR_RINT (1 << 9)
79 #define DSSR_HBK (1 << 8)
80 #define DSSR_ADC(n) (1 << ((n)-1))
83 #define D2SRCR 0x3000c
84 #define DSRCR_TVCL (1 << 15)
85 #define DSRCR_FRCL (1 << 14)
86 #define DSRCR_VBCL (1 << 11)
87 #define DSRCR_RICL (1 << 9)
88 #define DSRCR_HBCL (1 << 8)
89 #define DSRCR_ADCL(n) (1 << ((n)-1))
90 #define DSRCR_MASK 0x0000cbff
94 #define DIER_TVE (1 << 15)
95 #define DIER_FRE (1 << 14)
96 #define DIER_VBE (1 << 11)
97 #define DIER_RIE (1 << 9)
98 #define DIER_HBE (1 << 8)
99 #define DIER_ADCE(n) (1 << ((n)-1))
102 #define CPCR_CP4CE (1 << 19)
103 #define CPCR_CP3CE (1 << 18)
104 #define CPCR_CP2CE (1 << 17)
105 #define CPCR_CP1CE (1 << 16)
108 #define DPPR_DPE(n) (1 << ((n)*4-1))
109 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n))
110 #define DPPR_DPS_SHIFT(n) (((n)-1)*4)
111 #define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */
112 #define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1))
113 #define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2))
114 #define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */
117 #define D2EFR 0x30020
118 #define DEFR_CODE (0x7773 << 16)
119 #define DEFR_EXSL (1 << 12)
120 #define DEFR_EXVL (1 << 11)
121 #define DEFR_EXUP (1 << 5)
122 #define DEFR_VCUP (1 << 4)
123 #define DEFR_DEFE (1 << 0)
125 #define DAPCR 0x00024
126 #define DAPCR_CODE (0x7773 << 16)
127 #define DAPCR_AP2E (1 << 4)
128 #define DAPCR_AP1E (1 << 0)
130 #define DCPCR 0x00028
131 #define DCPCR_CODE (0x7773 << 16)
132 #define DCPCR_CA2B (1 << 13)
133 #define DCPCR_CD2F (1 << 12)
134 #define DCPCR_DC2E (1 << 8)
135 #define DCPCR_CAB (1 << 5)
136 #define DCPCR_CDF (1 << 4)
137 #define DCPCR_DCE (1 << 0)
139 #define DEFR2 0x00034
140 #define D2EFR2 0x30034
141 #define DEFR2_CODE (0x7775 << 16)
142 #define DEFR2_DEFE2G (1 << 0)
144 #define DEFR3 0x00038
145 #define D2EFR3 0x30038
146 #define DEFR3_CODE (0x7776 << 16)
147 #define DEFR3_EVDA (1 << 14)
148 #define DEFR3_EVDM_1 (1 << 12)
149 #define DEFR3_EVDM_2 (2 << 12)
150 #define DEFR3_EVDM_3 (3 << 12)
151 #define DEFR3_VMSM2_EMA (1 << 6)
152 #define DEFR3_VMSM1_ENA (1 << 4)
153 #define DEFR3_DEFE3 (1 << 0)
155 #define DEFR4 0x0003c
156 #define D2EFR4 0x3003c
157 #define DEFR4_CODE (0x7777 << 16)
158 #define DEFR4_LRUO (1 << 5)
159 #define DEFR4_SPCE (1 << 4)
161 #define DVCSR 0x000d0
162 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16))
163 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16))
164 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16))
165 #define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16))
166 #define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16))
167 #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2))
168 #define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2))
169 #define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2))
170 #define DVCSR_VCnFB_INIT(n) (3 << ((n)*2))
171 #define DVCSR_VCnFB_MASK(n) (3 << ((n)*2))
173 #define DEFR5 0x000e0
174 #define DEFR5_CODE (0x66 << 24)
175 #define DEFR5_YCRGB2_DIS (0 << 14)
176 #define DEFR5_YCRGB2_PRI1 (1 << 14)
177 #define DEFR5_YCRGB2_PRI2 (2 << 14)
178 #define DEFR5_YCRGB2_PRI3 (3 << 14)
179 #define DEFR5_YCRGB2_MASK (3 << 14)
180 #define DEFR5_YCRGB1_DIS (0 << 12)
181 #define DEFR5_YCRGB1_PRI1 (1 << 12)
182 #define DEFR5_YCRGB1_PRI2 (2 << 12)
183 #define DEFR5_YCRGB1_PRI3 (3 << 12)
184 #define DEFR5_YCRGB1_MASK (3 << 12)
185 #define DEFR5_DEFE5 (1 << 0)
187 #define DDLTR 0x000e4
188 #define DDLTR_CODE (0x7766 << 16)
189 #define DDLTR_DLAR2 (1 << 6)
190 #define DDLTR_DLAY2 (1 << 5)
191 #define DDLTR_DLAY1 (1 << 1)
193 #define DEFR6 0x000e8
194 #define DEFR6_CODE (0x7778 << 16)
195 #define DEFR6_ODPM22_D2SMR (0 << 10)
196 #define DEFR6_ODPM22_DISP (2 << 10)
197 #define DEFR6_ODPM22_CDE (3 << 10)
198 #define DEFR6_ODPM22_MASK (3 << 10)
199 #define DEFR6_ODPM12_DSMR (0 << 8)
200 #define DEFR6_ODPM12_DISP (2 << 8)
201 #define DEFR6_ODPM12_CDE (3 << 8)
202 #define DEFR6_ODPM12_MASK (3 << 8)
203 #define DEFR6_TCNE2 (1 << 6)
204 #define DEFR6_MLOS1 (1 << 2)
205 #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE2)
207 /* -----------------------------------------------------------------------------
208 * Display Timing Generation Registers
221 #define CLAMPSR 0x00070
222 #define CLAMPWR 0x00074
226 /* -----------------------------------------------------------------------------
227 * Display Attribute Registers
230 #define CP1TR 0x00080
231 #define CP2TR 0x00084
232 #define CP3TR 0x00088
233 #define CP4TR 0x0008c
236 #define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))
238 #define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))
240 #define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))
242 #define RINTOFSR 0x0009c
244 #define DSHPR 0x000c8
245 #define DSHPR_CODE (0x7776 << 16)
246 #define DSHPR_PRIH (0xa << 4)
247 #define DSHPR_PRIL_BPP16 (0x8 << 0)
248 #define DSHPR_PRIL_BPP32 (0x9 << 0)
250 /* -----------------------------------------------------------------------------
251 * Display Plane Registers
254 #define PLANE_OFF 0x00100
256 #define PnMR 0x00100 /* plane 1 */
257 #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */
258 #define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */
259 #define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */
260 #define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */
261 #define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */
262 #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */
263 #define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */
264 #define PnMR_WAE (1 << 16) /* Wrap around Enable */
265 #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */
266 #define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */
267 #define PnMR_SPIM_EOR (2 << 12) /* EOR */
268 #define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */
269 #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */
270 #define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */
271 #define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */
272 #define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */
273 #define PnMR_DC (1 << 7) /* Display Area Change */
274 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
275 #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */
276 #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
277 #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */
278 #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */
279 #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */
280 #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */
281 #define PnMR_DDDF_YC (3 << 0) /* YC */
282 #define PnMR_DDDF_MASK (3 << 0)
284 #define PnMWR 0x00104
286 #define PnALPHAR 0x00108
287 #define PnALPHAR_ABIT_1 (0 << 12)
288 #define PnALPHAR_ABIT_0 (1 << 12)
289 #define PnALPHAR_ABIT_X (2 << 12)
291 #define PnDSXR 0x00110
292 #define PnDSYR 0x00114
293 #define PnDPXR 0x00118
294 #define PnDPYR 0x0011c
296 #define PnDSA0R 0x00120
297 #define PnDSA1R 0x00124
298 #define PnDSA2R 0x00128
299 #define PnDSA_MASK 0xfffffff0
301 #define PnSPXR 0x00130
302 #define PnSPYR 0x00134
303 #define PnWASPR 0x00138
304 #define PnWAMWR 0x0013c
306 #define PnBTR 0x00140
308 #define PnTC1R 0x00144
309 #define PnTC2R 0x00148
310 #define PnTC3R 0x0014c
311 #define PnTC3R_CODE (0x66 << 24)
313 #define PnMLR 0x00150
315 #define PnSWAPR 0x00180
316 #define PnSWAPR_DIGN (1 << 4)
317 #define PnSWAPR_SPQW (1 << 3)
318 #define PnSWAPR_SPLW (1 << 2)
319 #define PnSWAPR_SPWD (1 << 1)
320 #define PnSWAPR_SPBY (1 << 0)
322 #define PnDDCR 0x00184
323 #define PnDDCR_CODE (0x7775 << 16)
324 #define PnDDCR_LRGB1 (1 << 11)
325 #define PnDDCR_LRGB0 (1 << 10)
327 #define PnDDCR2 0x00188
328 #define PnDDCR2_CODE (0x7776 << 16)
329 #define PnDDCR2_NV21 (1 << 5)
330 #define PnDDCR2_Y420 (1 << 4)
331 #define PnDDCR2_DIVU (1 << 1)
332 #define PnDDCR2_DIVY (1 << 0)
334 #define PnDDCR4 0x00190
335 #define PnDDCR4_CODE (0x7766 << 16)
336 #define PnDDCR4_SDFS_RGB (0 << 4)
337 #define PnDDCR4_SDFS_YC (5 << 4)
338 #define PnDDCR4_SDFS_MASK (7 << 4)
339 #define PnDDCR4_EDF_NONE (0 << 0)
340 #define PnDDCR4_EDF_ARGB8888 (1 << 0)
341 #define PnDDCR4_EDF_RGB888 (2 << 0)
342 #define PnDDCR4_EDF_RGB666 (3 << 0)
343 #define PnDDCR4_EDF_MASK (7 << 0)
345 #define APnMR 0x0a100
346 #define APnMR_WAE (1 << 16) /* Wrap around Enable */
347 #define APnMR_DC (1 << 7) /* Display Area Change */
348 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
349 #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
351 #define APnMWR 0x0a104
352 #define APnDSA0R 0x0a120
353 #define APnDSA1R 0x0a124
354 #define APnDSA2R 0x0a128
355 #define APnMLR 0x0a150
357 /* -----------------------------------------------------------------------------
358 * Display Capture Registers
361 #define DCMWR 0x0c104
362 #define DC2MWR 0x0c204
363 #define DCSAR 0x0c120
364 #define DC2SAR 0x0c220
365 #define DCMLR 0x0c150
366 #define DC2MLR 0x0c250
368 /* -----------------------------------------------------------------------------
369 * Color Palette Registers
372 #define CP1_000R 0x01000
373 #define CP1_255R 0x013fc
374 #define CP2_000R 0x02000
375 #define CP2_255R 0x023fc
376 #define CP3_000R 0x03000
377 #define CP3_255R 0x033fc
378 #define CP4_000R 0x04000
379 #define CP4_255R 0x043fc
381 /* -----------------------------------------------------------------------------
382 * External Synchronization Control Registers
386 #define ESCR2 0x31000
387 #define ESCR_DCLKOINV (1 << 25)
388 #define ESCR_DCLKSEL_DCLKIN (0 << 20)
389 #define ESCR_DCLKSEL_CLKS (1 << 20)
390 #define ESCR_DCLKSEL_MASK (1 << 20)
391 #define ESCR_DCLKDIS (1 << 16)
392 #define ESCR_SYNCSEL_OFF (0 << 8)
393 #define ESCR_SYNCSEL_EXVSYNC (2 << 8)
394 #define ESCR_SYNCSEL_EXHSYNC (3 << 8)
395 #define ESCR_FRQSEL_MASK (0x3f << 0)
398 #define OTAR2 0x31004
400 /* -----------------------------------------------------------------------------
401 * Dual Display Output Control Registers
404 #define DORCR 0x11000
405 #define DORCR_PG2T (1 << 30)
406 #define DORCR_DK2S (1 << 28)
407 #define DORCR_PG2D_DS1 (0 << 24)
408 #define DORCR_PG2D_DS2 (1 << 24)
409 #define DORCR_PG2D_FIX0 (2 << 24)
410 #define DORCR_PG2D_DOOR (3 << 24)
411 #define DORCR_PG2D_MASK (3 << 24)
412 #define DORCR_DR1D (1 << 21)
413 #define DORCR_PG1D_DS1 (0 << 16)
414 #define DORCR_PG1D_DS2 (1 << 16)
415 #define DORCR_PG1D_FIX0 (2 << 16)
416 #define DORCR_PG1D_DOOR (3 << 16)
417 #define DORCR_PG1D_MASK (3 << 16)
418 #define DORCR_RGPV (1 << 4)
419 #define DORCR_DPRS (1 << 0)
421 #define DPTSR 0x11004
422 #define DPTSR_PnDK(n) (1 << ((n) + 16))
423 #define DPTSR_PnTS(n) (1 << (n))
425 #define DAPTSR 0x11008
426 #define DAPTSR_APnDK(n) (1 << ((n) + 16))
427 #define DAPTSR_APnTS(n) (1 << (n))
429 #define DS1PR 0x11020
430 #define DS2PR 0x11024
432 /* -----------------------------------------------------------------------------
433 * YC-RGB Conversion Coefficient Registers
438 #define CRNOR 0x11088
439 #define CBNOR 0x1108c
440 #define RCRCR 0x11090
441 #define GCRCR 0x11094
442 #define GCBCR 0x11098
443 #define BCBCR 0x1109c
445 #endif /* __RCAR_DU_REGS_H__ */