2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/iopoll.h>
29 #include <linux/of_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/component.h>
33 #include <linux/reset.h>
34 #include <linux/delay.h>
36 #include "rockchip_drm_drv.h"
37 #include "rockchip_drm_gem.h"
38 #include "rockchip_drm_fb.h"
39 #include "rockchip_drm_psr.h"
40 #include "rockchip_drm_vop.h"
42 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
43 vop_mask_write(x, off, mask, shift, v, write_mask, true)
45 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, false)
48 #define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, \
50 reg.mask, reg.shift, v, reg.write_mask)
51 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, \
53 mask, reg.shift, v, reg.write_mask)
55 #define VOP_WIN_SET(x, win, name, v) \
56 REG_SET(x, win->base, win->phy->name, v, RELAXED)
57 #define VOP_SCL_SET(x, win, name, v) \
58 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
59 #define VOP_SCL_SET_EXT(x, win, name, v) \
60 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
61 #define VOP_CTRL_SET(x, name, v) \
62 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
64 #define VOP_INTR_GET(vop, name) \
65 vop_read_reg(vop, 0, &vop->data->ctrl->name)
67 #define VOP_INTR_SET(vop, name, mask, v) \
68 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
69 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
71 int i, reg = 0, mask = 0; \
72 for (i = 0; i < vop->data->intr->nintrs; i++) { \
73 if (vop->data->intr->intrs[i] & type) { \
78 VOP_INTR_SET(vop, name, mask, reg); \
80 #define VOP_INTR_GET_TYPE(vop, name, type) \
81 vop_get_intr_type(vop, &vop->data->intr->name, type)
83 #define VOP_WIN_GET(x, win, name) \
84 vop_read_reg(x, win->base, &win->phy->name)
86 #define VOP_WIN_GET_YRGBADDR(vop, win) \
87 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
89 #define to_vop(x) container_of(x, struct vop, crtc)
90 #define to_vop_win(x) container_of(x, struct vop_win, base)
97 struct drm_plane base;
98 const struct vop_win_data *data;
103 struct drm_crtc crtc;
105 struct drm_device *drm_dev;
108 /* mutex vsync_ work */
109 struct mutex vsync_mutex;
110 bool vsync_work_pending;
111 struct completion dsp_hold_completion;
113 /* protected by dev->event_lock */
114 struct drm_pending_vblank_event *event;
116 struct drm_flip_work fb_unref_work;
117 unsigned long pending;
119 struct completion line_flag_completion;
121 const struct vop_data *data;
126 /* physical map length of vop register */
129 /* one time only one process allowed to config the register */
131 /* lock vop irq reg */
140 /* vop share memory frequency */
144 struct reset_control *dclk_rst;
146 struct vop_win win[];
149 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
151 writel(v, vop->regs + offset);
152 vop->regsbak[offset >> 2] = v;
155 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
157 return readl(vop->regs + offset);
160 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
161 const struct vop_reg *reg)
163 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
166 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
167 uint32_t mask, uint32_t shift, uint32_t v,
168 bool write_mask, bool relaxed)
174 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
176 uint32_t cached_val = vop->regsbak[offset >> 2];
178 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
179 vop->regsbak[offset >> 2] = v;
183 writel_relaxed(v, vop->regs + offset);
185 writel(v, vop->regs + offset);
188 static inline uint32_t vop_get_intr_type(struct vop *vop,
189 const struct vop_reg *reg, int type)
192 uint32_t regs = vop_read_reg(vop, 0, reg);
194 for (i = 0; i < vop->data->intr->nintrs; i++) {
195 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
196 ret |= vop->data->intr->intrs[i];
202 static inline void vop_cfg_done(struct vop *vop)
204 VOP_CTRL_SET(vop, cfg_done, 1);
207 static bool has_rb_swapped(uint32_t format)
210 case DRM_FORMAT_XBGR8888:
211 case DRM_FORMAT_ABGR8888:
212 case DRM_FORMAT_BGR888:
213 case DRM_FORMAT_BGR565:
220 static enum vop_data_format vop_convert_format(uint32_t format)
223 case DRM_FORMAT_XRGB8888:
224 case DRM_FORMAT_ARGB8888:
225 case DRM_FORMAT_XBGR8888:
226 case DRM_FORMAT_ABGR8888:
227 return VOP_FMT_ARGB8888;
228 case DRM_FORMAT_RGB888:
229 case DRM_FORMAT_BGR888:
230 return VOP_FMT_RGB888;
231 case DRM_FORMAT_RGB565:
232 case DRM_FORMAT_BGR565:
233 return VOP_FMT_RGB565;
234 case DRM_FORMAT_NV12:
235 return VOP_FMT_YUV420SP;
236 case DRM_FORMAT_NV16:
237 return VOP_FMT_YUV422SP;
238 case DRM_FORMAT_NV24:
239 return VOP_FMT_YUV444SP;
241 DRM_ERROR("unsupported format[%08x]\n", format);
246 static bool is_yuv_support(uint32_t format)
249 case DRM_FORMAT_NV12:
250 case DRM_FORMAT_NV16:
251 case DRM_FORMAT_NV24:
258 static bool is_alpha_support(uint32_t format)
261 case DRM_FORMAT_ARGB8888:
262 case DRM_FORMAT_ABGR8888:
269 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
270 uint32_t dst, bool is_horizontal,
271 int vsu_mode, int *vskiplines)
273 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
276 if (mode == SCALE_UP)
277 val = GET_SCL_FT_BIC(src, dst);
278 else if (mode == SCALE_DOWN)
279 val = GET_SCL_FT_BILI_DN(src, dst);
281 if (mode == SCALE_UP) {
282 if (vsu_mode == SCALE_UP_BIL)
283 val = GET_SCL_FT_BILI_UP(src, dst);
285 val = GET_SCL_FT_BIC(src, dst);
286 } else if (mode == SCALE_DOWN) {
288 *vskiplines = scl_get_vskiplines(src, dst);
289 val = scl_get_bili_dn_vskip(src, dst,
292 val = GET_SCL_FT_BILI_DN(src, dst);
300 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
301 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
302 uint32_t dst_h, uint32_t pixel_format)
304 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
305 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
306 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
307 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
308 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
309 bool is_yuv = is_yuv_support(pixel_format);
310 uint16_t cbcr_src_w = src_w / hsub;
311 uint16_t cbcr_src_h = src_h / vsub;
318 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
322 if (!win->phy->scl->ext) {
323 VOP_SCL_SET(vop, win, scale_yrgb_x,
324 scl_cal_scale2(src_w, dst_w));
325 VOP_SCL_SET(vop, win, scale_yrgb_y,
326 scl_cal_scale2(src_h, dst_h));
328 VOP_SCL_SET(vop, win, scale_cbcr_x,
329 scl_cal_scale2(cbcr_src_w, dst_w));
330 VOP_SCL_SET(vop, win, scale_cbcr_y,
331 scl_cal_scale2(cbcr_src_h, dst_h));
336 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
337 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
340 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
341 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
342 if (cbcr_hor_scl_mode == SCALE_DOWN)
343 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
345 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
347 if (yrgb_hor_scl_mode == SCALE_DOWN)
348 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
350 lb_mode = scl_vop_cal_lb_mode(src_w, false);
353 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
354 if (lb_mode == LB_RGB_3840X2) {
355 if (yrgb_ver_scl_mode != SCALE_NONE) {
356 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
359 if (cbcr_ver_scl_mode != SCALE_NONE) {
360 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
363 vsu_mode = SCALE_UP_BIL;
364 } else if (lb_mode == LB_RGB_2560X4) {
365 vsu_mode = SCALE_UP_BIL;
367 vsu_mode = SCALE_UP_BIC;
370 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
372 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
373 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
374 false, vsu_mode, &vskiplines);
375 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
377 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
378 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
380 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
381 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
382 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
383 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
384 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
386 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
387 dst_w, true, 0, NULL);
388 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
389 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
390 dst_h, false, vsu_mode, &vskiplines);
391 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
393 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
394 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
395 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
396 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
397 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
398 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
399 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
403 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
407 if (WARN_ON(!vop->is_enabled))
410 spin_lock_irqsave(&vop->irq_lock, flags);
412 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
413 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
415 spin_unlock_irqrestore(&vop->irq_lock, flags);
418 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
422 if (WARN_ON(!vop->is_enabled))
425 spin_lock_irqsave(&vop->irq_lock, flags);
427 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
429 spin_unlock_irqrestore(&vop->irq_lock, flags);
433 * (1) each frame starts at the start of the Vsync pulse which is signaled by
434 * the "FRAME_SYNC" interrupt.
435 * (2) the active data region of each frame ends at dsp_vact_end
436 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
437 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
439 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
441 * LINE_FLAG -------------------------------+
445 * | Vsync | Vbp | Vactive | Vfp |
449 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
450 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
451 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
452 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
454 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
456 uint32_t line_flag_irq;
459 spin_lock_irqsave(&vop->irq_lock, flags);
461 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
463 spin_unlock_irqrestore(&vop->irq_lock, flags);
465 return !!line_flag_irq;
468 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
472 if (WARN_ON(!vop->is_enabled))
475 spin_lock_irqsave(&vop->irq_lock, flags);
477 VOP_CTRL_SET(vop, line_flag_num[0], line_num);
478 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
479 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
481 spin_unlock_irqrestore(&vop->irq_lock, flags);
484 static void vop_line_flag_irq_disable(struct vop *vop)
488 if (WARN_ON(!vop->is_enabled))
491 spin_lock_irqsave(&vop->irq_lock, flags);
493 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
495 spin_unlock_irqrestore(&vop->irq_lock, flags);
498 static int vop_enable(struct drm_crtc *crtc)
500 struct vop *vop = to_vop(crtc);
503 ret = pm_runtime_get_sync(vop->dev);
505 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
506 goto err_put_pm_runtime;
509 ret = clk_enable(vop->hclk);
510 if (WARN_ON(ret < 0))
511 goto err_put_pm_runtime;
513 ret = clk_enable(vop->dclk);
514 if (WARN_ON(ret < 0))
515 goto err_disable_hclk;
517 ret = clk_enable(vop->aclk);
518 if (WARN_ON(ret < 0))
519 goto err_disable_dclk;
522 * Slave iommu shares power, irq and clock with vop. It was associated
523 * automatically with this master device via common driver code.
524 * Now that we have enabled the clock we attach it to the shared drm
527 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
529 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
530 goto err_disable_aclk;
533 memcpy(vop->regs, vop->regsbak, vop->len);
537 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
539 vop->is_enabled = true;
541 spin_lock(&vop->reg_lock);
543 VOP_CTRL_SET(vop, standby, 0);
545 spin_unlock(&vop->reg_lock);
547 enable_irq(vop->irq);
549 drm_crtc_vblank_on(crtc);
554 clk_disable(vop->aclk);
556 clk_disable(vop->dclk);
558 clk_disable(vop->hclk);
560 pm_runtime_put_sync(vop->dev);
564 static void vop_crtc_disable(struct drm_crtc *crtc)
566 struct vop *vop = to_vop(crtc);
571 rockchip_drm_psr_deactivate(&vop->crtc);
574 * We need to make sure that all windows are disabled before we
575 * disable that crtc. Otherwise we might try to scan from a destroyed
578 for (i = 0; i < vop->data->win_size; i++) {
579 struct vop_win *vop_win = &vop->win[i];
580 const struct vop_win_data *win = vop_win->data;
582 spin_lock(&vop->reg_lock);
583 VOP_WIN_SET(vop, win, enable, 0);
584 spin_unlock(&vop->reg_lock);
589 drm_crtc_vblank_off(crtc);
592 * Vop standby will take effect at end of current frame,
593 * if dsp hold valid irq happen, it means standby complete.
595 * we must wait standby complete when we want to disable aclk,
596 * if not, memory bus maybe dead.
598 reinit_completion(&vop->dsp_hold_completion);
599 vop_dsp_hold_valid_irq_enable(vop);
601 spin_lock(&vop->reg_lock);
603 VOP_CTRL_SET(vop, standby, 1);
605 spin_unlock(&vop->reg_lock);
607 wait_for_completion(&vop->dsp_hold_completion);
609 vop_dsp_hold_valid_irq_disable(vop);
611 disable_irq(vop->irq);
613 vop->is_enabled = false;
616 * vop standby complete, so iommu detach is safe.
618 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
620 clk_disable(vop->dclk);
621 clk_disable(vop->aclk);
622 clk_disable(vop->hclk);
623 pm_runtime_put(vop->dev);
625 if (crtc->state->event && !crtc->state->active) {
626 spin_lock_irq(&crtc->dev->event_lock);
627 drm_crtc_send_vblank_event(crtc, crtc->state->event);
628 spin_unlock_irq(&crtc->dev->event_lock);
630 crtc->state->event = NULL;
634 static void vop_plane_destroy(struct drm_plane *plane)
636 drm_plane_cleanup(plane);
639 static int vop_plane_atomic_check(struct drm_plane *plane,
640 struct drm_plane_state *state)
642 struct drm_crtc *crtc = state->crtc;
643 struct drm_crtc_state *crtc_state;
644 struct drm_framebuffer *fb = state->fb;
645 struct vop_win *vop_win = to_vop_win(plane);
646 const struct vop_win_data *win = vop_win->data;
648 struct drm_rect clip;
649 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
650 DRM_PLANE_HELPER_NO_SCALING;
651 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
652 DRM_PLANE_HELPER_NO_SCALING;
657 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
658 if (WARN_ON(!crtc_state))
663 clip.x2 = crtc_state->adjusted_mode.hdisplay;
664 clip.y2 = crtc_state->adjusted_mode.vdisplay;
666 ret = drm_plane_helper_check_state(state, &clip,
667 min_scale, max_scale,
675 ret = vop_convert_format(fb->format->format);
680 * Src.x1 can be odd when do clip, but yuv plane start point
681 * need align with 2 pixel.
683 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
689 static void vop_plane_atomic_disable(struct drm_plane *plane,
690 struct drm_plane_state *old_state)
692 struct vop_win *vop_win = to_vop_win(plane);
693 const struct vop_win_data *win = vop_win->data;
694 struct vop *vop = to_vop(old_state->crtc);
696 if (!old_state->crtc)
699 spin_lock(&vop->reg_lock);
701 VOP_WIN_SET(vop, win, enable, 0);
703 spin_unlock(&vop->reg_lock);
706 static void vop_plane_atomic_update(struct drm_plane *plane,
707 struct drm_plane_state *old_state)
709 struct drm_plane_state *state = plane->state;
710 struct drm_crtc *crtc = state->crtc;
711 struct vop_win *vop_win = to_vop_win(plane);
712 const struct vop_win_data *win = vop_win->data;
713 struct vop *vop = to_vop(state->crtc);
714 struct drm_framebuffer *fb = state->fb;
715 unsigned int actual_w, actual_h;
716 unsigned int dsp_stx, dsp_sty;
717 uint32_t act_info, dsp_info, dsp_st;
718 struct drm_rect *src = &state->src;
719 struct drm_rect *dest = &state->dst;
720 struct drm_gem_object *obj, *uv_obj;
721 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
722 unsigned long offset;
729 * can't update plane when vop is disabled.
734 if (WARN_ON(!vop->is_enabled))
737 if (!state->visible) {
738 vop_plane_atomic_disable(plane, old_state);
742 obj = rockchip_fb_get_gem_obj(fb, 0);
743 rk_obj = to_rockchip_obj(obj);
745 actual_w = drm_rect_width(src) >> 16;
746 actual_h = drm_rect_height(src) >> 16;
747 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
749 dsp_info = (drm_rect_height(dest) - 1) << 16;
750 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
752 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
753 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
754 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
756 offset = (src->x1 >> 16) * fb->format->cpp[0];
757 offset += (src->y1 >> 16) * fb->pitches[0];
758 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
760 format = vop_convert_format(fb->format->format);
762 spin_lock(&vop->reg_lock);
764 VOP_WIN_SET(vop, win, format, format);
765 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
766 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
767 if (is_yuv_support(fb->format->format)) {
768 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
769 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
770 int bpp = fb->format->cpp[1];
772 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
773 rk_uv_obj = to_rockchip_obj(uv_obj);
775 offset = (src->x1 >> 16) * bpp / hsub;
776 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
778 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
779 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
780 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
784 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
785 drm_rect_width(dest), drm_rect_height(dest),
788 VOP_WIN_SET(vop, win, act_info, act_info);
789 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
790 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
792 rb_swap = has_rb_swapped(fb->format->format);
793 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
795 if (is_alpha_support(fb->format->format)) {
796 VOP_WIN_SET(vop, win, dst_alpha_ctl,
797 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
798 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
799 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
800 SRC_BLEND_M0(ALPHA_PER_PIX) |
801 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
802 SRC_FACTOR_M0(ALPHA_ONE);
803 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
805 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
808 VOP_WIN_SET(vop, win, enable, 1);
809 spin_unlock(&vop->reg_lock);
812 static const struct drm_plane_helper_funcs plane_helper_funcs = {
813 .atomic_check = vop_plane_atomic_check,
814 .atomic_update = vop_plane_atomic_update,
815 .atomic_disable = vop_plane_atomic_disable,
818 static const struct drm_plane_funcs vop_plane_funcs = {
819 .update_plane = drm_atomic_helper_update_plane,
820 .disable_plane = drm_atomic_helper_disable_plane,
821 .destroy = vop_plane_destroy,
822 .reset = drm_atomic_helper_plane_reset,
823 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
824 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
827 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
829 struct vop *vop = to_vop(crtc);
832 if (WARN_ON(!vop->is_enabled))
835 spin_lock_irqsave(&vop->irq_lock, flags);
837 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
838 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
840 spin_unlock_irqrestore(&vop->irq_lock, flags);
845 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
847 struct vop *vop = to_vop(crtc);
850 if (WARN_ON(!vop->is_enabled))
853 spin_lock_irqsave(&vop->irq_lock, flags);
855 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
857 spin_unlock_irqrestore(&vop->irq_lock, flags);
860 static const struct rockchip_crtc_funcs private_crtc_funcs = {
861 .enable_vblank = vop_crtc_enable_vblank,
862 .disable_vblank = vop_crtc_disable_vblank,
865 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
866 const struct drm_display_mode *mode,
867 struct drm_display_mode *adjusted_mode)
869 struct vop *vop = to_vop(crtc);
871 adjusted_mode->clock =
872 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
877 static void vop_crtc_enable(struct drm_crtc *crtc)
879 struct vop *vop = to_vop(crtc);
880 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
881 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
882 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
883 u16 hdisplay = adjusted_mode->hdisplay;
884 u16 htotal = adjusted_mode->htotal;
885 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
886 u16 hact_end = hact_st + hdisplay;
887 u16 vdisplay = adjusted_mode->vdisplay;
888 u16 vtotal = adjusted_mode->vtotal;
889 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
890 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
891 u16 vact_end = vact_st + vdisplay;
892 uint32_t pin_pol, val;
897 ret = vop_enable(crtc);
899 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
904 * If dclk rate is zero, mean that scanout is stop,
905 * we don't need wait any more.
907 if (clk_get_rate(vop->dclk)) {
909 * Rk3288 vop timing register is immediately, when configure
910 * display timing on display time, may cause tearing.
912 * Vop standby will take effect at end of current frame,
913 * if dsp hold valid irq happen, it means standby complete.
916 * standby and wait complete --> |----
920 * configure display timing --> |
925 reinit_completion(&vop->dsp_hold_completion);
926 vop_dsp_hold_valid_irq_enable(vop);
928 spin_lock(&vop->reg_lock);
930 VOP_CTRL_SET(vop, standby, 1);
932 spin_unlock(&vop->reg_lock);
934 wait_for_completion(&vop->dsp_hold_completion);
936 vop_dsp_hold_valid_irq_disable(vop);
939 pin_pol = BIT(DCLK_INVERT);
940 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
941 0 : BIT(HSYNC_POSITIVE);
942 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
943 0 : BIT(VSYNC_POSITIVE);
944 VOP_CTRL_SET(vop, pin_pol, pin_pol);
946 switch (s->output_type) {
947 case DRM_MODE_CONNECTOR_LVDS:
948 VOP_CTRL_SET(vop, rgb_en, 1);
949 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
951 case DRM_MODE_CONNECTOR_eDP:
952 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
953 VOP_CTRL_SET(vop, edp_en, 1);
955 case DRM_MODE_CONNECTOR_HDMIA:
956 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
957 VOP_CTRL_SET(vop, hdmi_en, 1);
959 case DRM_MODE_CONNECTOR_DSI:
960 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
961 VOP_CTRL_SET(vop, mipi_en, 1);
963 case DRM_MODE_CONNECTOR_DisplayPort:
964 pin_pol &= ~BIT(DCLK_INVERT);
965 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
966 VOP_CTRL_SET(vop, dp_en, 1);
969 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
972 VOP_CTRL_SET(vop, out_mode, s->output_mode);
974 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
977 VOP_CTRL_SET(vop, hact_st_end, val);
978 VOP_CTRL_SET(vop, hpost_st_end, val);
980 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
983 VOP_CTRL_SET(vop, vact_st_end, val);
984 VOP_CTRL_SET(vop, vpost_st_end, val);
986 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
988 VOP_CTRL_SET(vop, standby, 0);
990 rockchip_drm_psr_activate(&vop->crtc);
993 static bool vop_fs_irq_is_pending(struct vop *vop)
995 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
998 static void vop_wait_for_irq_handler(struct vop *vop)
1004 * Spin until frame start interrupt status bit goes low, which means
1005 * that interrupt handler was invoked and cleared it. The timeout of
1006 * 10 msecs is really too long, but it is just a safety measure if
1007 * something goes really wrong. The wait will only happen in the very
1008 * unlikely case of a vblank happening exactly at the same time and
1009 * shouldn't exceed microseconds range.
1011 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1012 !pending, 0, 10 * 1000);
1014 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1016 synchronize_irq(vop->irq);
1019 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1020 struct drm_crtc_state *old_crtc_state)
1022 struct drm_atomic_state *old_state = old_crtc_state->state;
1023 struct drm_plane_state *old_plane_state;
1024 struct vop *vop = to_vop(crtc);
1025 struct drm_plane *plane;
1028 if (WARN_ON(!vop->is_enabled))
1031 spin_lock(&vop->reg_lock);
1035 spin_unlock(&vop->reg_lock);
1038 * There is a (rather unlikely) possiblity that a vblank interrupt
1039 * fired before we set the cfg_done bit. To avoid spuriously
1040 * signalling flip completion we need to wait for it to finish.
1042 vop_wait_for_irq_handler(vop);
1044 spin_lock_irq(&crtc->dev->event_lock);
1045 if (crtc->state->event) {
1046 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1047 WARN_ON(vop->event);
1049 vop->event = crtc->state->event;
1050 crtc->state->event = NULL;
1052 spin_unlock_irq(&crtc->dev->event_lock);
1054 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1055 if (!old_plane_state->fb)
1058 if (old_plane_state->fb == plane->state->fb)
1061 drm_framebuffer_reference(old_plane_state->fb);
1062 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1063 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1064 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1068 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1069 struct drm_crtc_state *old_crtc_state)
1071 rockchip_drm_psr_flush(crtc);
1074 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1075 .enable = vop_crtc_enable,
1076 .disable = vop_crtc_disable,
1077 .mode_fixup = vop_crtc_mode_fixup,
1078 .atomic_flush = vop_crtc_atomic_flush,
1079 .atomic_begin = vop_crtc_atomic_begin,
1082 static void vop_crtc_destroy(struct drm_crtc *crtc)
1084 drm_crtc_cleanup(crtc);
1087 static void vop_crtc_reset(struct drm_crtc *crtc)
1090 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1093 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1095 crtc->state->crtc = crtc;
1098 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1100 struct rockchip_crtc_state *rockchip_state;
1102 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1103 if (!rockchip_state)
1106 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1107 return &rockchip_state->base;
1110 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1111 struct drm_crtc_state *state)
1113 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1115 __drm_atomic_helper_crtc_destroy_state(&s->base);
1119 static const struct drm_crtc_funcs vop_crtc_funcs = {
1120 .set_config = drm_atomic_helper_set_config,
1121 .page_flip = drm_atomic_helper_page_flip,
1122 .destroy = vop_crtc_destroy,
1123 .reset = vop_crtc_reset,
1124 .atomic_duplicate_state = vop_crtc_duplicate_state,
1125 .atomic_destroy_state = vop_crtc_destroy_state,
1128 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1130 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1131 struct drm_framebuffer *fb = val;
1133 drm_crtc_vblank_put(&vop->crtc);
1134 drm_framebuffer_unreference(fb);
1137 static void vop_handle_vblank(struct vop *vop)
1139 struct drm_device *drm = vop->drm_dev;
1140 struct drm_crtc *crtc = &vop->crtc;
1141 unsigned long flags;
1143 spin_lock_irqsave(&drm->event_lock, flags);
1145 drm_crtc_send_vblank_event(crtc, vop->event);
1146 drm_crtc_vblank_put(crtc);
1149 spin_unlock_irqrestore(&drm->event_lock, flags);
1151 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1152 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1155 static irqreturn_t vop_isr(int irq, void *data)
1157 struct vop *vop = data;
1158 struct drm_crtc *crtc = &vop->crtc;
1159 uint32_t active_irqs;
1160 unsigned long flags;
1164 * interrupt register has interrupt status, enable and clear bits, we
1165 * must hold irq_lock to avoid a race with enable/disable_vblank().
1167 spin_lock_irqsave(&vop->irq_lock, flags);
1169 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1170 /* Clear all active interrupt sources */
1172 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1174 spin_unlock_irqrestore(&vop->irq_lock, flags);
1176 /* This is expected for vop iommu irqs, since the irq is shared */
1180 if (active_irqs & DSP_HOLD_VALID_INTR) {
1181 complete(&vop->dsp_hold_completion);
1182 active_irqs &= ~DSP_HOLD_VALID_INTR;
1186 if (active_irqs & LINE_FLAG_INTR) {
1187 complete(&vop->line_flag_completion);
1188 active_irqs &= ~LINE_FLAG_INTR;
1192 if (active_irqs & FS_INTR) {
1193 drm_crtc_handle_vblank(crtc);
1194 vop_handle_vblank(vop);
1195 active_irqs &= ~FS_INTR;
1199 /* Unhandled irqs are spurious. */
1201 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1207 static int vop_create_crtc(struct vop *vop)
1209 const struct vop_data *vop_data = vop->data;
1210 struct device *dev = vop->dev;
1211 struct drm_device *drm_dev = vop->drm_dev;
1212 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1213 struct drm_crtc *crtc = &vop->crtc;
1214 struct device_node *port;
1219 * Create drm_plane for primary and cursor planes first, since we need
1220 * to pass them to drm_crtc_init_with_planes, which sets the
1221 * "possible_crtcs" to the newly initialized crtc.
1223 for (i = 0; i < vop_data->win_size; i++) {
1224 struct vop_win *vop_win = &vop->win[i];
1225 const struct vop_win_data *win_data = vop_win->data;
1227 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1228 win_data->type != DRM_PLANE_TYPE_CURSOR)
1231 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1232 0, &vop_plane_funcs,
1233 win_data->phy->data_formats,
1234 win_data->phy->nformats,
1235 win_data->type, NULL);
1237 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1239 goto err_cleanup_planes;
1242 plane = &vop_win->base;
1243 drm_plane_helper_add(plane, &plane_helper_funcs);
1244 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1246 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1250 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1251 &vop_crtc_funcs, NULL);
1253 goto err_cleanup_planes;
1255 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1258 * Create drm_planes for overlay windows with possible_crtcs restricted
1259 * to the newly created crtc.
1261 for (i = 0; i < vop_data->win_size; i++) {
1262 struct vop_win *vop_win = &vop->win[i];
1263 const struct vop_win_data *win_data = vop_win->data;
1264 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1266 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1269 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1272 win_data->phy->data_formats,
1273 win_data->phy->nformats,
1274 win_data->type, NULL);
1276 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1278 goto err_cleanup_crtc;
1280 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1283 port = of_get_child_by_name(dev->of_node, "port");
1285 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1286 dev->of_node->full_name);
1288 goto err_cleanup_crtc;
1291 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1292 vop_fb_unref_worker);
1294 init_completion(&vop->dsp_hold_completion);
1295 init_completion(&vop->line_flag_completion);
1297 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1302 drm_crtc_cleanup(crtc);
1304 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1306 drm_plane_cleanup(plane);
1310 static void vop_destroy_crtc(struct vop *vop)
1312 struct drm_crtc *crtc = &vop->crtc;
1313 struct drm_device *drm_dev = vop->drm_dev;
1314 struct drm_plane *plane, *tmp;
1316 rockchip_unregister_crtc_funcs(crtc);
1317 of_node_put(crtc->port);
1320 * We need to cleanup the planes now. Why?
1322 * The planes are "&vop->win[i].base". That means the memory is
1323 * all part of the big "struct vop" chunk of memory. That memory
1324 * was devm allocated and associated with this component. We need to
1325 * free it ourselves before vop_unbind() finishes.
1327 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1329 vop_plane_destroy(plane);
1332 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1333 * references the CRTC.
1335 drm_crtc_cleanup(crtc);
1336 drm_flip_work_cleanup(&vop->fb_unref_work);
1339 static int vop_initial(struct vop *vop)
1341 const struct vop_data *vop_data = vop->data;
1342 const struct vop_reg_data *init_table = vop_data->init_table;
1343 struct reset_control *ahb_rst;
1346 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1347 if (IS_ERR(vop->hclk)) {
1348 dev_err(vop->dev, "failed to get hclk source\n");
1349 return PTR_ERR(vop->hclk);
1351 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1352 if (IS_ERR(vop->aclk)) {
1353 dev_err(vop->dev, "failed to get aclk source\n");
1354 return PTR_ERR(vop->aclk);
1356 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1357 if (IS_ERR(vop->dclk)) {
1358 dev_err(vop->dev, "failed to get dclk source\n");
1359 return PTR_ERR(vop->dclk);
1362 ret = clk_prepare(vop->dclk);
1364 dev_err(vop->dev, "failed to prepare dclk\n");
1368 /* Enable both the hclk and aclk to setup the vop */
1369 ret = clk_prepare_enable(vop->hclk);
1371 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1372 goto err_unprepare_dclk;
1375 ret = clk_prepare_enable(vop->aclk);
1377 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1378 goto err_disable_hclk;
1382 * do hclk_reset, reset all vop registers.
1384 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1385 if (IS_ERR(ahb_rst)) {
1386 dev_err(vop->dev, "failed to get ahb reset\n");
1387 ret = PTR_ERR(ahb_rst);
1388 goto err_disable_aclk;
1390 reset_control_assert(ahb_rst);
1391 usleep_range(10, 20);
1392 reset_control_deassert(ahb_rst);
1394 memcpy(vop->regsbak, vop->regs, vop->len);
1396 for (i = 0; i < vop_data->table_size; i++)
1397 vop_writel(vop, init_table[i].offset, init_table[i].value);
1399 for (i = 0; i < vop_data->win_size; i++) {
1400 const struct vop_win_data *win = &vop_data->win[i];
1402 VOP_WIN_SET(vop, win, enable, 0);
1408 * do dclk_reset, let all config take affect.
1410 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1411 if (IS_ERR(vop->dclk_rst)) {
1412 dev_err(vop->dev, "failed to get dclk reset\n");
1413 ret = PTR_ERR(vop->dclk_rst);
1414 goto err_disable_aclk;
1416 reset_control_assert(vop->dclk_rst);
1417 usleep_range(10, 20);
1418 reset_control_deassert(vop->dclk_rst);
1420 clk_disable(vop->hclk);
1421 clk_disable(vop->aclk);
1423 vop->is_enabled = false;
1428 clk_disable_unprepare(vop->aclk);
1430 clk_disable_unprepare(vop->hclk);
1432 clk_unprepare(vop->dclk);
1437 * Initialize the vop->win array elements.
1439 static void vop_win_init(struct vop *vop)
1441 const struct vop_data *vop_data = vop->data;
1444 for (i = 0; i < vop_data->win_size; i++) {
1445 struct vop_win *vop_win = &vop->win[i];
1446 const struct vop_win_data *win_data = &vop_data->win[i];
1448 vop_win->data = win_data;
1454 * rockchip_drm_wait_line_flag - acqiure the give line flag event
1455 * @crtc: CRTC to enable line flag
1456 * @line_num: interested line number
1457 * @mstimeout: millisecond for timeout
1459 * Driver would hold here until the interested line flag interrupt have
1460 * happened or timeout to wait.
1463 * Zero on success, negative errno on failure.
1465 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
1466 unsigned int mstimeout)
1468 struct vop *vop = to_vop(crtc);
1469 unsigned long jiffies_left;
1471 if (!crtc || !vop->is_enabled)
1474 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
1477 if (vop_line_flag_irq_is_enabled(vop))
1480 reinit_completion(&vop->line_flag_completion);
1481 vop_line_flag_irq_enable(vop, line_num);
1483 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1484 msecs_to_jiffies(mstimeout));
1485 vop_line_flag_irq_disable(vop);
1487 if (jiffies_left == 0) {
1488 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1494 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
1496 static int vop_bind(struct device *dev, struct device *master, void *data)
1498 struct platform_device *pdev = to_platform_device(dev);
1499 const struct vop_data *vop_data;
1500 struct drm_device *drm_dev = data;
1502 struct resource *res;
1506 vop_data = of_device_get_match_data(dev);
1510 /* Allocate vop struct and its vop_win array */
1511 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1512 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1517 vop->data = vop_data;
1518 vop->drm_dev = drm_dev;
1519 dev_set_drvdata(dev, vop);
1523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1524 vop->len = resource_size(res);
1525 vop->regs = devm_ioremap_resource(dev, res);
1526 if (IS_ERR(vop->regs))
1527 return PTR_ERR(vop->regs);
1529 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1533 ret = vop_initial(vop);
1535 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1539 irq = platform_get_irq(pdev, 0);
1541 dev_err(dev, "cannot find irq for vop\n");
1544 vop->irq = (unsigned int)irq;
1546 spin_lock_init(&vop->reg_lock);
1547 spin_lock_init(&vop->irq_lock);
1549 mutex_init(&vop->vsync_mutex);
1551 ret = devm_request_irq(dev, vop->irq, vop_isr,
1552 IRQF_SHARED, dev_name(dev), vop);
1556 /* IRQ is initially disabled; it gets enabled in power_on */
1557 disable_irq(vop->irq);
1559 ret = vop_create_crtc(vop);
1561 goto err_enable_irq;
1563 pm_runtime_enable(&pdev->dev);
1568 enable_irq(vop->irq); /* To balance out the disable_irq above */
1572 static void vop_unbind(struct device *dev, struct device *master, void *data)
1574 struct vop *vop = dev_get_drvdata(dev);
1576 pm_runtime_disable(dev);
1577 vop_destroy_crtc(vop);
1580 const struct component_ops vop_component_ops = {
1582 .unbind = vop_unbind,
1584 EXPORT_SYMBOL_GPL(vop_component_ops);