2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG(off, _mask, s) \
29 #define VOP_REG_MASK(off, _mask, s) \
35 static const uint32_t formats_win_full[] = {
49 static const uint32_t formats_win_lite[] = {
60 static const struct vop_scl_regs rk3036_win_scl = {
61 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
62 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
63 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
64 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
67 static const struct vop_win_phy rk3036_win0_data = {
68 .scl = &rk3036_win_scl,
69 .data_formats = formats_win_full,
70 .nformats = ARRAY_SIZE(formats_win_full),
71 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
72 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
73 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
74 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
75 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
76 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
77 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
78 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
79 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
80 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
83 static const struct vop_win_phy rk3036_win1_data = {
84 .data_formats = formats_win_lite,
85 .nformats = ARRAY_SIZE(formats_win_lite),
86 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
87 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
88 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
89 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
90 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
91 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
92 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
93 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
96 static const struct vop_win_data rk3036_vop_win_data[] = {
97 { .base = 0x00, .phy = &rk3036_win0_data,
98 .type = DRM_PLANE_TYPE_PRIMARY },
99 { .base = 0x00, .phy = &rk3036_win1_data,
100 .type = DRM_PLANE_TYPE_CURSOR },
103 static const int rk3036_vop_intrs[] = {
110 static const struct vop_intr rk3036_intr = {
111 .intrs = rk3036_vop_intrs,
112 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
113 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
114 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
115 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
118 static const struct vop_ctrl rk3036_ctrl_data = {
119 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
120 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
121 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
122 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
123 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
124 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
125 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
126 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
127 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
130 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
131 {RK3036_DSP_CTRL1, 0x00000000},
134 static const struct vop_data rk3036_vop = {
135 .init_table = rk3036_vop_init_reg_table,
136 .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
137 .ctrl = &rk3036_ctrl_data,
138 .intr = &rk3036_intr,
139 .win = rk3036_vop_win_data,
140 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
143 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
144 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
145 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
146 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
147 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
148 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
149 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
150 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
151 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
152 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
153 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
154 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
155 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
156 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
157 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
158 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
159 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
160 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
161 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
162 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
163 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
164 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
167 static const struct vop_scl_regs rk3288_win_full_scl = {
168 .ext = &rk3288_win_full_scl_ext,
169 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
170 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
171 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
172 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
175 static const struct vop_win_phy rk3288_win01_data = {
176 .scl = &rk3288_win_full_scl,
177 .data_formats = formats_win_full,
178 .nformats = ARRAY_SIZE(formats_win_full),
179 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
180 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
181 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
182 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
183 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
184 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
185 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
186 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
187 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
188 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
189 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
190 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
193 static const struct vop_win_phy rk3288_win23_data = {
194 .data_formats = formats_win_lite,
195 .nformats = ARRAY_SIZE(formats_win_lite),
196 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
197 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
198 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
199 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
200 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
201 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
202 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
203 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
204 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
207 static const struct vop_ctrl rk3288_ctrl_data = {
208 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
209 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
210 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
211 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
212 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
213 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
214 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
215 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
216 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
217 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
218 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
219 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
220 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
221 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
222 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
223 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
224 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
225 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
226 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
227 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
230 static const struct vop_reg_data rk3288_init_reg_table[] = {
231 {RK3288_SYS_CTRL, 0x00c00000},
232 {RK3288_DSP_CTRL0, 0x00000000},
233 {RK3288_WIN0_CTRL0, 0x00000080},
234 {RK3288_WIN1_CTRL0, 0x00000080},
235 /* TODO: Win2/3 support multiple area function, but we haven't found
236 * a suitable way to use it yet, so let's just use them as other windows
237 * with only area 0 enabled.
239 {RK3288_WIN2_CTRL0, 0x00000010},
240 {RK3288_WIN3_CTRL0, 0x00000010},
244 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
245 * special support to get alpha blending working. For now, just use overlay
246 * window 3 for the drm cursor.
249 static const struct vop_win_data rk3288_vop_win_data[] = {
250 { .base = 0x00, .phy = &rk3288_win01_data,
251 .type = DRM_PLANE_TYPE_PRIMARY },
252 { .base = 0x40, .phy = &rk3288_win01_data,
253 .type = DRM_PLANE_TYPE_OVERLAY },
254 { .base = 0x00, .phy = &rk3288_win23_data,
255 .type = DRM_PLANE_TYPE_OVERLAY },
256 { .base = 0x50, .phy = &rk3288_win23_data,
257 .type = DRM_PLANE_TYPE_CURSOR },
260 static const int rk3288_vop_intrs[] = {
267 static const struct vop_intr rk3288_vop_intr = {
268 .intrs = rk3288_vop_intrs,
269 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
270 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
271 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
272 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
275 static const struct vop_data rk3288_vop = {
276 .init_table = rk3288_init_reg_table,
277 .table_size = ARRAY_SIZE(rk3288_init_reg_table),
278 .feature = VOP_FEATURE_OUTPUT_RGB10,
279 .intr = &rk3288_vop_intr,
280 .ctrl = &rk3288_ctrl_data,
281 .win = rk3288_vop_win_data,
282 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
285 static const struct vop_ctrl rk3399_ctrl_data = {
286 .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
287 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
288 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
289 .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
290 .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
291 .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
292 .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
293 .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
294 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
295 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
296 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
297 .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
298 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
299 .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
300 .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
301 .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
302 .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
303 .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
304 .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
305 .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
306 .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
307 .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
308 .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
309 .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
310 .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
313 static const int rk3399_vop_intrs[] = {
323 static const struct vop_intr rk3399_vop_intr = {
324 .intrs = rk3399_vop_intrs,
325 .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
326 .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
327 .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
328 .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
331 static const struct vop_reg_data rk3399_init_reg_table[] = {
332 {RK3399_SYS_CTRL, 0x2000f800},
333 {RK3399_DSP_CTRL0, 0x00000000},
334 {RK3399_WIN0_CTRL0, 0x00000080},
335 {RK3399_WIN1_CTRL0, 0x00000080},
336 /* TODO: Win2/3 support multiple area function, but we haven't found
337 * a suitable way to use it yet, so let's just use them as other windows
338 * with only area 0 enabled.
340 {RK3399_WIN2_CTRL0, 0x00000010},
341 {RK3399_WIN3_CTRL0, 0x00000010},
344 static const struct vop_data rk3399_vop_big = {
345 .init_table = rk3399_init_reg_table,
346 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
347 .feature = VOP_FEATURE_OUTPUT_RGB10,
348 .intr = &rk3399_vop_intr,
349 .ctrl = &rk3399_ctrl_data,
351 * rk3399 vop big windows register layout is same as rk3288.
353 .win = rk3288_vop_win_data,
354 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
357 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
358 { .base = 0x00, .phy = &rk3288_win01_data,
359 .type = DRM_PLANE_TYPE_PRIMARY },
360 { .base = 0x00, .phy = &rk3288_win23_data,
361 .type = DRM_PLANE_TYPE_CURSOR},
364 static const struct vop_data rk3399_vop_lit = {
365 .init_table = rk3399_init_reg_table,
366 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
367 .intr = &rk3399_vop_intr,
368 .ctrl = &rk3399_ctrl_data,
370 * rk3399 vop lit windows register layout is same as rk3288,
371 * but cut off the win1 and win3 windows.
373 .win = rk3399_vop_lit_win_data,
374 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
377 static const struct of_device_id vop_driver_dt_match[] = {
378 { .compatible = "rockchip,rk3036-vop",
379 .data = &rk3036_vop },
380 { .compatible = "rockchip,rk3288-vop",
381 .data = &rk3288_vop },
382 { .compatible = "rockchip,rk3399-vop-big",
383 .data = &rk3399_vop_big },
384 { .compatible = "rockchip,rk3399-vop-lit",
385 .data = &rk3399_vop_lit },
388 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
390 static int vop_probe(struct platform_device *pdev)
392 struct device *dev = &pdev->dev;
395 dev_err(dev, "can't find vop devices\n");
399 return component_add(dev, &vop_component_ops);
402 static int vop_remove(struct platform_device *pdev)
404 component_del(&pdev->dev, &vop_component_ops);
409 struct platform_driver vop_platform_driver = {
411 .remove = vop_remove,
413 .name = "rockchip-vop",
414 .of_match_table = of_match_ptr(vop_driver_dt_match),